April 25, 2012
Panel on Next-Generation Codes/Portability
Hank Childs, LBNL
Jeremy Meredith, ORNL
Pat McCormick, LANL
Chris Sewell, LANL
Ken Moreland, SNL
Dept. of Energy Computer Graphics Forum 2012
Panel on Software for Future Architectures
Exascale vis & analysis in a nutshell
Multiple science communities have declared that ExaFLOP-compute capabilities will revolutionize their field
Climate
High EnergyPhysics
Nuclear Physics
NuclearReactors
Fusion
Material Science & Chemistry
Biology
National Security
Exascale vis & analysis in a nutshell
Power is the central issue at the exascale ORNL Jaguar: 2 PFLOPs, 6MW Exascale machine: 1 EFLOP, 20 MW
Every aspect of the machine and the simulation process must be re-thought to minimize power Plenty of other challenges too!! (e.g.
resiliency, memory constraints, etc.)
c/o SciDAC Review 16, February 2010
Exascale vis & analysis in a nutshell
Power is dictating a thrust towards many-core
0.01 0.1 0.2 0.5 1 20
10
20
30
40
50
60
70
80
90
100
Stacked JEDEC 30pj/bit 2018 ($20M)Advanced 7pj/bit Memory ($100M)Enhanced 4pj/bit Advanced Memory ($150M cumulative)Feasible Power Envelope (20MW)
Bytes/FLOP ratio (# bytes per peak FLOP)
Mem
ory
Pow
er
Consum
pti
on in
Megaw
att
s (
MW
)
c/o John Shalf, LBNL
Exascale vis & analysis in a nutshell
Data movement will be a leading cause of power consumption
Exascale: a heterogeneous, distributed memory GigaHz KiloCore MegaNode system
~3
c/o P. Beckman, Argonne
Exascale vis & analysis in a nutshell
We must minimize data movement:
This motivates in situ processing Which means that we likely will be
running on many-core architectures, alongside the simulation
And VTK is not many-core capable… … but technologies are emerging that
are many-core capable.
Within a node
Between nodes
To and from disk
Format for this panel
Hank Childs, intro, 10 minutes Jeremy Meredith, EAVL, 20 minutes Pat McCormick, Scout, 20 minutes Chris Sewell, PISTON, 20 minutes Ken Moreland, DAX, 20 minutes Discussion: 30 minutes
Questions for the panelists
What fundamental problem are you trying to solve?
What are your plans to deal with exascale-specific issues (massive concurrency, distributed memory, memory overhead, fault tolerance)?
What is your philosophy for dealing with ambiguity of the exascale architecture (multiple swim lanes, heterogeneous architectures)?
How is your technology implemented? What is the long-term result for this
effort? (Production software? Research prototype?)
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