Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Numerical Analysis ofAsymmetric Differential Inductors
Masaki Kanemaru, Daisuke Imanishi, Kenichi Okada, and Akira Matsuzawa
Tokyo Institute of Technology, Japan
2008/12/18 M. Kanemaru, Tokyo Tech.
2
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Contents
●Background
●Matrix-Decomposition Technique
●Simulation & Measurement Results
●Summary
2008/12/18 M. Kanemaru, Tokyo Tech.
3
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
BackgroundMiniaturization of CMOS process→Difficulty of characterize on-chip inductors
Degradation of circuit performances
●On-chip differential inductorUsed for LC-VCO, differential LNA, Mixer…Mismatch between left and right halvesdegrades circuit performances.
Accurate modeling of on-chip symmetric inductor→ Extract of asymmetric parameters
2008/12/18 M. Kanemaru, Tokyo Tech.
4
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Symmetric inductor analysis
•3-port symmetric inductor analysis in various operation modes [1]-Circuit parameters are extracted by numerical optimization-Symmetry is assumed in the parameters
•Asymmetric properties are estimated from Y11 and Y22 [2]-The difference is involved in only difference in shunt parasiticcomponents
)Re()Im()Im(1)()(
)(2
diff
diffdiffdiffdiff
222113121123
1323
diff
diffdiff
ZZQZL
YYYYYYYY
IVZ
==∴
−−−+
==
ω
[1] K. Okada, et al., EuMC, Oct. 2007, pp. 520– 523. [2] Y. Aoki, et al., EuMC, Oct. 2007, pp. 339–342.
2008/12/18 M. Kanemaru, Tokyo Tech.
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Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Proposed methodby Matrix-Decomposition Technique
Extract π−type equivalent circuit3port S-parameter
port3(C.T.)
port1 port2
・Physically reliable parameters can be extracted. ・The mismatch can be accurately evaluated.
2008/12/18 M. Kanemaru, Tokyo Tech.
6
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Contents
●Background
●Matrix-Decomposition Technique
●Simulation & Measurement Results
●Summary
2008/12/18 M. Kanemaru, Tokyo Tech.
7
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Overviewsubcmeas YYY +=
vYYi meas
3
2
1
meas
3
2
1=
⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛=
⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛=
vvv
iii
1 2
sub1 sub3 sub2
1 2
3
1 2
3
1 2
3
12
Yc: Inductor core
Ysub: Interlayer-dielectricand Si substrate
●All ports have common voltagesYc can be ignored → Ysub is calculated from Ymeas
●Yc is calculated from Ymeas and Ysub
●Zcore is derived from Yc by converting matrix
2008/12/18 M. Kanemaru, Tokyo Tech.
8
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Calculation of YsubVoltages of each port are equal
⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛+
⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛=
⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛=
⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛
a
a
a
sub
a
a
a
c
a
a
a
meas
3
2
1
vvv
vvv
vvv
iii
YY
Y
meas33meas32meas31sub3 yyyy ++=
Ymeas
Yc
Ysub
→No current flows through zn
=0
⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛=
sub3
sub2
sub1
sub00
0000
yy
yY
meas13meas12meas11sub1 yyyy ++=
meas23meas22meas21sub2 yyyy ++=
2008/12/18 M. Kanemaru, Tokyo Tech.
9
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Conversion of matrix Yc to Zcoresubsmeac YYY −= ′
Matrix Yc is converted into matrix Zcore
zcorez212
121core iZvZ =⎟
⎠⎞
⎜⎝⎛−
−= zMjMjz
ωω
cY
⎟⎠⎞
⎜⎝⎛=⎟
⎠⎞
⎜⎝⎛=⎟
⎠⎞
⎜⎝⎛
−−=⎟
⎠⎞
⎜⎝⎛=
2
1
2
1z
32
31
2
1z i
iii
vvvv
vv
z
z
z
z iv
vYYi c
3
2
1
c
3
2
1=
⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛=
⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛=
vvv
iii
Obtain converting matrix A and B
e.g.)1 2
1 23
z1 z2
123
1 23
z1 z2
12
Define Zcore by 2×2 matrix
⎟⎠⎞⎜
⎝⎛=⎟
⎠⎞⎜
⎝⎛
−−= 0
010
01
11
10
01 BA
BT can be A* AA*=I
BiiAvv == zz
1ccore *)( −= ABYZ
c
c
BYZAvBYZBiZAv
core
corecore
=
==
2008/12/18 M. Kanemaru, Tokyo Tech.
10
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Contents
●Background
●Matrix-Decomposition Technique
●Simulation & Measurement Results
●Summary
2008/12/18 M. Kanemaru, Tokyo Tech.
11
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Mismatch of ground loop
1
3
2
GND
1 2
GND
3
Even
Odd
Flux loss: Only half side Flux loss: Both sides
The inductance mismatch depends on the number of turns.
Each loss is different Mismatch
Each loss is almost equal Mismatch
2008/12/18 M. Kanemaru, Tokyo Tech.
12
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Simulation model
・Inductance mismatches are evaluated by the proposed method.・The mismatches are plotted as a function of ∆x.
x
2008/12/18 M. Kanemaru, Tokyo Tech.
13
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Simulation Result
∆x (µm)
00 50 100 150
2
4
6
8
10
12
L m
ism
atch
(%) 1 turn
2 turn
200
3 turn
・The mismatch of 2-turn is smaller than 1- and 3-turn ・Increasing ∆x, mismatch decreases
2008/12/18 M. Kanemaru, Tokyo Tech.
14
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Measurement
Line width:9µm, Line space:2µmInner diameter:100µm, Turn:3
0.18 µm Si-CMOS
AsymmetricSymmetric
VNA : 4port 10MHz-67GHzE8361A+N4421BH67(Agilent)
Probe : I67-D-GSGSG-150 (Cascade)I67-GSG-150 (Cascade)
2008/12/18 M. Kanemaru, Tokyo Tech.
15
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Measurement Result
1.00.5
0.6
0.7
0.8
Frequency [GHz]
Indu
ctan
ce [n
H]
0.5
0.6
0.7
0.8
Indu
ctan
ce [n
H]
10 20 1.0Frequency [GHz]
10 20
left-halfright-half
left-halfright-half
Mismatch1.5% 4.0%
Symmetric Asymmetric
・ Influence of asymmetric ground loop is extracted ・Other reasons to cause asymmetry exist
2008/12/18 M. Kanemaru, Tokyo Tech.
16
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Contents
●Background
●Matrix-Decomposition Technique
● Simulation & Measurement Results
●Summary
2008/12/18 M. Kanemaru, Tokyo Tech.
17
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Summary
The numerical analysis using the matrix-decomposition technique is proposed
・Physically reliable parameter can be extracted ・The mismatch can be accurately evaluated
Proposed method is applied to 1-, 2-, and 3-turn differential inductors
Influence of asymmetric ground loop can be accurately extracted
2008/12/18 M. Kanemaru, Tokyo Tech.
18
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Q factor
AsymmetricSymmetric
2008/12/18 M. Kanemaru, Tokyo Tech.
19
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Extract Ymeas’
Ymeas
・Zshort and Yopen are removed by Open-Short de-embedding1
openshort1
openmeassmea )()( −−′ −−−= YZYYZ
1smeasmea−′′ = ZY
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