NSQF QUALIFICATION FILE Version 6: Draft of 08 March 2016
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NSQF QUALIFICATION FILE Version 6: Draft of 08 March 2016
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CONTACT DETAILS OF THE BODY SUBMITTING THE QUALIFICATION FILE
Name and address of submitting body:
Ministry of Micro, Small and Medium Enterprises
UdyogBhawan,
Rafi Marg,
New Delhi - 110011
Name and contact details of individual dealing with the submission
Name : Mr.Sujayat Khan
Position in the Organization : Principal Director
Address if different from above Central Institute of Tool Design
Tel number : 040-23774536/2658
E-mail address :[email protected]
List of documents submitted in support of the Qualifications File
1. PGDVES_CURRICULUM FORMAT
2. Summery Sheet of Industry vetting
3. Summery Sheet of Qualification file
NSQF QUALIFICATION FILE Version 6: Draft of 08 March 2016
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SUMMARY
Qualification Title Post Graduate Diploma in VLSI & Embedded
Systems
Qualification Code MSME / PGDVE /14
Nature and purpose of the
qualification
Nature: Certificate course of Post Graduate Diploma in
VLSI & Embedded Systems
Purpose: Learners who attain this qualification are
competent in Electronic sector and deal with
technology change. Learners can Design the chip in
ASIC domain and Board Design and can get a job in
VLSI/ES Industry or become an entrepreneur.
Qualifying learners attain skills to work in post
Digital Design Engineer, Physical Design
Engineer, Synthesis Engineer, Verification
Engineer, Embedded Engineer, &
Programming Engineer.
Qualified learners are capable of designing the
logic, system level modeling, capable of layout
design, generating the netlist from HDL
Programme, capable of verifying the logic of
any module in the design, and capable of
compiling and deployment of compiled file into
embedded hardware.
Body/bodies which will
award the qualification
MSME-Technology Center, Ministry of Micro, Small
& Medium Enterprises, New Delhi.
Body which will accredit
providers to offer courses
leading to the qualification
MSME-Technology Center, Ministry of Micro, Small
& Medium Enterprises, New Delhi.
Body/bodies which will
carry out assessment of
learners
MSME-Technology Center, Ministry of Micro, Small
& Medium Enterprises, New Delhi.
Occupation(s) to which the
qualification gives access
Digital Design Engineer or Physical Design Engineer or
Synthesis Engineer or Verification Engineer or
Embedded Engineer or Programming Engineer
Licensing requirements Not Applicable
Level of the qualification in
the NSQF
8
Anticipated volume of
training/learning required to
complete the qualification
Total : 2340 hours
Entry requirements and/or
recommendations
Bachelor of Engineering / Bachelor of Technology in
Electronics and Communication/Electrical and
Electronics/Instrumentation or its equivalent.
Progression from the
qualification
Job Progression:
After completion of course and after 6 months of
NSQF QUALIFICATION FILE Version 6: Draft of 08 March 2016
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Industry Intership the trainee can work as a Digital
Design Engineer or Physical Design Engineer or
Synthesis Engineer or Verification Engineer or
Embedded Engineer or Programming Engineer and
after 3 years of experience the person can work as Full
chip Integration Engineer.
Education progression:
M.Tech. (VLSI System Design) programme is a next
stage of progression in education to the trainee.
Planned arrangements for
the Recognition of Prior
learning (RPL)
Yes
International comparability
where known
UCSC Silicon Valley Extension California (CA) offers
Very Large Scale Integration (VLSI) & Embedded
Engineering Certificate Program for professionals
working in the integrated circuit.
(http://www.ucsc-extension.edu/content/contact-
information)
Date of planned review of
the qualification.
01/2018
Formal structure of the
qualification
Post Graduate Diploma in
VLSI & Embedded Systems
Mandatory/
Optional
Estimated size
(learning
hours)
Level
Digital VLSI Design Mandatory 110 Hrs 7
CMOS Analog Integrated Circuit
Design
Mandatory 110 Hrs 7
Physics Of Semiconductor
Device
Mandatory 104 Hrs 8
Advanced Digital Signal
Processing
Mandatory 110 Hrs 8
Advanced Logic Synthesis Mandatory 110 Hrs 8
Artificial Neural Networks Mandatory 110 Hrs 8
Microcontrollers For
Embedded System Design Mandatory 110 Hrs 5
Embedded Real Time Operating
Systems Mandatory 110 Hrs 7
Advanced Operating Systems Mandatory 110 Hrs 8
Embedded Computing Systems Mandatory 110 Hrs 7
Computer Networks Mandatory 112 Hrs 7
Industry Internship Mandatory 1134 Hrs 8
Total 2340 Hrs
NSQF QUALIFICATION FILE Version 6: Draft of 08 March 2016
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SECTION 1
ASSESSMENT
Body/Bodies which will carry out assessment:
Assessment for the Post Graduate Diploma in VLSI & Embedded Systems is conducted in
Examination Cell of CITD, Hyderabad.
Will the assessment body be responsible for RPL assessment?
YES. Learners who have met the requirements of any Unit Standard that forms part of this
qualification may apply for recognition of prior learning to the relevant Education body. The
applicant must be assessed against the specific outcomes and with the assessment criteria for the
relevant Unit Standards.
Describe the overall assessment strategy and specific arrangements which have been put
in place to ensure that assessment is always valid, consistent and fair and show that these
are in line with the requirements of the NSQF:
1. ASSESSMENT GUIDELINE:
- Criteria for assessment based on each learning outcomes, will be assigned marks proportional
to its importance.
- The assessment for the theory &practical part is based on knowledge bank of questions created
by trainers and approved by Examination cell (CITD Hyderabad)
- For each Individual batch, Examination cell will create unique question papers for theory part
as well as practical for each candidate at each examination.
To pass the Qualification, every trainee should score a minimum of 75% cumulatively (Theory
and Practical)
- Assessment comprises the following components:
>Job carried out in labs
>Record book/ daily diary
>Answer sheet of assessment
>Viva –voce
>Marks sheet
>Attendance and punctuality
2. ASSESSORS:
CITD faculty teaching the Post Graduate Diploma in VLSI & Embedded Systems course, also
assesses the students as per guidelines set by Examination cell of CITD. Faculties are been trained
from time to time to upgrade their skills on various aspects such as conduction of assessments,
teaching methodology etc. These training are usually conducted at C-DAC Hyderabad.
3. ELIGIBILITY TO APPEAR IN THE EXAM:
Minimum 75% attendance is compulsory for the students to appear for the assessments.
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4. MARKING SCHEME:
Sr. No. Method of Assessments Weightage (Max. marks) Evaluator
1 Written test 40 Trainer + Head of ESDM
Dept. + Examiner
nominated by
Examination cell (CITD)
2 Practical test 20
3 Oral test/viva voce 10
4 Project 20
5 Direct Observation 10
Total 100
5. PASSING MARKS:
Passing criteria is based on marks obtain in attendance record, term works , assignments,
practical’s performance, viva or oral exam, module test, practical exam and final exam
Minimum Marks to pass practical exam – 60%
Minimum Marks to pass final exam – 40%
6. RESULTS AND CERTIFICATION:
The assessment results are backed by evidences collected by assessors. Successful trainees
are awarded the certificates by CITD.
ASSESSMENT EVIDENCE
Assessment evidence comprises the following components document in the form of records:
1) Job carried out in labs
2) Record book/ daily diary
3) Answer sheet of assessment
4) Viva –voce
5) Marks sheet
6) Attendance and punctuality
Title of Component: Post Graduate Diploma in VLSI & Embedded Systems
Sr.
No.
Outcomes to be assessed Assessment criteria for the outcome
1 Demonstrate the Various
Digital Circuits in VLSI.
The candidate should able to;
1.1 Describe the different VLSI Technologies
1.2 Design the Digital circuits using Combinational and
Sequential elements.
1.3 Draw the Layouts of Logical Cells and other logics.
1.4 Describe the different methodologies in System
Design.
1.5 Design the different types of Adders and Simple ALU.
1.6 Describe and Design the different types of Memories
like SRAM, DRAM.
1.7 Dynamic and clocked CMOS inverters.
1.8 Clocking strategies, single and two phase clocking,
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clock distribution.
1.9 Scaling of MOS circuits.
1.10 Implementation of Boolean functions using basic gates synchronous and Asynchronous sequential circuits.
1.11 Flip Flops, registers.
1.12 Counters Mealy and Moore state machines.
1.13 Mos circuit designs layer representation.
1.14 CMOS Design rules-spacing and dimensions checks stick diagrams layouts of basic gates using different CMOS logics.
1.15 Estimation of delay in NMOS and CMOS inverters. Driving of large capacitive loads super buffers. Estimation of power.
1.16 Power reduction techniques.
1.17 Design description domains and design strategies-Hierarchy, regularity, Modularity.
1.18 Locality Design methods Behavioral synthesis RTL synthesis logic optimization structural to Layout structural to layout synthesis- placement, routing.
1.19 Issues in subsystem design.
1.20 carry select adder design of simple ALU, Shifters-Array shifters using transmission gates.
1.21 Static RAM-four transistor SRAM cell.
1.22 Six transistor SRAM cell.
2 Demonstrate the Design the
CMOS Analog Integrated
Circuits.
The candidate should able to;
2.1 Describe the MOS devices and types of Single Stage
Amplifiers.
2.2 Describe the types of Differential Amplifiers.
2.3 Describe the types of Current mirrors and Current
sources.
2.4 Describe the working of Operational Amplifiers.
2.5 Demonstrate how to use the Differential Amplifiers in
the different modes.
2.6 Describe the different types of Feedback circuits.
2.7 Describe the Frequency compensation Techniques.
2.8 Describe the A/D and D/A circuits by using the
Operational Amplifiers.
3 Demonstrate the study of
Physics of Semiconductor
Devices.
The candidate should able to;
3.1 Describe the Quantum mechanics.
3.2 Lattices, E-k diagrams
3.3 Quasiparticles in semiconductors
3.4 electrons, holes and phonons.
3.5 Boltzmann transport equation and solution in the
presence of low electric and magnetic fields.
3.6 mobility and diffusivity.
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3.7 Poisson's equation and their solution.
3.8 Hot carriers and avalanche breakdown.
3.9 homo- and hetero-junction band diagrams and I-
Characteristics.
3.10 Two terminal and surface states devices based on semiconductor junctions.
3.11 The ideal and Non ideal MOS capacitor band diagrams and CVs.
3.12 Effects of oxide charges.
3.13 Characterization of MOS capacitors.
3.14 High field effects and breakdown.
4 Using the Advanced Digital
Signal Processing
The candidate should able to;
4.1 Design the different types of filters like DFT, FFT, IIR
and FIR.
4.2 Decimation by a factor D.
4.3 Multistage Implementation of Sampling Rate
Conversion.
4.4 Filter design & Implementation for sampling rate
conversion.
4.5Non-Parametric methods of Power Spectral
Estimation.
4.6Estimation of spectra from finite duration observation
of signals.
4.7 Bartlett, Welch & Blackman & Tukey methods,
Comparison of all Non-Parametric methods.
4.8 Parametric Methods of Power Spectrum Estimation.
4.9 Relation between auto correlation & model
parameters.
4.10 Forward and Backward Linear Prediction.
4.11 Optimum reflection coefficients for the Lattice
Forward and Backward Predictors.
4.12 Solution of the Normal Equations: Levinson Durbin
Algorithm, Schur Algorithm.
4.13 Properties of Linear Prediction Filters.
4.14 Analysis of finite word length effects in Fixed-point DSP systems.
4.15 Fixed, Floating Point Arithmetic.
4.16 ADC quantization noise & signal quality.
4.17 Finite word length effect in IIR digital Filters.
4.18 Finite word-length effects in FFT algorithms.
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5 Demonstrate the Procedure
for Advanced Logic Synthesis.
The candidate should able to;
5.1 Optimize the Boolean equations by using the K-Maps
and Tabular and other methods.
5.2 Describe the Sequential Logic Synthesis.
5.3 Describing the use of FSM
5.4 Describing the different techniques in Minimization
and developing the FSM.
5.5 Minimization using Merger graph.
5.6 Merger Table, closed covering.
5.7Binate covering problem.
5.8FSM traversal algorithms.
5.9Depth first search.
5.10 Breadth first search.
5.11 shortest path. State encoding and optimization.
5.12 multilevel logic syntheses.
5.13 Introduction, Algebraic and Boolean Division.
5.14Kernels and Cokernels.
5.15Algebraic and Boolean resubtitution methods.
5.16Technology mapping.
5.17Graph covering and Technology mapping.
5.18Tree covering by Dynamic programming, Decomposition. Delay optimization and Graph covering.
6 Demonstrate the Designing of
Artificial Neural Networks
The candidate able to;
6.1 Understand the Basic Artificial Neural Networks.
6.2 Describe the Typical Applications of Artificial Neural
Networks (ANN)
6.3 Describe and use the different architectures and
Algorithms.
6.4 Describe the counter propagation networks and
principal component analysis.
6.5Multi-layer networks-Architecture.
6.6Back Propagation Algorithm (BTA) and other Training
algorithms, Applications.
6.7Adaptive Multi-layer networks-Architecture, training
algorithms;
6.8Recurrent Networks.
6.9 Feed-forward networks.
6.10 Radial-Basis-Function (RBF) networks.
6.11Unsupervised Learning.
6.12Winner-takes-all networks.
6.13Hamming networks, Maxnet.
6.14Simple Competitive learning.
6.15Vector-Quantization.
6.16 Counter propagation networks.
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6.17Adaptive Resonance Theory.
6.18 Kohonen's Self-organizing Maps.
6.19Principal Component Analysis.
6.20Hopfield Networks.
6.21Brain-in-a-Box network.
6.22Boltzmann machine.
6.23Hopfield Networks for-TSP, Solution of simultaneous linear equations.
6.24Iterated Gradient Descent.
6.25 Simulated Annealing; Genetic Algorithm.
7 Demonstrate the Micro
controllers for Embedded
System Design
The candidate should able to
7.1 Describe the Process of Embedded design and
Hardware devices for Embedded system.
7.2 Describe the 8051 and PIC Architecture and design
the interfacing system for 8051 and PIC micro
controllers.
7.3 Demonstrate the I/O Devices of 8051 and PIC Micro
controllers.
7.4 Describe the PSOC architecture and programming the
PSOC.
7.5 Demonstrate the various blocks like Capacitor, I/O
and Digital.
Demonstrate the ARM processor Architecture.
7.6 Capable of using the Interrupts and Device Drivers
like Serial Port Device drivers, Device drivers for Internal
Programmable timing Devices etc.
7.7 Describe the different Network Protocols.
8 Develop a Real Time
Operating System for
Embedded Devices.
The Candidate should able to;
8.1 Interfaces with the UNIX Operating System.
8.2 Develop a program in UNIX environment.
8.3 Use the Temporal parameters and Periodic task
model etc. while developing the code.
8.4 Establish a communication path between the devices
with the programs.
8.5 Describe the RTOS Environment.
8.6 Work with VX Works and Develop a system using the
VX Works.
8.9 Case study of Programming with RTOS for Automatic
Chocolate Vending Machine.
8.10 Use different types of Networking Protocols.
9 Demonstrate the Advance
Operating System Techniques.
The Candidate should able to;
9.1 Describe the Computer system Hardware.
9.2 Use the Basic commands of LINUX Operating Systems.
9.3 Describe and Use the Different types of System calls.
9.4 Describe the Distributed Systems.
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9.5 Develop a Communication between Client – Server
model and Remote procedure.
9.6 Synchronize the Distributed Systems.
9.7Commonly used Approaches to Real Time Scheduling Clock Driven, Weighted Round Robin, Priority Driven. 9.8Dynamic Vs State Systems.
9.9Effective release time and Dead lines.
9.10Offline Vs Online Scheduling.
9.11Inter-process Communication and Synchronization of Processes.
9.12Tasks and Threads-Multiple Process in an Application.
9.13 Problem of Sharing data by multiple tasks & routines, Inter-process communication.
9.14Real Time Operating Systems & Programming Tools. 9.15 Operating Systems Services, I/O Subsystems, RT & Embedded Systems OS, Interrupt Routine in RTOS. 9.16Environment Micro C/OS-II- Need of a well Tested & Debugged RTOs.
9.17Use of COS-II.
9.18 VX Works & Case Studies Memory managements task state transition diagram, pre-emptive priority.
9.19 Scheduling context switches- semaphore- Binary mutex, counting watch dugs, I/O system.
9.20 Case Studies of programming with RTOS- Case Study of Automatic Chocolate Vending m/c using COS RTOS.
9.21 case study of sending application Layer byte Streams on a TCP/IP network, Case Study of an Embedded System for a smart card.
10 Demonstrate how to Compute
in Embedded Systems.
The Candidate should able to;
10.1 Demonstrate the Software Design requirements
such as structural and behavioral descriptions.
10.2 Describe the RISC, Super Scalar and VLIW
architecture etc.
10.3 Use of Embedded Bus Architecture.
10.4 Test and optimize the program and do performance
analysis.
10.5 Scheduling and Development of Hardware
Accelerators.
10.6 Describe the FPGA Architecture.
10.7 Develop a Verilog Code for the Designs.
11 Demonstrate the Usage of
different techniques while
establishing the networks
between the Computers.
The Candidate should able to;
11.1 Describe the different Network Topologies like
WAN, LAN and MAN.
11.2 Describe the Network models like OSI and TCP/IP
etc.
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11.3 Demonstrate the Usage of Physical Layer in Network
models.
11.4 Describe the Data link layer in HDLC, Internet and
ATM.
11.5 Describe the ALOHA, MAC, wireless LANS in Medium
Access Sub Layer.
11.6 Describe the different types of Routing algorithms in
Network Layer.
i) Means of assessment 1 and 2
ii) Skill performance is assess by conducting
iii) Assignment for each module
iv) Written test for each module
v) Final exam after completion of all modules
vi) Practical exam for each module
vii) Final practical exam after completion of all modules
viii) Viva / Oral Exam
ix) Project report and presentation
Pass/Fail
Passing criteria is based on marks obtain in attendance record, term works , assignments,
practical’s performance, viva or oral exam, module test, practical exam and final exam
i) Minimum Marks to pass practical exam – 60%
ii) Minimum Marks to pass final exam – 40%
iii) Minimum Marks to pass viva / oral exam –60%
iv) Minimum Marks to pass Project report and presentation exam – 90%
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SECTION 2
EVIDENCE OF LEVEL
Option A
Title/Name of qualification/component: Post Graduate Diploma in VLSI & Embedded Systems:8
NSQF Domain Outcomes of the
Qualification/Component
How the job role relates to the NSQF level descriptors NSQF
Level
Process Commanding on electronic
devices, electronic files and data
safely, securely and according to
specified requirements in a
Procedure of designing of
circuits.
Employs are expected to have a command on the Design flow for specifications and
requirements for a system design of basic creative principles and processes for Tape
out of Design by interpreting Knowledge of Designing the circuits, Developing the
codes, Interfacing the devices and testing the Design to this outcome is pegged at Level
8.
8
Professional
knowledge
Employs should have the
capability of requirements for
System Design (Including
Embedded and VLSI) based on
given specifications of users.
Employ should have factual
Knowledge including the
finding solutions, Designing
the circuits for the
algorithms, Implementing
the algorithms, Developing
circuits, Writing programs
for circuits and devices
interruptions, and Testing
the System etc.
Job holder’s needs to have a practical knowledge of designing principles and
knowledge about the usage of the software such as MATLAB, Cadence, Synopsys and
remaining EDA Tools. Job holders have factual knowledge of field of study which is
designing, programming, testing and Implementing the system. Job holder’s should
have factual Knowledge including the finding solutions, Designing the circuits for the
algorithms, Implementing the algorithms, Developing circuits, Writing programs for
circuits and devices interruptions, and Testing the System. Therefore this is pegged at
level 8.
8
Professional
skill
Wide range of skill should be
there in Designing the
circuits according to design
Job holder is engaged in tasks such as Designing the circuits, simulating the codes,
synthesis the logical codes, drawing layouts, Physical designing and verifying the
constraints. These activities are routine in nature of System designing with narrow
7
Comment [PB1]: The level descriptors are not justified enough
NSQF QUALIFICATION FILE Version 6: Draft of 08 March 2016
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specification of client’s given
data.
Optimizing the system design
in terms of Power area and
timings.
range of application. Hence this is pegged at level 7.
Core skill Evaluated Techniques such
as low power and area
optimized effects against
specified requirements
Manage System Design
production according to
specified requirements.
The jobholder is needs to have Generic Communication Skills. Jobholder needs
Document postproduction requirements. Understand the project requirements/client
requirement which requires clarity in written skills and while working on the content
he needs to be aware of the applications based on the projects. Therefore it is pegged
at level 8.
8
Responsibility Check-up procedures to
ensure that project
objectives are finished
within specified time frames
are developed.
Checkup procedures to
ensure that agreed ethical
and legal requirements are
met are designed.
The compliance of Electronic
system design products with
specified requirements is
ensured.
Products can include
Integrated Circuits (IC),
modems, Interfacing devices,
Complete System design for
Client requirements.
Job holder is required to carry out functions such as designing the circuits, simulating
circuits, Interfacing the devices, synthesizing the design and sign off verification.
Job holder needs to ensure the procedures according to the legal requirement that are
met. He needs to be well aware about different Integrated circuits for different
applications and he should know how to synchronize with other Integrated circuits
for the purpose of complete system design according to the client requirements.
Therefore it is pegged at level 8.
8
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ECTION 3
EVIDENCE OF NEED
What evidence is there that the qualification is needed?
POST GRADUATE DIPLOMA IN VLSI AND EMBEDDED SYSTEMS has been started in the year 2004 and
from then to 2015 total 467 students have been trained and 70% of the placement have been
happened. Hence from this It is evident that POST GRADUATE DIPLOMA IN VLSI AND EMBEDDED
SYSTEMS (PGDVES) is needed.
What is the estimated uptake of this qualification and what is the basis of this estimate?
The electronics industry has recorded very high growth in subsequent years. By 1991, private
investments both foreign and domestic were encouraged. The easing of foreign investment norms,
allowance of 100 percent foreign equity, reduction in custom tariffs, and delicensing of several
consumer electronic products attracted remarkable amount of foreign collaboration and investment.
The domestic industry also responded favorably to the politic policies of the government. The opening
of the electronics field to private sector enabled entrepreneurs to establish industries to meet hitherto
suppressed demand.
Improvements in the electronics industry have not been limited to a particular segment, but
encompass all its sectors. Strides have been made in the areas of commercial electronics, software,
telecommunications, instrumentation, positioning and networking systems, and defense. The result
has been a significant trade growth that began in the late 1990s.
Despite commendable achievements in the sphere of electronics, considerable infrastructural improvements remain a priority. Water, power, telecommunications, and transportation sectors must still be augmented so that high economic growth can be sustained.
The total electronic growth over a ten year period is given below
What steps were taken to ensure that the qualification(s) does/do not duplicate already
existing or planned qualifications in the NSQF?
The qualification is originally designed by curriculum committee comprising the training head,
industrial expert, academic professional experts.
The work group under the guidance of curriculum development committee already conducted desk
search as well as refers the qualification packs for as a supporting document for the mapping of
NSQF QUALIFICATION FILE Version 6: Draft of 08 March 2016
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curriculum.
As per the search it is found that, the certificate course is not available for the skill development of the
candidates in Animation Sector under the Electronics Sector Skill Council of India.
What arrangements are in place to monitor and review the qualification(s)? What data will be
used and at what point will the qualification(s) be revised or updated?
The Board of Studies (BOS) committee will meet for review of the syllabus in the month of Jan 2018
which consists of University Professors and industrial experts with subject specialization.
The data used for revision or update will be impact analysis (student and industries) and new subject
area opportunities, multiple entry and exits incorporated or RPL strategy implementations.
The curriculum review and updates, in consultation with industries and expert of respective domain,
NOS approved by NSDA will also be referred to from time to time.
SECTION 4
EVIDENCE OF RECOGNITION AND PROGRESSION
What steps have been taken in the design of this or other qualifications to ensure that
there is a clear path to other qualifications in this sector?
Qualifying trainee will obtain a CITD Certificate in ‘Post Graduate Diploma in VLSI &
Embedded Systems’. After 1 yr of training and 6 months of internship experience give the
opportunities to the trainees to work as Design Engineer/ Embedded Engineer/ Physical Design
Engineer/ Synthesis Engineer/ Program Engineer/Verification Engineer/ Layout Engineer as a
career progression with this position and experience of 3 years gives career scope of Senior
Design Engineer/Senior Embedded Engineer/ Senior Physical Design Engineer/ Senior
Synthesis Engineer/ Senior Program Engineer/ Senior Verification Engineer/ Senior Layout
Engineer. Also he/she can become an entrepreneur in this sector after getting 3 year of
experience. The below mention diagrams represent the vertical mobility for the job holder as a
job progression in Animation Sector.
As a educational progression the trainee will be able to apply for (as per university entry
scheme) M.Tech (VLSI System Design) at any corresponding University.
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Design Engineer in
Digital Domain
Sr. Design Engineer in
Digital Domain
Team Leader in Digital Domain
Project Manager
Delivery Manager
Career progression, trainee appoint as a Digital Design Engineer
Verification Engineer
Sr. Verification
Engineer
Team Leader in
Verification Domain
Project
Manager
Delivery
ManagerCareer progression, trainee appoint as a Verification Design Engineer
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Physical Design
Engineer
Sr. Physical
Design Engineer
Team Leader in Physical
Design.
Project
Manager
Delivery
ManagerCareer progression, trainee appoint as a Physical Design (PD) Engineer
Synthesis
Design Engineer
Sr. Synthesis
Design Engineer
Team Leader in Synthesis
Design.
Project
Manager
Delivery
ManagerCareer progression, trainee appoint as a Synthesis Design Engineer
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Embedded
Engineer
Sr. Embedded
Engineer
Team Leader at Board
Level
Project
Manager
Delivery
ManagerCareer progression, trainee appoint as a Embedded Engineer
Programming
Engineer
Sr.
Programming Engineer
Team Leader in Embedded
Domain
Project
Manager
Delivery
ManagerCareer progression, trainee appoint as a Programming Engineer
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