Muon Tracking FEE
R.E. Mischke
Los Alamos
10 September, 1999
presentation to the
PHENIX Muon Arm
Technical Advisory Committee
Outline
• Scope of Project
• Status
• Results from CROC prototype
• Schedule
• Production cost
• Summary
Scope of Project• Electronics
tracking chambers to Phenix interface
• Associated Mechanical Structures
• Power and Grounding
• Ancillary Systems
• Installation
• Calibration
CROC
CROC
CROC
CROC
CONTROLLER
CONTROLLER
Glink2Clink Fanout(5 channels)
ARCNet from ARCNet Hub, ordaisy-chain from previouscontroller
LVDC distribution cards onPlatform (10 channels ea)
Clink2Glink card (5 pairs ofrec., trans)
GTM fanout (platform)LVDC Power Supplies(platform)
DCM (countinghouse)
CRA manifold
CRA manifold
Nitrogen manifold(Under Platform)
H2O manifold(UnderPlatform)
Cathode Plane
CountingHouse
Patch Panel(platform)
Slow ControlsMonitors
VME Crate(platform)
HV Plane Pulser(platform)
Signal fromCounting House
Chambers Gas systeminterface (platform)
Chamber cathodes
8 CPA
2 AMUADC
CROC
FPGA
ARCnet
24” cable
CNTL
Clink
Glink
DCM
T&FC
System components
Mechanics Status and Schedule
• In-magnet mechanics• design and review complete
• fabrication in process (AMC at NMSU)
• deliveries on 1 Jan and 1 May, 2000
• Platform• design underway (B. Archuleta, J. Archuleta)
• installation in Feb, 2000
• Cable routing• preliminary design complete
FEE Design Spec•Want 100 micron position resolution from 0.5 cm cathode strips read out at 1 cm
•input cap 0 - 150 pF; typical charge 80 fC
•noise requirement of 0.7% or 0.5fC (3125 e)
•dynamic range 11 bits (0.8fC to 800fC)
•gain: 3.5 mV/fC
•typical spacing of pulses is 100 ms
•pulse rise time 500 ns
•decay time less than 12 ms
•four samples per pulse
•reasonable power-up defaults; calibration control
CPA StatusReviewed in Dec 98 - Several Issues
Additional measurements in Jan 99
power supply sensitivity, linearity, channel to channel gain variations, recovery from overload, cross talk, dynamic range
Modifications
fix serial out, change default offset DAC
Final review Apr 99
Production order Jul 99
Delivery Oct 99
CROC StatusPrototype board is being extensively tested
repaired prototype CPA chips are used
power-up defaults are unsatisfactory
load serial strings via CPA test stand
analog sections can be studied without CNTL board
mounted in chassis with backplane
test chamber and 24” cable
used as a load and to inject signals
MUON1_ROT.JPG
ResultsGain: 2.5V/764mV/1pF = 3.3 mV/fC
typical noise values for 64 CPA channels0.6mV RMS (no load)
2 mV RMS (with test chamber)
setup not optimal - additional testing plannedno HV, jumper wires, temporary grounds, incomplete
shielding, small scale, no digital
Anode pulse - 1.3 V out/ 7.3 V in
BLR (base line restore) concerns
CNTL and Glink Status
•CNTL board
•prototype almost assembled
•initial FPGA code written
•Glink/Clink
•design in layout
•cable tests underway soon
Status of Other Items
Everything Else (non-critical items postponed for now)
•LV power
•Arcnet
•T&FC and DCM connections
•Ancillary systems
Calibration
•pulsing of anodes has been shown to work
•system design just beginning
MilestonesMuTr FEE Milestones as of: 1/20/99 8/18/99
1 CPA production 3/1/99 7/23/992 Prototype-1 schematics finished 3/8/99 3/25/993 LVDC power review complete 3/17/99 11/1/994 Prototype-1 layouts finished 4/6/99 7/23/995 In-magnet mechanics review complete 5/13/99 7/27/996 Prototype-1 tested 6/2/99 10/1/997 Power and grounding review complete 6/30/99 11/1/998 CPA tested 7/12/99 12/1/999 Prototype-2 tested (production CPA required) 8/4/99 10/31/9910 FEM review 9/10/99 11/1/9911 FEM boards and assembly lines available 12/14/99 3/1/0012 First CRA assembled (with tested boards) 2/3/00 3/15/0013 Start install in-magnet framework and platform 2/1/0014 In-magnet framework installed 3/2/00 3/2/0015 First CRA installed 4/14/00 4/14/0016 Last CRA assembled 4/20/00 5/21/0017 Installation complete 7/11/00 7/11/00
Agreement with NIS4•will continue with present design of electronics through prototyping
•will support mechanical design as resources permit
•will not oversee electronics production, but will be available for consultation
•expect to complete work by 31 October
Schedule ICPA chips
production chips expected
first chips will be tested in Los Alamos
remaining chips will be tested at BNL (Chi)
CPA test stands (two from ORNL)
modify for production (McGaughey)
Stand alone ARCnet
existing capability to inject serial strings (Hoover)
implement for prototypes via spare CNTL (Liu)
31 Oct
5 Nov
Jan, 00
15 Oct
1 Oct
Schedule IICROC board
complete testing of analog portion (Cafferty)
test digital part (awaits CNTL board)
order corrected prototype board
final tests with production CPA chips
CNTL board (Robinson, Thornton)
initial checkout and loopback tests
communication with AMUADC
T&FC and DCM links
15 Sep
10 Oct
1 Nov
10 Nov
15 Sep
10 Oct
20 Oct
Schedule IIIFEM review
target date is early November
chain test with production chips is prerequisite
including data with real signals from test chamber
Production of CROC and CNTL boards
early parts orders in preparation (Hart)
place most orders if funds available
allow 3 1/2 months for board production
10 Nov
15 Sep
15 Nov
Mar, 00
Schedule IVBoard test stands
Develop design (Liu)
Assemble at LANL for use with prototypes
Ready for production testing at BNL (Liu, Hoover, +)
Calibration
Begin detailed design (Leitch)
Available for system checkout
1 Oct
1 Nov
Mar, 00
1 Oct
Jun, 00
Schedule V
Glink/Clink (Echave, S. Archuleta)
complete cable tests
prototype boards
packaging and location
Power
complete specs (Hart)
Slow Controls (Hoover)
Ancillary Systems (Pate)
30 Sep31 Oct30 Nov
1 Oct
Feb, 00
Feb, 00
Schedule VI
Assembly and Installation (Sondheim)
detailed plans need to be developed
test and assembly at BNL
Milestone targets look reasonable
1 Mar boards available
14 Apr install 1st CRA
11 Jul install last CRA
1 Nov
Mar, 00
(Cross rib assembly)
Production Costs
project file current estCROC $ 90.4K 139CNTL 202.6 157backplane 38.2 40Glink/Clink 58.2 60FEM Assembly and Install 227.5 183power and grounding 100 50ancillary systems 20 20interface 46.8 47platforms 54.2 54calibration 69.1 30system engineering 50 0 contingency 177 total $957K $957K
Summary
•Performance of analog portion of prototype encouraging
•design specs have been met (with caveats)
•No show-stoppers expected with digital portions
•Most areas of project are being addressed
•Schedule is aggressive, but not unreasonable
•Production cost estimate conservative
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