Doc No. MV-S109418-00 Rev. A
April 21, 2015
Document Classification: ProprietaryMarvell. Moving Forward Faster
88SE9345 R3.3Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller
Preliminary Datasheet
88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O ControllerPreliminary Datasheet
No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the express written permission of Marvell. Marvell retains the right to make changes to this document at any time, without notice. Marvell makes no warranty of any kind, expressed or implied, with regard to any information contained in this document, including, but not limited to, the implied warranties of merchantability or fitness for any particular purpose. Further, Marvell does not warrant the accuracy or completeness of the information, text, graphics, or other items contained within this document. Marvell products are not designed for use in life-support equipment or applications that would cause a life-threatening situation if any such products failed. Do not use Marvell products in these types of equipment or applications. With respect to the products described herein, the user or recipient, in the absence of appropriate U.S. government authorization, agrees: 1) Not to re-export or release any such information consisting of technology, software or source code controlled for national security reasons by the U.S. Export Control Regulations ("EAR"), to a national of EAR Country Groups D:1 or E:2; 2) Not to export the direct product of such technology or such software, to EAR Country Groups D:1 or E:2, if such technology or software and direct products thereof are controlled for national security reasons by the EAR; and, 3) In the case of technology controlled for national security reasons under the EAR where the direct product of the technology is a complete plant or component of a plant, not to export to EAR Country Groups D:1 or E:2 the direct product of the plant or major component thereof, if such direct product is controlled for national security reasons by the EAR, or is subject to controls under the U.S. Munitions List ("USML"). At all times hereunder, the recipient of any such information agrees that they shall be deemed to have manually signed this document in connection with their receipt of any such information.
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Patent(s) Pending—Products identified in this document may be covered by one or more Marvell patents and/or patent applications.
For more information, visit our website at: www.marvell.com
ii
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
Ordering Information
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Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
ORDERING INFORMATION
Ordering Part Numbers and Package Markings
The following figure shows the ordering part numbering scheme for the 88SE9345 part. For complete ordering information, contact your Marvell FAE or sales representative.
Sample Ordering Part Number
The standard ordering part numbers for the respective solutions are indicated in the following table.
The next figure shows a typical Marvell package marking.
88SE9345 Package Marking and Pin 1 Location
Ordering Part Numbers
Part Number Description
88SE9345C3-BMJ2C000 481-Ball TFBGA 19 × 19 mm
This product does not support Marvell RAID stack.
Part Number
Product Revision
Custom Code
Custom Code(optional )
88XXXXX - XX - XXX - C000 - XXXX
Temperature CodeC = CommercialI = Industrial
Environmental Code + = RoHS 0/6–= RoHS 5/61 = RoHS 6/62 = Green)
Package Code3-character
alphabetic code such as BCC, TEH
Custom Code
Extended Part Number
YYWW xx@Country of Origin
Part number, package code, environmental code eXXXXX = Part number AAA = Package codee = Environmental code (+ = RoHS 0/6, no code = RoHS 5/6, 1 = RoHS 6/6, 2 = Green)
Country of origin(contained in the mold ID ormarked as the last line onthe package)
Pin 1 location
Marvell Logo
Lot Number88XXXXX-AAAe
Date code, custom code, assembly plant codeYYWW = Date code (YY = year, WW = Work Week)xx = Custom code or die revision@ = Assembly plant code
88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller Preliminary Datasheet
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Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
Change History
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Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
CHANGE HISTORY
The following table identifies the document change history for Rev. A.
Document Changes *
Location Type Description Date
Page 1-1 Update Updated the description for chapter 1, Overview:
from
The 88SE9345 is a four-port, 6.0 Gbps SATA controller that provides a one- or four-lane PCIe 2.0 host interface, and supports advanced RAID topologies. The 88SE9xx5 is similar to the 88SE9xx0, but does not support the Marvell RAID stack.
to
The 88SE9345 is a four-port, 6.0 Gbps SATA controller that provides a one-, two-, or four-lane PCIe 2.0 host interface, and supports advanced RAID topologies. The 88SE9xx5 is similar to the 88SE9xx0, but does not support the Marvell RAID stack.
December 8, 2014
Page 2-2 Update Updated the description for section 2.1, General. December 5, 2014
Page 3-5 Update Updated Table 3-1, Signal Type Definitions. December 8, 2014
Page 3-8 Update Updated the description for PIN_TEST[9:8] in Table 3-2, General Purpose I/O Signals:
from
PIN_TEST[9:8]–PCIe maximum lane width
0h: x81h: x12h: x43h: x8
to
PIN_TEST[9:8]–PCIe maximum lane width
0h: x8
Note: Always use 0h.
January 14, 2015
Page 4-2 Update Added notes for the following schematics in section 4.1, 88SE9345 Board Schematics:
• 88SE9345 Example Board Schematic (1 of 4)• 88SE9345 Example Board Schematic (2 of 4)• 88SE9345 Example Board Schematic (3 of 4)• 88SE9345 Example Board Schematic (4 of 4)
June 27, 2014
88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O ControllerPreliminary Datasheet
vi
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
Page 5-4 Parameter Updated Table 5-3, DC Electrical Characteristics:
• Updated Analog Power for PCIe PHY 1.8V.• Updated Analog Power for SATA PHY 2.5V, Chip PLL.• Updated Digital Core Power.• Updated Digital I/O Power.• Corrected the Maximum value of Input Low Voltage of Digital I/O from
0.8 to 0.3 × VDDOx.• Corrected the Minimum value of Input High Voltage of Digital I/O from
2.0 to 0.7 × VDDOx.• Corrected the Maximum value of Input High Voltage of Digital I/O
from 3.6 to VDDOx + 0.4.• Corrected the Typical value of Output High Voltage of Digital I/O from
VDDO1/VDDO2 to VDDOx.
December 18, 2014
Page 5-5 Update Updated the description for section 5.4, Thermal Data:
from
Table 5-5 shows the values for the package thermal parameters for the 484-pin TFBGA mounted on a 4-layer PCB.
to
Table 5-5 shows the values for the package thermal parameters for the 481-ball TFBGA mounted on a 4-layer PCB.
December 4, 2014
* The type of change is categorized as: Parameter, Revision, or Update. A Parameter change is a change to a spec value, a Revision change is one that originates from the chip Revision Notice, and an Update change includes all other document updates.
Document Changes * (continued)
Location Type Description Date
Contents
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Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
CONTENTS
1 OVERVIEW ........................................................................................................................................................ 1-1
2 FEATURES ........................................................................................................................................................ 2-1
2.1 GENERAL .................................................................................................................................................. 2-2
2.2 PCIE ......................................................................................................................................................... 2-3
2.3 SATA ...................................................................................................................................................... 2-4
2.4 XOR ENGINE ............................................................................................................................................ 2-5
2.5 PERIPHERALS ............................................................................................................................................ 2-6
3 PACKAGE ......................................................................................................................................................... 3-1
3.1 BALL DIAGRAM .......................................................................................................................................... 3-2
3.2 MECHANICAL DIMENSIONS ......................................................................................................................... 3-3
3.3 SIGNAL DESCRIPTIONS ............................................................................................................................... 3-53.3.1 Signal Definitions ...................................................................................................................... 3-53.3.2 Signal Descriptions ................................................................................................................... 3-6
4 LAYOUT GUIDELINES ...................................................................................................................................... 4-1
4.1 88SE9345 BOARD SCHEMATICS ................................................................................................................ 4-2
4.2 LAYER STACK-UP ...................................................................................................................................... 4-74.2.1 Layer 1–Topside, Parts, Low and High-Speed Signal Routes, and Power Routes ................... 4-74.2.2 Layer 2–Solid Ground Plane ..................................................................................................... 4-74.2.3 Layer 3–Power Plane and Low Speed Signals ......................................................................... 4-74.2.4 Layer 4–Power Plane ................................................................................................................ 4-74.2.5 Layer 5–Solid Ground Plane ..................................................................................................... 4-74.2.6 Layer 6–Bottom Layer, Low and High-Speed Signal Routes, and Power Routes .................... 4-8
4.3 POWER SUPPLY ........................................................................................................................................ 4-94.3.1 VDD Power (1.0V) ..................................................................................................................... 4-94.3.2 PCIe Analog Power Supply (1.8V) ............................................................................................ 4-94.3.3 SATA Analog Power Supply (2.5V) ........................................................................................... 4-94.3.4 General I/O Power (3.3V) .......................................................................................................... 4-94.3.5 Bias Current Resistor (RSET) ................................................................................................. 4-10
4.4 PCB TRACE ROUTING ............................................................................................................................. 4-11
4.5 RECOMMENDED LAYOUT .......................................................................................................................... 4-12
5 ELECTRICAL SPECIFICATIONS ...................................................................................................................... 5-1
5.1 ABSOLUTE MAXIMUM RATINGS .................................................................................................................. 5-2
5.2 RECOMMENDED OPERATING CONDITIONS ................................................................................................... 5-3
5.3 DC ELECTRICAL CHARACTERISTICS ........................................................................................................... 5-4
5.4 THERMAL DATA ......................................................................................................................................... 5-5
5.5 AC TIMING ................................................................................................................................................ 5-65.5.1 SATA ......................................................................................................................................... 5-65.5.2 PCIe .......................................................................................................................................... 5-65.5.3 Parallel Flash and NVSRAM ..................................................................................................... 5-6
88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller Preliminary Datasheet
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Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
Part 1: Chip OverviewOverview
1-1
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
1 OVERVIEW
The 88SE9345 is a four-port, 6.0 Gbps SATA controller that provides a one-, two-, or four-lane PCIe 2.0 host interface, and supports advanced RAID topologies. The 88SE9xx5 is similar to the 88SE9xx0, but does not support the Marvell RAID stack.
The 88SE9345 controller brings a high-performance, low-cost 6.0 Gbps per port SATA solution to HBA, workstation, and server designs utilizing a one- or four-lane PCIe 2.0 interface. The 88SE9345 integrates four high-performance SATA PHYs and a self-configuring four-lane PCIe core. Each of the four PHYs is capable of 1.5 Gbps, 3.0 Gbps, and 6.0 Gbps SATA link rates. The controller supports the SATA protocol defined in the Serial ATA, Revision 3.0 Specification.
Figure 1-1 shows the system block diagram.
Figure 1-1 88SE9345 (4-Port SATA) Block
AH
B B
us
MXI Bus
XOR x2
PCI-Express
x4
FLASHNVSRAM
PBSRAM
SATAx4
Config, Interrupts , and Timers
GPPs, UART, andTWSI
Comm
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88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller Preliminary Datasheet
1-2
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
Part 1: Chip OverviewFeatures
2-1
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
2 FEATURES
The chapter contains the following sections:
General
PCIe
SATA
XOR Engine
Peripherals
88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller Preliminary Datasheet
2-2 General
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
2.1 General
Four SATA ports.
Choice of x1, x2, or x4 lane PCIe 2.0 host interface.
Supports three Serial Device Bus (I2C) controllers for communicating with hardware monitoring ICs.
Supports two industry standard 57600 UARTs.
Supports two SFF-8485 compliant SGPIO ports.
Up to 2048 concurrent I/O operations.
Up to 64 concurrent SATA Devices.
No hardware limit on the number of SAS devices supported.
55 nm CMOS process, 1.0V digital core, 2.5V analog power supply, and 3.3V I/O supply.
Estimated power (4-port):
Minimum = 3.0W
Typical = 3.93W
Maximum = 5.7W
Up to 34 LED/GPIO ports.
Supports hardware RAID 5 and RAID 6 acceleration.
Supports Data Path Parity Protection (DPP).
Part 1: Chip OverviewFeatures
PCIe 2-3
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
2.2 PCIe
Supports x1, x2, or x4 lane PCIe 2.0 Interface (5.0 Gbps).
Supports four fully independent PCIe functions.
Supports independent interrupt mechanisms for each PCIe function.
Supports Message Signal Interrupts (MSI).
All registers memory mapped.
Supports PCIe Power Management: D0, D1, D3COLD, D3HOT.
88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller Preliminary Datasheet
2-4 SATA
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
2.3 SATA
Serial ATA Revision 3.0 (6 Gbps) compliant, with speed negotiation to 3.0 Gbps and 1.5 Gbps.
Supports programmable SATA signaling levels, including Gen1x, Gen2i, and Gen2x.
Supports ATA and ATAPI commands.
Supports Native Command Queuing (NCQ).
Non-zero offset and non-sequential data delivery.
32 outstanding commands per device.
Supports Port Multiplier.
FIS based Switching on NCQ and legacy commands.
Supports Host mode and Device mode of operation.
Supports hardware assisted Scatter-Gather.
Part 1: Chip OverviewFeatures
XOR Engine 2-5
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
2.4 XOR Engine
Supports Advanced RAID features including:
Dual XOR RAID 6.
P + Q + Copy, or Q + Q + Q RAID 6.
Memory Block Fill.
Zero Result Check.
Generates up to 3 checksums concurrently, including any combination of P and Q.
Independent GF Multiply coefficient for each of 3 concurrent Q checksum calculations.
Supports rebuilding three failed drives simultaneously with a single read of remaining good drives.
Supports chained XOR Descriptor Tables, with up to 32 operations in each table.
Supports Scatter-Gather transfers using a common PRD format.
Supports CRC32 checksum generation and checking.
88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller Preliminary Datasheet
2-6 Peripherals
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
2.5 Peripherals
Supports up to 4 MB of external NVSRAM memory (x8/x16).
Supports up to 4 MB of external PBSRAM memory (x32).
Supports up to 8 MB of external Parallel Flash memory (x8/x16).
Supports up to 16 MB of external SPI Flash memory.
Part 1: Chip OverviewPackage
3-1
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
3 PACKAGE
This chapter contains the following sections:
Ball Diagram
Mechanical Dimensions
Signal Descriptions
88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller Preliminary Datasheet
3-2 Ball Diagram
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
3.1 Ball Diagram
The 481-pin TFBGA ball diagram is illustrated in Figure 3-1.
Figure 3-1 Ball Diagram
VSS
VSS
PRXP
[0]
VSS
PRXP[1
]
VSS
PRXP
[2]
VSS
PRXP
[3]
VSS
REFC
LKP
VSS
NC
VSS
NC
VSS
NC
VSS
NC
VSS
PIN
_F_
WE_NP
IN_P
_
DATA
[20]V
SS
PIN
_TEST
[13]V
SS
PRXN[0
]
VSS
PRXN[1
]
VSS
PRXN[2
]
VSS
PRXN[3
]
VSS
REFC
LKN
VSSN
CVSS
NC
VSS
NC
VSS
NC
VSS
PIN
_F_
BYTE
_NPIN
_P_
DATA
[19]
PIN
_P_
DATA
[26]
PIN
_TEST
[10]
PIN
_TEST
[15]V
SS
PTX
P[0
]
VSS
PTX
P[1
]
VSS
PTX
P[2
]
VSS
PTX
P[3
]
VSS
NC
VSS
NC
VSS
NC
VSS
NC
VSS
PIN
_N_
CE_NP
IN_F
_
RESET
_NPIN
_P_
DATA
[25]
PIN
_P_
DATA
[29]
PIN
_TEST
[8]
PIN
_TEST
[14]V
SS
PTX
N[0
]
VSS
PTX
N[1
]
VSS
PTX
N[2
]
VSS
PTX
N[3
]
VSS
NC
VSS
NC
VSS
NC
VSS
NC
VSS
PIN
_N_
WE_NP
IN_F
_
READY
PIN
_P_
DATA
[24]P
IN_P
_
DATA
[30]
PIN
_TEST
[9]
PIN_T
EST
[11]
PIN
_TEST
[12]VS
SVSS
VSS
VSS
VSS
PTP
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
PIN
_F_C
E
_NPIN
_P
_DATA
[18]P
IN_P
_
DATA
[27]P
IN_P
_
DATA
[31]
PIN
_TEST
[4]
PIN
_TEST
[7]
PIN
_TEST
[6]V
SS
VSS
AVDD25
_
1VSS
AVDD[8
]-1
AVDD[8
]-1
AVDD[8
]-1
VSS
PIN
_ISET
AVDD[8
]-2
AVDD[8
]-2
AVD
D[8
]-2
VSS
AVDD25
_0
VSS
VDD
O2
PIN
_F_O
E_
NPIN
_P_
DATA
[34]P
IN_P
_
DATA
[17]
PIN
_P_
ADDR
[3]
PIN
_TEST
[1]
PIN
_TEST
[3]
PIN
_TEST
[5]
VSS
PIN
_N_O
E_
NPIN
_P_
DATA
[16]P
IN_P
_
DATA
[21]
PIN
_P_
ADDR
[2]
PIN
_FLT
[8]
PIN_T
EST
[0]
PIN
_TEST
[2]
VDDO1
VDD
VDD
AVDD[8
]-1
AVD
D[8
]-1
AVD
D[8
]-1
AVDD[8
]-1
AVD
D[8
]-2
AVD
D[8
]-2
AVD
D[8
]-2
AVDD[8
]-2
VDD
VDD
VDD
VDDO2
PIN
_P_
DATA
[22]P
IN_P
_
DATA
[23]
PIN
_P_
ADDR
[1]
PIN
_FLT
[5]
PIN
_FLT
[6]
PIN
_FLT
[7]
VDDO1
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDO2
PIN
_P_
DATA
[28]P
IN_P
_
DATA
[35]
PIN
_P_
ADDR
[19]
PIN
_FLT
[2]
PIN
_FLT
[3]
PIN
_FLT
[4]
VDDO1
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDO2
PIN
_P_
ADDR
[5]P
IN_P
_
ADDR
[0]
PIN
_P_
ADDR
[18]
PIN
_FLT
[0]
PIN
_FLT
[1]
PIN
_ACT
[8]
VDDO1
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDO2
PIN
_P_
ADDR
[4]
PIN
_P_
ADDR
[11]P
IN_P
_
ADDR
[10]
PIN
_ACT
[6]
PIN
_ACT
[7]
PIN
_ACT
[3]V
DDO1
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDO2
PIN
_P_
ADDR
[17]
PIN
_P_
ADDR
[13]P
IN_P
_
ADDR
[12]
PIN
_ACT
[5]
PIN
_ACT
[4]
PIN
_ACT
[0]
VDDO1
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDO2
PIN
_P_
ADDR
[14]P
IN_P
_
ADDR
[16]
PIN
_P_
ADDR
[15]
PIN
_ACT
[2]
PIN_A
CT
[1]
PIN
_SCL
[0]
VDDO1
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDO2
PIN
_P_
DATA
[1]P
IN_P
_
DATA
[0]
PIN
_P_
DATA
[32]
PIN
_SCL
[2]
PIN
_SCL
[1]
PIN
_SDA
[0]
VDDO1
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDO2
PIN
_P_
DATA
[5]
PIN
_P_
DATA
[6]P
IN_P
_
DATA
[2]
PIN
_SDA
[2]
PIN
_SDA
[1]
PIN
_UAO
[0]
VDDO1
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDO2
PIN
_P_
DATA
[10]PIN
_P_
DATA
[12]
PIN
_P_
DATA
[3]
PIN
_UAI
[1]
PIN_U
AI
[0]
PIN
_SPI_
DOV
AA_
ANA
VDDO2
PIN
_P_
DATA
[14]
PIN
_P_
DATA
[11]P
IN_P
_
DATA
[4]
PIN
_UAO[1
]
PIN
_SPI_
DI
PIN
_RESET
_NVSS
VSS
VSS
VSS
VAA[4
-7]
VAA[4
-7]
VAA[4
-7]
VAA[4
-7]
VAA[4
-7]
VAA[0
-3]
VAA[0
-3]
VAA[0
-3]
VAA[0
-3]
VAA[0
-3]
VSS
VSS
VSS
PIN
_P_
GW
_NPIN
_P_
DATA
[13]P
IN_P
_
DATA
[7]
PIN
_SPI_
CS_N
PIN
_CNFG
[1]
ISET
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
PIN
_P_W
E
_N[1
]PIN
_P_
DATA
[15]P
IN_P
_
DATA
[8]
PIN
_SPI_
CLK
PIN
_CNFG
[0]V
SS
NC
VSS
NC
VSS
NCV
SS
NC
VSS
PIN
_RXN
[3]V
SS
PIN
_RXN
[2]V
SS
PIN
_RXN
[1]V
SS
PIN
_RXN[0
]
VSS
PIN
_P_W
E_N
[2]
PIN
_P_
WE_N
[0]
PIN
_P_
DATA
[33]P
IN_P
_
DATA
[9]
PIN
_M_
DATA
PIN
_PRE
SET_N
VSS
NCV
SS
NC
VSS
NC
VSS
NCV
SS
PIN
_RXP
[3]
VSS
PIN_R
XP
[2]V
SS
PIN
_RXP
[1]V
SS
PIN
_RXP
[0]V
SS
PIN
_P_
CS1_
NPIN
_P_
WE_N
[3]
PIN
_P_
ADV_NP
IN_P
_
ADDR
[9]
PIN
_M_
CLK
PIN
_REF
CLKN
CVSS
NC
VSS
NCV
SS
NC
VSS
PIN
_TXN
[3]
VSS
PIN
_TXN
[2]V
SS
PIN
_TXN
[1]
VSS
PIN
_TXN
[0]
VSSP
IN_P
_
ADDR
[20]P
IN_P
_
ADDR
[6]
PIN
_P
_OUT_
CLKP
IN_P
_
ADSC_
NPIN
_P_
ADDR
[8]
VSS
PIN
_
TPNC
VSS
NC
VSS
NCV
SS
NC
VSS
PIN
_TXP
[3]V
SS
PIN
_TXP
[2]V
SS
PIN
_TXP
[1]V
SS
PIN
_TXP
[0]V
SS
PIN
_P_
ADDR
[21]
PIN
_P_
ADDR
[7]P
IN_P
_
OE_NP
IN_P
_
BW
_NVSS
Part 1: Chip OverviewPackage
Mechanical Dimensions 3-3
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
3.2 Mechanical Dimensions
The package mechanical drawing is shown in Figure 3-2 and the mechanical dimensions are shown in Figure 3-2.
Figure 3-2 Package Mechanical Drawing (BMJ)
88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller Preliminary Datasheet
3-4 Mechanical Dimensions
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
Figure 3-3 Package Mechanical Dimensions (BMJ)
Part 1: Chip OverviewPackage
Signal Descriptions 3-5
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
3.3 Signal Descriptions
This section includes information on signal definitions and descriptions:
Signal Definitions
Signal Descriptions
3.3.1 Signal Definitions
Signal type definitions are shown in Table 3-1.
Table 3-1 Signal Type Definitions
Signal Type Definition
I/O Input and output
I Input only
O Output only
OC Open Collector
OD Open-Drain pad
Ground Ground
Power Power
NC No Connect*
* Pin is floating and is not connected internally to any active circuitry nor has any electrical continuity to any other pin
DNC Do Not Connect†
† Device pin to which there may or may not be an internal connection, but to which no external connections are allowed.
N/A Not Applicable
88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller Preliminary Datasheet
3-6 Signal Descriptions
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
3.3.2 Signal Descriptions
This section outlines the 88SE9345 signal descriptions. Signals ending with the letter “N” are active-low signals.
Table 3-2 General Purpose I/O Signals
Signal NameSignal Number
Type Description
PIN_ACT[8]
PIN_ACT[7]
PIN_ACT[6]
PIN_ACT[5]
PIN_ACT[4]
PIN_ACT[3]
PIN_ACT[2]
PIN_ACT[1]
PIN_ACT[0]
L21
M22
M23
N23
N22
M21
P23
P22
N21
I/O, OC Activity LED.
Active low.
PIN_ACT is active when SATA PHY is transmitting or receiving.
These pins can be used as GPIO.
PIN_ACT[3:0]–SATA PHY[3:0] activity.
PIN_ACT[7:4]—Not used.
PIN_ACT[8]–Global Activity. Enabled when any SATA PHY is active.
Part 1: Chip OverviewPackage
Signal Descriptions 3-7
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
PIN_FLT[8]
PIN_FLT[7]
PIN_FLT[6]
PIN_FLT[5]
PIN_FLT[4]
PIN_FLT[3]
PIN_FLT[2]
PIN_FLT[1]
PIN_FLT[0]
H23
J21
J22
J23
K21
K22
K23
L22
L23
I/O, OC Fault LED.
Active low signals.
PIN_FLT is active when PHY is not ready or when PHY is ready and there is any PHY related error or connection error.
These pins can be used as GPIO, SGPIO, I2C, or FLT_LED. See GPIO_FLT_CFG (R10080h [7:0]) and I2C_SGPIO_FLT_PAD_SEL (R10104h [9:8]).
Pins used as Fault LED:
• PIN_FLT[8]: Global Fault indication. The indicator is on when any SATA_PHY has a fault.
• PIN_FLT[3:0] corresponds to SATA_PHY3 through PHY0.
Note: When PHY is not ready, PIN_FLT[7:0] is always on. After the PHY is ready, a fault occurs.
Pins used as SGPIO:
• PIN_FLT[8]: Same as FLT mode.• PIN_FLT[7:4]: SGPIO1 SCLK, SLOAD, SDOUT,
SDIN• PIN_FLT[3:0]: SGPIO0
SCLK,SLOAD,SDOUT,SDIN
Used as I2C:
• PIN_FLT[8]: Same as FLT Mode• PIN_FLT[7:6]: I2C2 CLK, DATA• PIN_FLT[5:4]: Not used• PIN_FLT[3:2]: I2C1 CLK, DATA• PIN_FLT[1:0]: Not used
Table 3-2 General Purpose I/O Signals (continued)
Signal NameSignal Number
Type Description
88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller Preliminary Datasheet
3-8 Signal Descriptions
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
PIN_TEST[15]
PIN_TEST[14]
PIN_TEST[13]
PIN_TEST[12]
PIN_TEST[11]
PIN_TEST[10]
PIN_TEST[9]
PIN_TEST[8]
PIN_TEST[7]
PIN_TEST[6]
PIN_TEST[5]
PIN_TEST[4]
PIN_TEST[3]
PIN_TEST[2]
PIN_TEST[1]
PIN_TEST[0]
C22
D22
B23
E21
E22
C23
E23
D23
F22
F21
G21
F23
G22
H21
G23
H22
I/O Configuration and test pins.
These pins can be used as GPIO.
PIN_TEST[15]-PCIe power-up disable
0h: Enable PCIe after power-up1h: Disable PCIe after power-up
Not applicable to this chip. This signal needs pull-down.
PIN_TEST[14:13]–Chip reference clock selection
0h: 20 MHz1h: 50 MHz2h: 100 MHz3h: 75 MHz
PIN_TEST[12:11]–Reserved
PIN_TEST[10]–PCIe ROM location
0h: Parallel Flash1h: Serial Flash
PIN_TEST[9:8]–PCIe maximum lane width
0h: x8
Always use 0h.PIN_TEST[7:6]–Reserved
PIN_TEST[5]—PCIe configuration access enable.
0h: PCIe responds to configuration access.
1h: PCIe returns a retry configuration access.
Not applicable to this chip. This signal needs pull-down.
PIN_TEST[4]–Parallel Flash x8/x16
0h: Byte mode1h: Word mode
PIN_TEST[3:2]–Reserved
PIN_TEST[1]–UART baudrate
0h: 576001h: Reserved
PIN_TEST[0]–UART mode
0h: Reserved1h: Terminal mode
Table 3-3 Clock and Reset Signals
Signal NameSignal Number
Type Description
PIN_REFCLK AB22 I Reference clock input.
2.5V, ± 350 ppm.
PIN_RESET_N V21 I Power-on reset.
Table 3-2 General Purpose I/O Signals (continued)
Signal NameSignal Number
Type Description
Part 1: Chip OverviewPackage
Signal Descriptions 3-9
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
.
PIN_PRESET_N AA22 I PCIe Reset
PIN_TP AC22 O SATA analog test port.
Table 3-4 I2C Signals
Signal NameSignal Number
Type Description
PIN_SCL[2]
PIN_SCL[1]
PIN_SCL[0]
R23
R22
P21
I/O, OC I2C clock.
PIN_SDA[2]
PIN_SDA[1]
PIN_SDA[0]
T23
T22
R21
I/O, OC I2C data.
Table 3-5 UART Signals
Signal NameSignal Number
Type Description
PIN_UAI[1]
PIN_UAI[0]
U23
U22
I UART input.
PIN_UAO[1]
PIN_UAO[0]
V23
T21
O UART output.
Table 3-6 Parallel Flash Signals
Signal NameSignal Number
Type Description
PIN_F_BYTE_N B3 O Parallel flash Byte mode.
PIN_F_CE_N E4 O Parallel flash chip select.
PIN_F_OE_N F4 O Parallel flash output enable.
PIN_F_READY D3 I Parallel flash ready signal.
Requires external pull-up resistor.
PIN_F_RESET_N C3 O Parallel flash reset.
PIN_F_WE_N A3 O Parallel flash write enable.
Table 3-3 Clock and Reset Signals (continued)
Signal NameSignal Number
Type Description
88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller Preliminary Datasheet
3-10 Signal Descriptions
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
PIN_P_ADDR[21]
PIN_P_ADDR[20]
PIN_P_ADDR[19]
PIN_P_ADDR[18]
PIN_P_ADDR[17]
PIN_P_ADDR[16]
PIN_P_ADDR[15]
PIN_P_ADDR[14]
PIN_P_ADDR[13]
PIN_P_ADDR[12]
PIN_P_ADDR[11]
PIN_P_ADDR[10]
PIN_P_ADDR[9]
PIN_P_ADDR[8]
PIN_P_ADDR[7]
PIN_P_ADDR[6]
PIN_P_ADDR[5]
PIN_P_ADDR[4]
PIN_P_ADDR[3]
PIN_P_ADDR[2]
PIN_P_ADDR[1]]
PIN_P_ADDR[0]
AC5
AB5
J1
K1
M3
N2
N1
N3
M2
M1
L2
L1
AA1
AB1
AC4
AB4
K3
L3
F1
G1
H1
K2
O Shared address bus for parallel flash, NVSRAM and PBSRAM.
For Parallel Flash, signals are word addresses.
For NVSRAM, signals are WORD addresses.
For PBSRAM, signals are Dword addresses.
Table 3-6 Parallel Flash Signals (continued)
Signal NameSignal Number
Type Description
Part 1: Chip OverviewPackage
Signal Descriptions 3-11
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
PIN_P_DATA[35]
PIN_P_DATA[34]
PIN_P_DATA[33]
PIN_P_DATA[32]
PIN_P_DATA[31]
PIN_P_DATA[30]
PIN_P_DATA[29]
PIN_P_DATA[28]
PIN_P_DATA[27]
PIN_P_DATA[26]
PIN_P_DATA[25]
PIN_P_DATA[24]
PIN_P_DATA[23]
PIN_P_DATA[22]
PIN_P_DATA[21]
PIN_P_DATA[20]
PIN_P_DATA[19]
PIN_P_DATA[18]
PIN_P_DATA[17]
PIN_P_DATA[16]
PIN_P_DATA[15]
PIN_P_DATA[14]
PIN_P_DATA[13]
PIN_P_DATA[12]
PIN_P_DATA[11]
PIN_P_DATA[10]
PIN_P_DATA[9]
PIN_P_DATA[8]
PIN_P_DATA[7]
PIN_P_DATA[6]
PIN_P_DATA[5]
PIN_P_DATA[4]
PIN_P_DATA[3]
PIN_P_DATA[2]
PIN_P_DATA[1]]
PIN_P_DATA[0]
J2
F3
Y2
P1
E1
D1
C1
J3
E2
B1
C2
D2
H2
H3
G2
A2
B2
E3
F2
G3
W2
U3
V2
T2
U2
T3
Y1
W1
V1
R2
R3
U1
T1
R1
P3
P2
I/O Shared Data Bus for Parallel Flash/NVSRAM/PBSRAM.
For Parallel Flash, DATA[15:0] are used.
In Byte mode, DATA[15] is address bit 0. DATA[7:0] are data.
In Word mode, DATA[15:0] are data.
For NVSRAM, DATA[15:0] are used.
For PBSRAM, DATA[35:0] are used.
DATA[35] is parity for Byte 3.
DATA[34] is parity for Byte 2.
DATA[33] is parity for Byte 1.
DATA[32] is parity for Byte 0.
Table 3-6 Parallel Flash Signals (continued)
Signal NameSignal Number
Type Description
88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller Preliminary Datasheet
3-12 Signal Descriptions
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
Table 3-7 NVSRAM Signals
Signal NameSignal Number
Type Description
PIN_N_CE_N C4 O nvSRAM chip select.
PIN_N_OE_N G4 O nvSRAM output enable.
PIN_N_WE_N D4 O nvSRAM write enable.
Table 3-8 PBSRAM Signals
Signal NameSignal Number
Type Description
PIN_P_ADSC_N AB2 O PBSRAM ASDC mode.
PIN_P_ADV_N AA2 O PBSRAM address advance.
PIN_P_BW_N AC2 O PBSRAM BW.
PIN_P_CS1_N AA4 O PBSRAM chip select.
PIN_P_GW_N V3 O PBSRAM global write enable.
PIN_P_OE_N AC3 O PBSRAM output enable.
PIN_P_OUT_CLK AB3 O PBSRAM clock.
PIN_P_WE_N[3]
PIN_P_WE_N[2]
PIN_P_WE_N[1]
PIN_P_WE_N[0]
AA3
Y4
W3
Y3
O PBSRAM write enable.
Table 3-9 System Interface Signals
Signal NameSignal Number
Type Description
PIN_CNFG[1]
PIN_CNFG[0]
W22
Y22
I Configuration.
00: Normal Functional mode.Others:Test Mode.
REFCLKP A13 I PCIe reference clock input.
100MHz ± 300ppm.No internal clock termination.
REFCLKN B13 I PCIe reference clock input.
100MHz ± 300ppm.No internal clock termination.
Part 1: Chip OverviewPackage
Signal Descriptions 3-13
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
Table 3-10 SPI Interface Signals
Signal NameSignal Number
Type Description
PIN_SPI_DI V22 I SPI data input.
PIN_SPI_CLK Y23 O SPI clock.
PIN_SPI_CS_N W23 O SPI chip select.
PIN_SPI_DO U21 O SPI data output.
Table 3-11 PCIe Interface Signals
Signal NameSignal Number
Type Description
ISET W21 I/O Reference Current for PCI-Express PHY.
This pin must be connected to an external 6.04 kΩ, 1% resistor to ground.
PIN_ISET F12 I Chip reference resistor 5 kΩ.
PTP E15 O Analog test port for PCIe.
PIN_M_CLK AB23 I PCIe debugging MDIO interface, clock.
PIN_M_DATA AA23 I/O PCIe debugging MDIO interface, data.
Table 3-12 SATA Transmitter and Receiver Interface Signals
Signal NameSignal Number
Type Description
PIN_RXP[3]
PIN_RXP[2]
PIN_RXP[1]
PIN_RXP[0]
AA12
AA10
AA8
AA6
I PIN_RXP[3:0]–SATA PHY 3–0 Receiver Differential Signal.
PIN_RXN[3]
PIN_RXN[2]
PIN_RXN[1]
PIN_RXN[0]
Y12
Y10
Y8
Y6
I PIN_RXN[3:0]–SATA PHY 3–0 Receiver Differential Signals.
88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller Preliminary Datasheet
3-14 Signal Descriptions
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
PIN_TXP[3]
PIN_TXP[2]
PIN_TXP[1]
PIN_TXP[0]
AC13
AC11
AC9
AC7
O PIN_TXP[3:0]–SATA PHY 3–0 Transmitter Differential Signals.
PIN_TXN[7]
PIN_TXN[6]
PIN_TXN[5]
PIN_TXN[4]
PIN_TXN[3]
PIN_TXN[2]
PIN_TXN[1]
PIN_TXN[0]
–
–
–
–
AB13
AB11
AB9
AB7
O PIN_TXN[3:0]–SATA PHY 3–0 Transmitter Differential Signals.
Table 3-13 PCIe Transmitter and Receiver Interface Signals
Signal NameSignal Number
Type Description
PRXP[3]
PRXP[2]
PRXP[1]
PRXP[0]
A15
A17
A19
A21
I PRXP[3:0]–PCI-Express Lane 3–0 Receiver Differential Signal (PCI-Express RX +/-).
PRXN[3]
PRXN[2]
PRXN[1]
PRXN[0]
B15
B17
B19
B21
I PRXN[3:0]–PCI-Express Lane 3–0 Receiver Differential Signals (PCI-Express RX +/-).
PTXP[3]
PTXP[2]
PTXP[1]
PTXP[0]
C14
C16
C18
C20
O PTXP[3:0]–PCI-Express Lane 3–0 Transmitter Differential Signals (PCI-Express TX -/+).
PTXN[3]
PTXN[2]
PTXN[1]
PTXN[0]
D14
D16
D18
D20
O PTXN[3:0]–PCI-Express Lane 3–0 Transmitter Differential Signals (PCI-Express TX -/+).
Table 3-12 SATA Transmitter and Receiver Interface Signals (continued)
Signal NameSignal Number
Type Description
Part 1: Chip OverviewPackage
Signal Descriptions 3-15
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
Table 3-14 Power Interface Signals
Signal NameSignal Number
Type Description
AVDD25_0 F7 Power, I I/O Pad Power 2.5V.
AVDD25_1 F18 Power, I I/O Pad Power 2.5V.
AVDD[8]-1 F14, F15, F16. H13, H14, H15, H16
Power, I 1.8V analog power for PCI-Express PHY.
AVDD[8] is for PLL and the current source.
AVDD[8]-2 F9, F10, F11, H9, H10, H11, H12
Power, I 1.8V analog power for PCI-Express PHY.
AVDD[8] is for PLL and the current source.
VAA[0-3] V7, V8, V9, V10, V11
Power, I 2.5V analog power for SATA PHY.
VAA[4-7] V12, V13, V14, V15, V16
Power, I 2.5V analog power for SATA PHY.
VAA_ANA U20 Power, I 2.5V analog power for PLL.
VDD H6, H7, H8, H17, H18, J6, J18, K6, K18, L6, L18, M6, M18, N6, N18, P6, P18, R6, R18, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18
Power, I 1.0V digital core power.
VDDO1 H20, J20, K20, L20, M20, N20, P20, R20, T20
Power, I Digital Power.
3.3V I/O Power to supply digital and I/Os.
VDDO2 F5, H4, J4, K4, L4, M4, N4, P4, R4, T4, U4
88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller Preliminary Datasheet
3-16 Signal Descriptions
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
VSS A1, A4, A6, A8, A10, A12, A14, A16, A18, A20, A22, A23, B4, B6, B8, B10, B12, B14, B16, B18, B20, B22, C5, C7, C9, C11, C13, C15, C17, C19, C21, D5, D7, D9, D11, D13, D15, D17, D19, D21, E5–E14, E16–E20, F6, F8, F13, F17, F19, F20, G20, J7–J17, K7–K17, L7–L17, M7– M17, N7–N17, P7–P17, R7–R17, V4–V6, V17– V20, W4–W20, Y5, Y7, Y9, Y11, Y13, Y15, Y17, Y19, Y21, AA5, AA7, AA9, AA11, AA13, AA15, AA17, AA19, AA21,
Ground Ground.
Table 3-14 Power Interface Signals (continued)
Signal NameSignal Number
Type Description
Part 1: Chip OverviewPackage
Signal Descriptions 3-17
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
VSS AB6, AB8, AB10, AB12, AB14, AB16, AB18, AB20, AC1, AC6, AC8, AC10, AC12, AC14, AC16, AC18, AC20, AC23
Ground Ground.
Table 3-15 No Connect Signals
Signal NameSignal Number
Type Description
NC – A5, A7, A9, A11, B5, B7, B9, B11, C6, C8, C10, C12, D6, D8, D10, D12, Y14, Y16, Y18, Y20, AA14, AA16, AA18, AA20, AB15, AB17, AB19, AB21, AC15, AC17, AC19, AC21
N/A No Connect
Table 3-14 Power Interface Signals (continued)
Signal NameSignal Number
Type Description
THIS PAGE LEFT INTENTIONALLY BLANK
88SE9345 R3.3Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller Preliminary Datasheet
3-18 Signal Descriptions
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
Part 1: Chip OverviewLayout Guidelines
4-1
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
4 LAYOUT GUIDELINES
This chapter describes the system recommendations from the Marvell Semiconductor design and application engineers who work with the 88SE9345. It is written for those who are designing schematics and printed circuit boards for an 88SE9345-based system. Whenever possible, the PCB designer should try to follow the suggestions provided in this chapter.
The information in this chapter is preliminary. Please consult with Marvell Semiconductor design and application engineers before starting your PCB design.
The chapter contains the following sections:
88SE9345 Board Schematics
Layer Stack-Up
Power Supply
PCB Trace Routing
Recommended Layout
Refer to Chapter 3, Package, for package information.
88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller Preliminary Datasheet
4-2 88SE9345 Board Schematics
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
4.1 88SE9345 Board Schematics
This section contains the following example board schematics:
Figure 4-1, 88SE9345 Example Board Schematic (1 of 4)
Figure 4-2, 88SE9345 Example Board Schematic (2 of 4)
Figure 4-3, 88SE9345 Example Board Schematic (3 of 4)
Figure 4-4, 88SE9345 Example Board Schematic (4 of 4)
Part 1: Chip OverviewLayout Guidelines
88SE9345 Board Schematics 4-3
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
Figure 4-4, 88SE9345 Example Board Schematic (4 of 4)
Figure 4-1 88SE9345 Example Board Schematic (1 of 4)
CNFG[1:0](INTERNAL TEST MODE SELECTION)
01:10:11:
*00: Normal
Vanir Lite: PCIE X 4 ONLY!
SRXN0
STXN1
SRXN1
SRXN2
STXN2
SRXN3
STXN3
S_RXN3
PTXN0PTXP0
PCLKN
PCLKP
CNFG0
CNFG1
STXP0
STXN0
PTXN3PTXP3
PTXN2PTXP2
PTXN1PTXP1
S_TXP0
S_TXN0
S_RXN0
S_RXP0 SRXP0
S_TXP1 STXP1
S_TXN1
S_RXN1
S_RXP1 SRXP1
S_TXP2 STXP2
S_TXN2
S_RXN2
S_RXP2 SRXP2
S_TXP3
S_TXN3
S_RXN3
S_RXP3
STXP3
SRXP3
STXN2STXP2
SRXP2SRXN2
SRXN0SRXP0
STXN3STXP3
SRXP3SRXN3
STXP0STXN0
STXN1STXP1
SRXP1SRXN1
S_RXP3
S_TXN3S_TXP3
S_RXP2S_RXN2
S_TXN2S_TXP2
S_RXP1S_RXN1
S_TXN1S_TXP1
S_RXP0S_RXN0
S_TXN0S_TXP0
JT_TCK
JT_TDI
JT_TMS
JT_TRSTn
JT_TDO
PRXP0PRXN0
PRXN1PRXP1
PRXN2PRXP2
PRXP3
PTXN1
PTXN0
PTXN2
PTXP0
PTXP2
PTXP1
PTXN3PTXP3
PRXN3 PCLKP
PCLKN
P0_PRSNTX2
PRXN3PRXP3
PRXN2PRXP2
PRXN1PRXP1
PRXN0PRXP0
PCIE_RESET_N
S_LOAD0S_CLK0
S_DIN0S_DOUT0
3V3
3V3
2V5
PCIE_12V_IN
3V3
3V3
SOC_RESET# 3
REG_PGOOD5
S_DIN03
S_LOAD03
S_DOUT03
S_CLK03
I2C_SCL3
I2C_SDA3
C110 100nF
R68 DNP_0R
C401U
R78 22R_X
C111 100nF
C3
71
00
0p
F_
X
C270.01U
PEX
CLOCK & RESET
SAS/SATA
U1A VanirLite_88SE9440
PIN_CNFG[1]W22PIN_CNFG[0]Y22
PIN_TPAC22
PIN_RXP[0]AA6
PIN_RXP[1]AA8
PIN_TXN[2]AB11
PIN_TXP[3]AC13
PIN_RXN[0]Y6
PIN_RXN[1]Y8
PIN_TXP[2]AC11
PIN_TXN[3]AB13
PIN_TXN[0]AB7
PIN_TXN[1]AB9
PIN_RXP[2]AA10
PIN_RXN[3]Y12
PIN_TXP[0]AC7
PIN_TXP[1]AC9
PIN_RXN[2]Y10
PIN_RXP[3]AA12
PRXN[7]B5
PRXN[6]B7
PRXP[7]A5
PRXP[6]A7
PRXN[5]A9
PRXN[4]D12
PRXN[3]B15
PRXP[2]A17
PRXP[1]A19
PRXP[0]A21
PRXP[5]B9
PRXP[4]C12
PRXP[3]A15
PRXN[2]B17
PRXN[1]B19
PRXN[0]B21
PIN_PRESET_NAA22
PIN_ISETF12
REFCLKPA13
REFCLKNB13
ISETW21
PTXN[7]D6
PTXP[7]C6
PTXN[6]D8
PTXP[6]C8
PTXN[5]D10
PTXP[5]C10
PTXN[4]B11
PTXP[4]A11
PTXN[3]D14
PTXP[3]C14
PTXN[2]D16
PTXP[2]C16
PTXN[1]D18
PTXP[1]C18
PTXN[0]D20
PTXP[0]C20
PIN_RESET_NV21
PIN_REFCLKAB22
PTPE15
R2100R_X
C112 100nF
R_CFG1_1 10K_X
C113 100nF
Y1
50MHZ_8W50000002
OE1
OUT3
Vcc4
GND2
PEX 4xP1
GOLD FINGER
+12VcB1
+12VdB2
RSVD5B3
SMCLKB5
SMDATB6
3V3cB8
TRSTB9
3.3VAuxB10
WAKE#B11
RSVD3B12
HSO_0+B14
HSO_0-B15
PRSNT#2aB17
HSO_1+B19
HSO_1-B20
HSO_2+B23
HSO_2-B24
HSO_3+B27
HSO_3-B28
RSVD4B30
PRSNT#2bB31
PRSNT#1A1
+12VbA2+12VaA3
GND21A4
TCKA5
TDIA6
TDOA7
TMSA8
3V3aA9
3V3bA10
RSTnA11
GND2A12
REFCLK+A13
REFCLK-A14
GND9A15GND8A18
RSVD2A19
GND7A20GND6A23GND5A24GND4A27GND3A28
RSVD1A32
HSI_0-A17
HSI_1-A22
HSI_2-A26
HSI_3-A30
HSI_0+A16
HSI_1+A21
HSI_2+A25
HSI_3+A29
GND11B29
GND12B26
GND13B25
GND14B22
GND15B21
GND16B18
GND17B16
GND18B13
GND19B7
GND20B4
GND22A31
GND10B32
C3
81
00
0p
F_
X
C160.01U
C114 100nF
C10.01U
R_CFG0_1 10K_X
C148
C0805
4.7uF10V
C290.01U
C140.01U
C116 100nF
R4 6.04K
J1
iPASS_0.8mm_36CONN-SAS-36pin-TS
RX+0A2
RX+1A5
RX+2A13
RX+3A16
RX-0A3
RX-1A6
RX-2A14
RX-3A17
TX+0B2
TX+1B5
TX+2B13
TX+3B16
TX-0B3
TX-1B6
TX-2B14
TX-3B17
GND1A1
GND2A4
GND3A7
GND4A12
GND5A15
GND6A18
GND7B1
GND8B4
GND9B7
GND10B12
PEG1P1
PEG2P2
MTH1S1
MTH2S2
MTH3S3
MTH4S4
MTH5S5
MTH6S6
SB0-SCLKB8
SB1-SLODB9
SB2-GNDB10
SB3A9
SB4_SDOA10
SB5_SDIA11
SB6B11
SB7A8
GND11B15
GND12B18
C100.01U
C30.01U
R77 22R_X
R_CFG0_2 1K-5%
U10
SN74LVC1G08AND
A1
B2
GND3
Y4
VCC5
C118 100nF
C190.01U
C110.01U
C3
51
00
0p
F_
X
C210.01U
C119 100nF
FB1
FB_1A
1 2
R73 22R
R_CFG0_310K_X
R3
4.99K
R_CFG1_2 1K-5%
C90.01U
R74 22R
TP2 1
C300.01U
TP11
C250.01U
C591U
C390.1U
C40.01U
C130.01U
R75 22R
R_CFG0_4
1K-5%_X
C20.01U
C3
61
00
0p
F_
X
+ C33
100uF/16V
R76 22R
88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller Preliminary Datasheet
4-4 88SE9345 Board Schematics
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
Note: This diagram is for reference only. Contact your Marvell field applications engineer for the latest schematics.
Figure 4-2 88SE9345 Example Board Schematic (2 of 4)
PIN_TEST[15:0]Configuration and Test pins, GPIO.PIN_TEST[15] => Must tie lowPIN_TEST[14:13] => Chip reference clock selection =>PIN_TEST[12:11] => RSVDPIN_TEST[10] => PCIE ROM Location =>PIN_TEST[9:8] => RSVDPIN_TEST[7:5] => RSVD Must tie lowPIN_TEST[4] => Parallel Flash x8/x16 =>PIN_TEST[3:2] => RSVDPIN_TEST[1] => UART Baud Rate =>PIN_TEST[0] => UART Mode =>
00: 20MHz, 01: 50MHz(default), 10: 100MHz, 11: 75MHz
0: Parallel Flash, 1: Serial Flash00 or 11
0: Byte Mode, 1: Word Mode
0: 57600, 1: RSVD0: RSVD, 1: Terminal Mode
(DRIVE FAULT LED)
SPI FLASH, 4MBit
(ACTIVITY LED)
NVRAM 32KBpin 2: NC, pin47: NC
NVRAM 128KBpin 2: A16, pin47: A15
Encryption key
Drive Fault/ Activity LED headers
Top - Activity (Green)Bottom - Fault (Yellow)
I2C connector
UART
Serial EEPROM for I2C
BUZZER
(ACTIVITY LED)
(DRIVE FAULT LED)
Install R34, 10K and R44, 1K for debug purposes (UART)
Item 25.
LED SILKSCREEN
U3,U5,U6 ARE OPTIONAL.
000
0
ACT2ACT3
ACT0ACT1
ACT4
ACT6ACT7
ACT5S_DIN1S_DOUT1S_LOAD1S_CLK1FLT8
P_ADDR0P_ADDR1P_ADDR2P_ADDR3P_ADDR4P_ADDR5P_ADDR6P_ADDR7P_ADDR8P_ADDR9P_ADDR10P_ADDR11P_ADDR12P_ADDR13P_ADDR14P_ADDR15P_ADDR16
P_DATA0P_DATA1P_DATA2P_DATA3P_DATA4P_DATA5P_DATA6P_DATA7
TEST[0]TEST[1]TEST[2]TEST[3]_FLT2TEST[4]_FLT3
TEST[5]TEST[6]_FLT4TEST[7]_FLT5TEST[8]
TEST[10]TEST[11]_FLT6TEST[12]_FLT7TEST[13]TEST[14]
UAI_0
N_WE_NN_CE_NN_OE_N
TEST[10]TEST[13]TEST[14]
M_DATA
N_WE_NP_ADDR13P_ADDR8P_ADDR9
P_ADDR15
P_ADDR11
N_CE_N
P_DATA6
P_ADDR10
P_DATA7P_DATA5P_DATA4P_DATA3
P_DATA0P_ADDR3P_ADDR2P_ADDR1P_ADDR0
P_ADDR16P_ADDR14P_ADDR12P_ADDR7P_ADDR6P_ADDR5
N_OE_N
P_ADDR4
P_DATA1P_DATA2
SOC_RESET# SMCLKSMDAT
ACT8
SMDATI2C_SDA
SMCLKI2C_SCL UAO_1
UAI_1
SPI_DISPI_DOSPI_CLKSPI_CS_N
ADM0_TX
SPI_CS_N
SPI_DO
TEST[2]
ACT2ACT3
ACT0ACT1
TEST[1]_DTEST[3]_DTEST[4]_D
TEST[0]
TEST[1]
SPI_CLK
SPI_DI
UAO_0
TEST[15]
UAI_0 ADM0_RXADM0_RX
I2C_SCL
I2C_SDA
S_DIN0S_DOUT0S_LOAD0S_CLK0
M_CLK
UAO_0
TEST[0]_DTEST[1]_D
TEST[4]_DTEST[3]_D
TEST[0]TEST[1]
TEST[4]_FLT3TEST[3]_FLT2
ACT3ACT2ACT1ACT0
ACT2_DACT3_D
ACT0_DACT1_D
TEST[0]_DTEST[1]_D
TEST[4]_DTEST[3]_D
TEST[0]_D
ACT2_DACT1_DACT0_D
ACT3_D
TEST[9]
3V3 3V3
3V3
3V3
3V33V3
3V3
3V3
3V3
3V3 3V3
3V33V3
3V3
3V3
3V3
3V3
3V3
3V3
3V33V3
3V3
3V3
3V3
SOC_RESET#2
S_DIN02
S_LOAD02S_DOUT02
S_CLK02
I2C_SCL2
I2C_SDA2
C48
0.1U
TP251
TP15 1
JP2
1 2
R46100R
R50 1K-5%
R40 10R
R36 10R
R17
10K_X
R19 10R
U2
ADM3202ARN
C1+1
V+2
C1-3
V-6
C2+4
C2-5
3.3V16
GND15
Tx1IN11
Tx2IN10
Rx1OUT12
Rx2OUT9
Tx1OUT14
Tx2OUT7
Rx1IN13
Rx2IN8
TP13 1
U12
PI74FCT241/SO
OEA1
DA02
DA14
DA26
DA38
GN
D10
VC
C20
OEB19
OA018
OA116
OA214
OA312
DB017
DB115
DB213
DB311
OB03
OB15
OB27
OB39
U4
4MbSPI FLASH - AT26F004
SOIC8-50-212
CS1
SO2
WP3
SI5
SCLK6
HOLD7
VCC8
Gnd4
TP481
R5710K
TP171
TP61 1
TP341
R8 10K
TP45 1
TP261
C49
C0402
100nF10V
J5
4 HEADER
1234
TP16 1
NVSRAM/FLASH
CONFIG/TEST/RSVD
PBSRAM
SERIAL INTERFACE
LED
U1B VanirLite_88SE9440
PIN_UAO[0]T21
PIN_UAO[1]V23
PIN_UAI[0]U22
PIN_UAI[1]U23
PIN_FLT[0]L23
PIN_FLT[1]L22
PIN_FLT[2]K23
PIN_FLT[3]K22
PIN_FLT[4]K21
PIN_FLT[5]J23
PIN_FLT[6]J22
PIN_FLT[7]J21
PIN_FLT[8]H23
PIN_SPI_DIV22
PIN_SPI_DOU21
PIN_SPI_CLKY23
PIN_SPI_CS_NW23
PIN_N_WE_ND4
PIN_N_CE_NC4
PIN_N_OE_NG4
PIN_P_ADDR[0]K2
PIN_P_ADDR[1]H1
PIN_P_ADDR[2]G1
PIN_P_ADDR[3]F1
PIN_P_ADDR[4]L3
PIN_P_ADDR[5]K3
PIN_P_ADDR[6]AB4
PIN_P_ADDR[7]AC4
PIN_P_ADDR[8]AB1
PIN_P_ADDR[9]AA1
PIN_P_ADDR[10]L1
PIN_P_ADDR[11]L2
PIN_P_ADDR[12]M1
PIN_P_ADDR[14]N3 PIN_P_ADDR[13]M2
PIN_P_ADDR[15]N1
PIN_P_ADDR[16]N2
PIN_P_ADDR[17]M3
PIN_P_ADDR[18]K1
PIN_P_ADDR[19]J1
PIN_P_ADDR[20]AB5
PIN_P_ADDR[21]AC5
PIN_P_BW_NAC2
PIN_P_OUT_CLKAB3
PIN_P_OE_NAC3
PIN_P_CS1_NAA4
PIN_P_WE_N[0]Y3
PIN_P_WE_N[1]W3
PIN_P_WE_N[2]Y4
PIN_P_WE_N[3]AA3
PIN_P_DATA[0]P2
PIN_P_DATA[1]P3
PIN_P_DATA[2]R1
PIN_P_DATA[3]T1
PIN_P_DATA[4]U1
PIN_P_DATA[5]R3
PIN_P_DATA[6]R2
PIN_P_DATA[7]V1
PIN_P_DATA[8]W1
PIN_P_DATA[9]Y1
PIN_P_DATA[10]T3
PIN_P_DATA[11]U2
PIN_P_DATA[12]T2
PIN_P_DATA[13]V2
PIN_P_DATA[14]U3
PIN_P_DATA[15]W2
PIN_P_DATA[16]G3
PIN_P_DATA[17]F2
PIN_P_DATA[18]E3
PIN_P_DATA[19]B2
PIN_P_DATA[20]A2
PIN_P_DATA[21]G2
PIN_P_DATA[22]H3
PIN_P_DATA[23]H2
PIN_P_DATA[24]D2
PIN_P_DATA[25]C2
PIN_P_DATA[26]B1
PIN_P_DATA[27]E2
PIN_P_DATA[28]J3
PIN_P_DATA[29]C1
PIN_P_DATA[30]D1
PIN_P_DATA[31]E1
PIN_P_DATA[32]P1
PIN_P_DATA[33]Y2
PIN_P_DATA[34]F3
PIN_P_DATA[35]J2
PIN_P_GW_NV3
PIN_P_ADSC_NAB2
PIN_P_ADV_NAA2
PIN_F_RESET_NC3
PIN_F_CE_NE4
PIN_F_READYD3
PIN_F_WE_NA3
PIN_F_OE_NF4
PIN_F_BYTE_NB3
PIN_SDA[0]R21
PIN_SDA[1]T22
PIN_SDA[2]T23
PIN_SCL[0]P21
PIN_SCL[1]R22
PIN_SCL[2]R23
PIN_TEST[0]H22
PIN_TEST[1]G23
PIN_TEST[2]H21
PIN_TEST[3]G22
PIN_TEST[4]F23
PIN_TEST[5]G21
PIN_TEST[6]F21
PIN_TEST[7]F22
PIN_TEST[8]D23
PIN_TEST[9]E23
PIN_TEST[10]C23
PIN_TEST[11]E22
PIN_TEST[12]E21
PIN_TEST[13]B23
PIN_TEST[14]D22
PIN_TEST[15]C22
PIN_ACT[0]N21
PIN_ACT[1]P22
PIN_ACT[2]P23
PIN_ACT[3]M21
PIN_ACT[4]N22
PIN_ACT[5]N23
PIN_ACT[6]M23
PIN_ACT[7]M22
PIN_ACT[8]L21
PIN_M_CLKAB23
PIN_M_DATAAA23
U5
DNP_AT24C02B
A01
A12
A23
GND4
SDA5 SCL6 WP7 VCC8
Q1FDC640PCT 1
2
3 4
5
6
BUZZ1
BUZZER_3VDC
12
TP491
TP60 1
R56
10K
FLT1 Amber
TP4 1
TP181
TP351
C46100nFC0402
C44
0.1U
C58
0.1U
R441K-5%
FLT4 Amber
R7 10K
TP271
R80 1K-5%
R38 10R
TP501
TP191
TP361
R72 1K-5%
TP39 1
U3
DNP_CY14B256L-SP35XCT
Vcap1
A162
A143
A124
A75
A66
A57
NC18
A49
NC210
NC311
NC412
VSS113
NC514
NC615
DQ016
A317
A218
A119
A020
DQ121
DQ222
NC723
NC824
VSS236NC1137NC1238NC1339A1140NC1441A942A843A1344
NC1035
NC934
DQ633
OE#32
A1031
CE#30
VCC248
A1547
HSB#46
WE#45
DQ729
DQ528
DQ427
DQ326
VCC125
R6
10K
TP55 1
C45
100nF
C0402
TP141
TP7 1
TP57 1
ACT2 GREEN
TP281
TP511
R5
10K
TP201
R22 10R
TP371
TP46 1
R79 1K-5%
R5410K
C50
0.1U
R5110K
+ C41
100uF/16V
R69 1K-5%
FLT2 Amber
TP11 1
TP291
C57
0.1U
TP59 1
TP521
TP211
TP381
R18 10R
TP5 1
TP81
J3
SH_2x5_2.54
11
22
33
44
55
66
77
88
99
1010
R37 10R
R70 1K-5%
R2
32
.0
K
R5510K
R48
10K
R16
10K_X
R11 56R
TP301
R9
R0603
0R
R34
10K
R71 1K-5%
TP66 1
TP221
R63
10K
TP401
R144.7K-5%R0603
J2
DNP_SJ-3523AUDIO-JACK-SJ-3523-SMT
GND1
RXO2
TXI3
J44
J55
FLT3 Amber
TP12 1
R2
72
.0
KR
28
2.0
KR
29
2.0
K
TP421
ACT4 GREEN
ACT1 GREEN
R3
02
.0
K
R2
42
.0
K
TP311
TP6 1
R2
52
.0
KR
26
2.0
K
TP231
TP43 1
R13 56R
C47
100nF
C0402
R15 56R
R12 56R
TP9 1 C42100nFC0402
TP441
C43
100nF
C0402
ACT3 GREEN
TP321
JP3
1 2
TP241
R49
10K
R5310K
TP56 1
R52
10K
TP53 1
TP58 1
TP3 1
LED1GREEN/YELLOWled_bi_smd4
C1
1A
12
C2
3A
24
U6
DNP_ARC100_16P_X
NC11
NC22
NC33
NC45
NC56
RST7
SCL8
VCC4
SDA19SDA210GND11GND_A12NC613NC714
TP471
TP41 1
TP101
I2C0
22-05-5035
11
22
33
R20 10R
TP331
R43 100R
Part 1: Chip OverviewLayout Guidelines
88SE9345 Board Schematics 4-5
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
Note: This diagram is for reference only. Contact your Marvell field applications engineer for the latest schematics.
Figure 4-3 88SE9345 Example Board Schematic (3 of 4)
VDDO1
AVDD[8]-1
AVDD[8]-1
AVDD[8]-2
AVDD_25
VDDO2
VDDO1
VAA_ANA
VAA_0_3
VAA_4_7
AVDD[8]-2
AVDD_25
1V0_core
VDDO2
1V0_core
1V0_core
VAA_ANA
VAA_0_3
VAA_4_7
2V5
3V3
1V0
2V5
2V5
2V5
1V8POWER/GND
U1C VanirLite_88SE9440
VSS0A1
VSS1AC1
VSS2A4
VSS3B4
VSS4V4
VSS5W4
VSS6C5
VSS7D5
VSS8E5
VSS9V5
VSS10W5
VSS11Y5
VSS12AA5
VSS13A6
VSS14B6
VSS15E6
VSS16F6
VSS17V6
VSS18W6
VSS19AB6
VSS20AC6
VSS21C7
VSS22D7
VSS23E7
VSS24J7
VSS25K7
VSS26L7
VSS27M7
VSS28N7
VSS29P7
VSS30R7
VSS31W7
VSS32Y7
VSS33AA7
VSS34A8
VSS35B8
VSS36E8
VSS37F8
VSS38J8
VSS39K8
VSS40L8
VSS41M8
VSS42N8
VSS43P8
VSS44R8
VSS45W8
VSS46AB8
VSS47AC8
VSS48C9
VSS49D9
VSS50E9
VSS51J9
VSS52K9
VSS53L9
VSS54M9
VSS55N9
VSS56P9
VSS57R9
VSS58W9
VSS59Y9
VSS60AA9
VSS61A10
VSS62B10
VSS63E10
VSS64J10
VSS65K10
VSS66L10
VSS67M10
VSS68N10
VSS69P10
VSS70R10
VSS71W10
VSS72AB10
VSS73AC10
VSS74C11
VSS75D11
VSS76E11
VSS77J11
VSS78K11
VSS79L11
VSS80M11
VSS81N11
VSS82P11
VSS83R11
VSS84W11
VSS85Y11
VSS86AA11
VSS87A12
VSS88B12
VSS89E12
VSS90J12
VSS91K12
VSS92L12
VSS93M12
VSS94N12
VSS95P12
VSS96R12
VSS97W12
VSS98AB12
VSS99AC12
VSS100C13
VSS101D13
VSS102E13
VSS103F13
VSS104J13
VSS105K13
VSS106L13
VSS107M13
VSS108N13
VSS109P13
VSS110R13
VSS111W13
VSS112Y13
VSS113AA13
VSS114A14
VSS115B14
VSS116E14
VSS117J14
VSS118K14
VSS119L14
VSS120M14
VSS121N14
VSS122P14
VSS123R14
VSS124W14
VSS125AB14
VSS126AC14
VSS127C15
AVDD[8]-1_0H13
AVDD[8]-1_1F14
AVDD[8]-1_2H14
AVDD[8]-1_3F15
AVDD[8]-1_4H15
AVDD[8]-1_5F16
AVDD[8]-1_6H16
AVDD[8]-2_0F9
VAA_ANAU20
VDDO1_0H20
VDDO1_1J20
VDDO1_2K20
VDDO1_3L20
VDDO1_4M20
VDDO1_5N20
VDDO1_6P20
VDDO1_7R20
VDD0H6
VDD1J6
VDD2K6
VDD3L6
VDD4M6
VDD5N6
VDD6P6
VDD7R6
VDD8T6
VDD9H7
VDD10T7
VDD11H8
VDD12T8
VDD13T9
VDD14T10
VDD15T11
VDD16T12
VDD17T13
VDD18T14
VDD19T15
VDD20T16
VDD21H17
VDD22T17
VDD23H18
VDD24J18
VDD25K18
VDD26L18
VDD27M18
VDD28N18
VDD29P18
VDD30R18
VDD31T18
VAA[0_3]_0V7
VAA[0_3]_1V8
VAA[0_3]_2V9
VAA[0_3]_3V10
VAA[4_7]_0V12
VAA[4_7]_1V13
VAA[4_7]_2V14
VAA[4_7]_3V15
VDDO2_0H4
VDDO2_1J4
VDDO2_2K4
VDDO2_3L4
VDDO2_4M4
VDDO2_5N4
VDDO2_6P4
VSS154E17
VSS155F17
VSS156J17
VSS157K17
VSS158L17
VSS159M17
VSS160N17
VSS161P17
VSS162R17
VSS163V17
VSS164W17
VSS165Y17
VSS166AA17
VSS167A18
VSS168B18
VSS169E18
VSS170V18
VSS171W18
VSS172AB18
VSS173AC18
VSS174C19
VSS175D19
VSS176E19
VSS177F19
VSS178V19
VSS179W19
VSS180Y19
VSS181AA19
VSS182A20
VSS183B20
VSS184E20
VSS185F20
VSS186G20
VSS187V20
VSS188W20
VSS189AB20
VSS190AC20
VSS191C21
VSS192D21
VSS193Y21
VSS194AA21
VSS195A22
VSS196B22
VSS197A23
VSS198AC23
VS
S1
35
R1
5
VS
S1
36
W1
5
VS
S1
37
Y1
5
VS
S1
38
AA
15
VS
S1
39
A1
6
VS
S1
40
B1
6
VSS128D15
VSS129J15
VSS130K15
VSS131L15
VSS132M15
VSS133N15
VSS134P15
VS
S1
41
E1
6
VS
S1
42
J1
6
VS
S1
43
K1
6
VS
S1
44
L1
6
VS
S1
45
M1
6
VS
S1
46
N1
6
VS
S1
47
P1
6
VS
S1
48
R1
6
VS
S1
49
W1
6
VS
S1
50
AB
16
VS
S1
51
AC
16
VS
S1
52
C1
7
VS
S1
53
D1
7
AVDD[8]-2_1H9
AVDD[8]-2_2F10
AVDD[8]-2_3H10
AVDD[8]-2_4F11
AVDD[8]-2_5H11
AVDD[8]-2_6H12
AVDD25_0F7
AVDD25_1F18
VAA[0_3]_4V11
VAA[4_7]_4V16
VDDO1_8T20
VDDO2_7R4
VDDO2_8T4
VDDO2_9U4
VDDO2_10F5
C84
0.01U
J6
Banana Plug_WHITE
C69
2.2U
C89
10U_10V
C52
0.01U
J10
Banana Plug_Blue
C98
0.01U
C67
0.01U
C68
1000P
C101
0.01U
C70
0.1U
C92
0.01U
C94
10U_10V
C105
0.1U
J7
Banana Plug_RED
FB10
FB_1A
1 2
TP64
1
C93
0.01U
FB7
FB_1A
1 2
C87
0.01U
C63
0.01U
FB8
FB_4A
1 2
C81
0.1U
C95
0.1U
C64
1000P
C104
0.1U
C99
0.01U
C85
0.01UFB9
FB_1A
1 2
C108
0.01U
C102
0.01U
C56
1000P
C72
1000P
R205 0.1-1%R0805
C88
0.01U
TP63
1
C90
0.1U
R206 0.1-1%R0805
FB4
FB_1A
1 2
R207 0.1-1%R0805
C107
0.01U
C61
2.2U
J4
Banana Plug_YELLOW
J8
GND
C109
0.01U
C82
0.1U
C54
0.1U
C106
0.1U
C62
0.1U
C96
0.1U
C91
0.1U
R210 0.1-1%R0805
C71
0.01U
C79
0.01U
R208 0.1-1%R0805
C55
0.01U
FB2
FB_1A
1 2
C65
2.2U
C53
2.2U
C97
0.1U
FB5
FB_2A
1 2
C78
0.1U
C77
10U_10V
C100
0.01U
C103
10U_10V
R209 0.1-1%R0805
C86
0.01U
C66
0.1UFB6
FB_1A
1 2
C80
10U_10V
C51
0.1U
FB3
FB_2A
1 2
C83
0.1U
88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller Preliminary Datasheet
4-6 88SE9345 Board Schematics
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
Note: This diagram is for reference only. Contact your Marvell field applications engineer for the latest schematics.
Figure 4-4 88SE9345 Example Board Schematic (4 of 4)
Note: This diagram is for reference only. Contact your Marvell field applications engineer for the latest schematics.
SYSTEM 1.0V/ 3A
REG_PGOOD
VSET1
PSET1
VSET2
PSET2
SDI
3V3
3V3
3V3
3V3
2V5
1V8
3V3
1V0
3V3
3V3
REG_PGOOD2
MTH2
Hole
1
C123
22U
+ C14222uF6V3C0805
C14747nF C0603
R-VSET1
165K
R_PSET1
0R
+ C14322uF6V3C0805
C131
0.1U
R62100K
R64
0R
R59
10R
C129
22U
L32.0uH
C126
22U
R148
R0402
10
C127
0.1U
R60
10K
+ GREEN
LED2
R67100K
+
C14522uF6V3C0805
C124
22U
R6518.7K-1%R0402
R66 1K-5% R0402
C146
C0805
4.7uF10V
C121
0.1UR61
100K
+
C14422uF6V3C0805
C122
0.1U
C130
0.1U
C128
22U
R_PSET2
0R
NORMAL:5APEAK:7.5A
U9 88PG877
VS
ET
1
EN2
VBS3
SW14
PVIN5PVIN6PVIN7
SW28
PGND9
PGND10
PGND11
SW312
SGND13
SFB14
SVIN15
SDI16
POR17
PS
ET
18
SW419
L22.0uH
C125
22U
MTH1
Hole
1
U8
88PG8237
EN1
SFB22
SVIN3
SGND4
SFB15
SDI6
SW1_17
PGND18
SW1_09
PVIN110
POR111
PSET112
VSET113
VSET214
PSET215
POR216
PVIN217
SW2_018
PGND219
SW2_120
R_VSET2
97.6K
L6
FDV0630-1R03.1A
1.0uH
R58100K
C141
C0402
100nF10V
R158
1K-5%
Part 1: Chip OverviewLayout Guidelines
Layer Stack-Up 4-7
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
4.2 Layer Stack-Up
The following layer stack up is recommended
Layer 1–Topside, Parts, Low and High-Speed Signal Routes, and Power Routes
Layer 2–Solid Ground Plane
Layer 3–Power Plane and Low Speed Signals
Layer 4–Power Plane
Layer 5–Solid Ground Plane
Layer 6–Bottom Layer, Low and High-Speed Signal Routes, and Power Routes
5 mil traces and 5 mil spacing are the recommended minimum requirements.
4.2.1 Layer 1–Topside, Parts, Low and High-Speed Signal Routes, and Power Routes
All active parts are to be placed on the topside. Some of the differential pairs for SATA and PCIe are routed on the top layer, differential 100 ohm impedance needs to be maintained for those high-speed signals.
4.2.2 Layer 2–Solid Ground Plane
A solid ground plane should be located directly below the top layer of the PCB. This layer should be a minimum distance below the top layer in order to reduce the amount of crosstalk and EMI. There should be no cutouts in the ground plane. Use of 1 ounce copper is recommended.
4.2.3 Layer 3–Power Plane and Low Speed Signals
Use solid planes on layer 3 to supply power to the ICs on the PCB. Avoid narrow traces and necks on this plane.
4.2.4 Layer 4–Power Plane
Use solid planes on layer 4 to supply power to the ICs on the PCB. Avoid narrow traces and necks on this plane.
4.2.5 Layer 5–Solid Ground Plane
A solid ground plane should be located directly below the top layer of the PCB. This layer should be a minimum distance below the top layer in order to reduce the amount of crosstalk and EMI. There should be no cutouts in the ground plane. Use of 1 ounce copper is recommended.
88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller Preliminary Datasheet
4-8 Layer Stack-Up
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
4.2.6 Layer 6–Bottom Layer, Low and High-Speed Signal Routes, and Power Routes
Some of the differential pairs for SATA and PCIe are routed on the top layer, differential 100Ω impedance needs to be maintained for those high speed signals.
Part 1: Chip OverviewLayout Guidelines
Power Supply 4-9
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
4.3 Power Supply
The 88SE9345 operates using the following power supplies:
VDD Power (1.0V) for the digital core
PCIe Analog Power Supply (1.8V)
SATA Analog Power Supply (2.5V)
General I/O Power (3.3V)
4.3.1 VDD Power (1.0V)
All digital power pins (VDD pins) must be connected directly to a VDD plane in the power layer with short and wide traces to minimize digital power-trace inductances.
Use vias close to the VDD pins to connect to this plane and avoid using the traces on the top layer. Marvell recommends placing capacitors around the three sides of the PCB near VDD pins with the following dimensions:
0.001 µF (1 capacitor)
0.1 µF (2 capacitors)
2.2 µF (1 ceramic capacitor)
The combinations of small capacitors are used to suppress switching noise at various frequency ranges. The 2.2 µF ceramic decoupling capacitor is required to filter the lower frequency power-supply noise.
To reduce system noise, place high-frequency surface-mount monolithic ceramic bypass capacitors as close as possible to the channel VDD pins. Place at least one decoupling capacitor on each side of the IC package.
4.3.2 PCIe Analog Power Supply (1.8V)
The analog supply provides power for the PCIe link’s high speed serial signals. To ensure high speed link operation, use a series of bypass capacitors for the supplies. A typical capacitor value combination is 1 nF, 0.1µF, and 2.2 µF.
4.3.3 SATA Analog Power Supply (2.5V)
The analog supply provides power for the SATA link’s high speed serial signals. To ensure high speed link operation, use a series of bypass capacitors for the supplies. A typical capacitor value combination is 1 nF, 0.1µF, and 2.2 µF.
4.3.4 General I/O Power (3.3V)
A general I/O power supply provides power to the GPIO, flash and I2C blocks. A stable and clean power source is desired. Use proper bypass capacitors to provide a clean power source with good stability. A typical capacitor value combination is 0.1µF, and 2.2 µF.
88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller Preliminary Datasheet
4-10 Power Supply
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
4.3.5 Bias Current Resistor (RSET)
Connect a 6.04KΩ (1%) resistor between the ISET pin and the adjacent top ground plane. This resistor should lie as close as possible to the ISET pin. Avoid routing noisy signals close to the ISET pin.
Part 1: Chip OverviewLayout Guidelines
PCB Trace Routing 4-11
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
4.4 PCB Trace Routing
The stack-up parameters for the reference board are shown in Table 4-1.
Table 4-1 PCB Board Stack-up Parameters
LayerLayer
DescriptionCopper Weight
(oz)Target Impedance
(±10%)
1 Signal 0.5 50
2 GND 1 N/A
3 Power and Signal
1 50
4 Power 1 N/A
5 GND 1 N/A
6 Signal 0.5 50
88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller Preliminary Datasheet
4-12 Recommended Layout
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
4.5 Recommended Layout
High-speed designs must consist of a good board stack-up and careful consideration of the power planes. For the 88SE9345, the following power planes are required:
VDDIO_C, VDDIO_D, and VDDIO_P power plane (3.3V power source for the digital I/O pins)
VDD (1.0V power source for the core and digital circuitry)
VAA (2.5V power source for SATA analog)
AVDD (1.8V power source for PCIe analog)
Solid ground planes are recommended. However, special care should be taken when routing VAA, AVDD, and VSS pins.
The following general tips describe what should be considered when determining your stack-up and board routing. These tips are not meant to substitute for consulting with a signal-integrity expert or doing your own simulations.
Note: Specific numbers or rules-of-thumb are not used here because they might not be applicable in every situation.
Do not split ground planes.
Keep good spacing between possible sensitive analog circuitry on your board and the digital signals to sufficiently isolate noise. A solid ground plane is necessary to provide a good return path for routing layers. Try to provide at least one ground plane adjacent to all routing layers (see Figure 4-5).
Keep trace layers as close as possible to the adjacent ground or power planes.
This helps minimize crosstalk and improve noise control on the planes.
Figure 4-5 Trace Has At Least One Solid Plane For Return Path
When routing adjacent to only a power plane, do not cross splits.
Route traces only over the power plane that supplies both the driver and the load. Otherwise, provide a decoupling capacitor near the trace at the end that is not supplied by the adjacent power plane.
Critical signals should avoid running parallel and close to or directly over a gap.
This would change the impedance of the trace.
Separate analog powers onto opposing planes.
This helps minimize the coupling area that an analog plane has with an adjacent digital plane.
GND
V2
V1
Part 1: Chip OverviewLayout Guidelines
Recommended Layout 4-13
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
For dual strip-line routing, traces should only cross at 90 degrees.
Avoid more than two routing layers in a row to minimize tandem crosstalk and to better control impedance.
Planes should be evenly distributed in order to minimize warping.
Calculating or modeling impedance should be made prior to routing.
This helps ensure that a reasonable trace thickness is used and that the desired board thickness is available. Consult with your board fabricator for accurate impedance.
Allow good separation between fast signals to avoid crosstalk.
Crosstalk increases as the parallel traces get longer.
When packages become smaller, route traces over a split power plane
Smaller packages force vias to become smaller, thereby reducing board thickness and layer counts, which might create the need to route traces over a split power plane. Some alternatives to provide return path for these signals are listed below.
Caution must be used when applying these techniques. Digital traces should not cross over analog planes, and vice-versa. All of these rules must be followed closely to prevent noise contamination problems that might arise due to routing over the wrong plane.
By tightly controlling the return path, control noise on the power and ground planes can be controlled.
Place a ground layer close enough to the split power plane in order to couple enough to provide buried capacitance, such as SIG-PWR-GND (see Figure 4-6). Return signals that encounter splits in this situation simply jumps to the ground plane, over the split, and back to the other power plane. Buried capacitance provides the benefit of adding low inductance decoupling to your board. Your fabricator may charge for a special license fee and special materials. To determine the amount of capacitance your planes provide, use the following equation:
Where ER is the dielectric coefficient, L • W represents the area of copper, and H is the separation between planes.
Provide return-path capacitors that connect to both power planes and jumps the split. Place them close to the traces so that there is one capacitor for every four or five traces. The capacitors would then provide the return path (see Figure 4-7).
Allow only static or slow signals on layers where they are adjacent to split planes.
Figure 4-6 shows the ground layer close to the split power plane.
Figure 4-6 Close Power and Ground Planes Provide Coupling For Good Return Path
C 1.249 10 13–• Er• L• W H⁄•=
V2 PLANE
GND PLANE
V1 PLANEH
88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller Preliminary Datasheet
4-14 Recommended Layout
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
Figure 4-7 shows the thermal ground plane in relation to the return-path capacitor.
Figure 4-7 Suggested Thermal Ground Plane On Opposite Side of Chip
V1
V2
Part 1: Chip OverviewElectrical Specifications
5-1
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
5 ELECTRICAL SPECIFICATIONS
This chapter contains the following sections:
Absolute Maximum Ratings
Recommended Operating Conditions
DC Electrical Characteristics
Thermal Data
AC Timing
88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller Preliminary Datasheet
5-2 Absolute Maximum Ratings
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
5.1 Absolute Maximum Ratings
CAUTION: Exposure to conditions at or beyond the maximum rating may damage the device. Operation beyond the recommended operating conditions (Table 5-2) is neither recommended nor guaranteed.
Note: Before designing a system, it is recommended that you read application note AN-63: Thermal Management for Marvell Technology Products. This application note presents basic concepts of thermal management for integrated circuits (ICs) and includes guidelines to ensure optimal operating conditions for Marvell Technology's products.
Table 5-1 Absolute Maximum Ratings
Parameter Symbol Minimum Typical Maximum Units
Absolute Analog Power for PCIe PHY AVDD[8:0] 1.62 1.8 1.98 V
Absolute Analog Power for SATA PHY, Chip PLL
VAA[7:0], VAA_ANA
2.25 2.5 2.75 V
Absolute Power for Digital Core VDD 0.9 1.0 1.1 V
Absolute Digital I/O Power VDDO1/VDDO2 3 3.3 3.6 V
Part 1: Chip OverviewElectrical Specifications
Recommended Operating Conditions 5-3
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
5.2 Recommended Operating Conditions
CAUTION: Operation beyond the recommended operating conditions is neither recommended nor guaranteed.
Table 5-2 Recommended Operating Conditions
Parameter Symbol Minimum Typical Maximum Units
Analog Power for PCIe PHY AVDD[8:0] 1.71 1.8 1.89 V
Analog Power for SATA PHY, Chip PLL
VAA[7:0], VAA_ANA
2.38 2.5 2.63 V
Digital Core Power VDD 0.95 1.0 1.05 V
Digital I/O Power VDDO1/VDDO2 3.14 3.3 3.47 V
Internal Bias Reference ISET, PIN_ISET 5.74 6.04 6.34 KΩ
Ambient Operating Temperature TA 0 N/A 70 °C
Junction Operating Temperature TJ 0 N/A 125 °C
88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller Preliminary Datasheet
5-4 DC Electrical Characteristics
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
5.3 DC Electrical Characteristics
CAUTION: Operation beyond the recommended operating conditions is neither recommended nor guaranteed.
Table 5-4 shows the internal pull-up and pull-down strength.
Table 5-3 DC Electrical Characteristics
Parameter Symbol Minimum Typical Maximum Units
Analog Power for PCIe PHY 1.8V IAVDD 0.19 0.215 0.24 A
Analog Power for SATA PHY 2.5V, Chip PLL
IVAA 0.55 0.62 0.69 A
Digital Core Power IVDD 1.5 1.94 2.93 A
Digital I/O Power IVDDO 9.2 10.5 11.6 mA
Input Low Voltage of Digital I/O VIL -0.4 N/A 0.3 × VDDOx V
Input High Voltage of Digital I/O VIH 0.7 × VDDOx N/A VDDOx + 0.4 V
Output Low Voltage of Digital I/O VOL N/A 0.13 N/A V
Output High Voltage of Digital I/O VOH 2.0 VDDOx*
* VDDOx: VDDO1/VDDO2.
N/A V
Table 5-4 Internal Pull-Up and Pull-Down Strength
Specifications Condition Minimum Nominal Maximum Unit
Pull-Up Strength V(PAD) = 0.5 × VDDO 10 N/A 50 µA
V(PAD) = 0 10 N/A 65 µA
Pull-Down Strength V(PAD) = 0.5 × VDDO 10 N/A 50 µA
Part 1: Chip OverviewElectrical Specifications
Thermal Data 5-5
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
5.4 Thermal Data
It is recommended to read application note AN-63 Thermal Management for Selected Marvell® Products (Document Number MV-S300281-00) and the ThetaJC, ThetaJA, and Temperature Calculations White Paper, available from Marvell, before designing a system. These documents describe the basic understanding of thermal management of integrated circuits (ICs) and guidelines to ensure optimal operating conditions for Marvell products.
Table 5-5 provides the thermal data for the 88SE9345. The simulation was performed according to JEDEC standards. The heat sink is 25.4 mm × 25.4 mm × 25 mm.
Table 5-5 shows the values for the package thermal parameters for the 481-ball TFBGA mounted on a 4-layer PCB.
Table 5-5 Package Thermal Data, 4-Layer PCB*
* All data is based on parts mounted on a 4” x 4.5” JEDEC 4L PCB.
Parameter DefinitionAirflow Value
0 m/s 1 m/s 2 m/s 3 m/s
θJA Thermal resistance: junction to ambient (no heat sink)
16.2 C/W 13.9 C/W 13.0 C/W 12.6 C/W
θJA Thermal resistance: junction to ambient (with heat sink)
11.7 C/W 8.4 C/W 7.8 C/W 7.6 C/W
θJC Thermal resistance: junction to case
5.30 C/W N/A N/A N/A
88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller Preliminary Datasheet
5-6 AC Timing
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
5.5 AC Timing
This section discusses the following topics:
SATA
PCIe
Parallel Flash and NVSRAM
5.5.1 SATA
This product conforms to AC timing requirements as specified in the Serial ATA Revision 3.0 Specification (www.sata-io.org).
5.5.2 PCIe
This product conforms to AC timing requirements as specified in the PCIe® Base 2.0 specification (www.pcisig.com/).
5.5.3 Parallel Flash and NVSRAM
This section describes the timing for Parallel Flash and NVSRAM.
Part 1: Chip OverviewElectrical Specifications
AC Timing 5-7
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
Figure 5-1 illustrates the Parallel Flash and NVSRAM Read timing, and Table 5-6 provides parameter information for the timing diagram.
Figure 5-1 Parallel Flash / NVSRAM Read Timing
Note: Tclk—Internal system clock cycle, default value is 3.33ns.
Table 5-6 Timing Parameters for Figure 5-1, Parallel Flash / NVSRAM Read Timing
Parameter Description NVSRAM Parallel Flash Unit
tRC Read Cycle Time (NV_RD_CYCLE_TM (R0C968h [7:0]) + 2) × Tclk
(FLSH_RD_CYCLE_TM (R0C978h [7:0]) + 2) × Tclk
ns
tRCEL Read CE Assert Time (NV_RD_CE_ASSRT_TM (R0C96Ch [23:16]) + 1) × Tclk
(FLSH_RD_CE_ASSRT_TM (R0C97Ch [23:16]) + 1) × Tclk
ns
tRCEH Read CE Deassert Time (NV_RD_CE_DEASSRT_TM (R0C96Ch [31:24]) + 2) × Tclk
(FLSH_RD_CE_DEASSRT_TM (R0C97Ch [31:24]) + 2) × Tclk
ns
tOEL Read OE Assert Time (NV_RD_OE_ASSRT_TM (R0C96Ch [7:0]) + 1) × Tclk
(FLSH_RD_OE_ASSRT_TM (R0C97Ch [7:0]) + 1) × Tclk
ns
tOEH Read OE Deassert Time (NV_RD_OE_DEASSRT_TM (R0C96Ch [15:8]) + 2) × Tclk
(FLSH_RD_OE_DEASSRT_TM (R0C97Ch [15:8]) + 2) × Tclk
ns
tACC Read Data Latch Time (NV_RD_DATA_LTCH_TM (R0C968h [15:8]) + 1) × Tclk - 20
(FLSH_RD_DATA_LTCH_TM (R0C978h [15:8]) + 1) × Tclk - 20
ns
Address Valid
Input Data Valid
tRC
tRCEH
tRCEL
tOEL
tACC
tOEH
P_ADDR
CE_N
OE_N
P_DATA
88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller Preliminary Datasheet
5-8 AC Timing
Copyright © 2015 Marvell Doc No. MV-S109418-00 Rev. AApril 21, 2015 Document Classification: Proprietary
Figure 5-2 illustrates the Parallel Flash and NVSRAM Write timing, and Table 5-7 provides parameter information for the timing diagram.
Figure 5-2 Parallel Flash / NVSRAM Write Timing
Table 5-7 Timing Parameters for Figure 5-1, Parallel Flash / NVSRAM Read Timing
Parameter Description NVSRAM Parallel Flash Unit
tWC Write Cycle Time (NV_WRT_CYCLE_TM (R0C960h [7:0]) + 2) × Tclk
(FLSH_WRT_CYCLE_TM (R0C970h [7:0]) + 2) × Tclk
ns
tWCEL Write CE Assert Time (NV_CE_ASSRT_TM (R0C960h [15:8]) + 1) × Tclk
(FLSH_CE_ASSRT_TM (R0C970h [15:8]) + 1) × Tclk
ns
tWCEH Write CE Deassert Time (NV_CE_DEASSRT_TM (R0C960h [23:16]) + 2) × Tclk
(FLSH_CE_DEASSRT_TM (R0C970h [23:16]) + 2) × Tclk
ns
tWEL Write WE Assert Time (NV_WRT_WE_ASSRT_TM (R0C964h [7:0]) + 1) × Tclk
(FLSH_WRT_WE_ASSRT_TM (R0C974h [7:0]) + 1) × Tclk
ns
tWEH Read WE Deassert Time (NV_WRT_WE_DEASSRT_TM (R0C964h [15:8]) + 2) × Tclk
(FLSH_WRT_WE_DEASSRT_TM (R0C974h [15:8]) + 2) × Tclk
ns
tDL Write Data IO Enable Time
(NV_WRT_DATA_IO_EN_TM (R0C964h [23:16]) + 1) × Tclk
(FLSH_WRT_DATA_IO_EN_TM (R0C974h [23:16]) + 1) × Tclk
ns
tDH Write Data IO Disable Time
(NV_WRT_DATA_IO_DSBL_TM (R0C964h [31:24]) + 2) × Tclk
(FLSH_WRT_DATA_IO_DSBL_TM (R0C974h [31:24]) + 2) × Tclk
ns
Address Valid
tWC
tWCEH
tWCEL
tWEL
tDH
tWEH
Output Data ValidtDL
P_ADDR
CE_N
WE_N
P_DATA
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