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Logic Design Lab 4
Verilogintroduction
Logic Design Lab 4Logic Design Lab 4
VerilogVerilogintroductionintroductionInstructor:Instructor: KuanKuan Jen Lin (Jen Lin ())
EE--Mail:Mail: [email protected]@mails.fju.edu.twWeb:Web: http://http://vlsi.ee.fju.edu.tw/teacher/kjlin/kjlin.htmvlsi.ee.fju.edu.tw/teacher/kjlin/kjlin.htmRoom: SF 727BRoom: SF 727B
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FPGA Design FlowDesign entry
Synthesis
Functional simulation
Fitting
Programming &
configuration
Timing simulation
HDL programming
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Schematic Capture
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Simulation
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What is an HDL?
A Hardware Description Language (HDL) is a highlevel programming language with special languageconstructs used to model the function of
hardware logic circuits. The special language constructs provide you the
ability to:Describe the connectivity (structure) of a
circuitDescribe the functionality (bhavior) of a
circuitDescribe a circuit at various levels of
abstractionDescribe the timing information and timing
constraints of a circuitExpress concurrency
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Why Use an HDL?
Model the design in higher level of abstraction Reduce the design capturing effort
Easy for handling complex design Separate from implementation, increase the protability
Potential for design re-use
Mix behavioral/structural descriptioms in adesign Model datapath and regular portion of circuit
structurally
Model control and regular portion of circuit behaviorally
Model the design and testbench with the samelanguage
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First Example
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Structural Description(An SR Latch)
name of the
module
Port declaration
Type declaration
primitive gates with
names and
interconnections
module nandLatch(q, qBar,set, reset);ouput q, qbar;input set, reset;nand g1 (q, qBar, set);nand g2 (qBar, q, reset);
endmodule
A module
is defined
g1
g2
q
qBar
set
Reset
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Primitives
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Overview of Verilog Module
A verilog module includes the following parts:
module module_name (port list) ;Declarations of port-type, wires, reg
Instantiation ofPrimitives & Low-level modules
assign-dataflow statements
endmodule
always & initialBehavioral blocks Task & function (testbench)
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2X4 Decoder with enable
high-active or low-active
Source: Mano, DigitalDesign, 3th edition.
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Structural Description (pp. 177)module decoder_2x4(D, A, B, enable);
output [3:0] D;input A, B, enable;
wire not_A, not_B, not_enable
not (not_A, A);
not (not_B, B);not (not_enable, enable);
nand (D[0], not_A, not_B, not_enable);nand (D[1], not_A, B, not_enable);nand (D[2], A, not_B, not_enable);nand (D[3], A, B, not_enable);
endmodule
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Continuous assignments( pp. 182)(Data flow description)
module decoder_2x4(D, A, B, enable);
output [3:0] D;input A, B, enable;
assign D[0] = ~(~A & ~B & ~enable);assign D[1] = ~(~A & B & ~enable);
assign D[2] = ~(A & ~B & ~enable);assign D[4] = ~(A & B & ~enable);endmodule
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Operators (1/2)
Logic operators : return a value.&&, ||, !
assign a = b && c;
Bitwise logic operators : return result in
bus form.&, |, ~,assign a[2:0] = b[2:0] & c[2:0];
Equality operator: ==, != Reduction operator: a = &b;
Relational operator: >=, > ,
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Operators (2/2)
Are all Verilog operators synthesizable? Conditional operators
e.g. assign a = c ? x : y ; Shift operators
e.g. assign a = b
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Module Hierarchymodule fulladder(S, Co, A, B, Ci);
input A, B, Ci;
output S, Co;
assign Co = { (A ^ B) & Ci } | (A & B);
assign S = A ^ B ^ Ci;
endmodule
A
B
Ci
S
Co
A B
SCiCo
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module adder(S, C4, A, B, C0);input [3:0] A, B;
input C0;output [3:0] S;output C4;wire C1, C2, C3; //Intermediate carries//Instantiate the fulladder
fulladder FA0(S[0], C1, A[0], B[0], C0);fulladder FA1(S[1], C2, A[1], B[1], C1);fulladder FA2(S[2], C3, A[2], B[2], C2);fulladder FA3(S[3], C4, A[3], B[3], C3);
endmodule
A B
SCiCo FA3
A B
SCiCo FA2
A B
SCiCo FA1
A B
SCiCo FA0
A[3]
S[3] S[2] S[1] S[0]
C4
A[2] A[1] A[0]B[3] B[2] B[1] B[0]
C2 C1 C0C3
Must not miss
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Behavioral Description
module decoder_2x4(D, A, B, enable);output [3:0] D;
input A, B, enable;always @(A, B, enable)begin
D=4b1111; // Dont miss this line
if (~A & ~B & ~enable) D[0] = 0;if (~A & B & ~enable) D[1] = 0;if ( A & ~B & ~enable) D[2] = 0;
if (A & B & ~enable) D[3] = 0;endendmodule
Sensitive list
C-likeProceduralstatements
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always (sensitive list) begin
C-like procedural statements.
endRules for combinational circuitsAll inputs to your combinational function must be
listed in the sensitive list.Combinational output(s) must be assigned to everycontrol path.
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Behavioral Description-2module decoder_2x4(D, A, B, enable);
output [3:0] D;
input A, B, enable;always @(A, B, enable)begin
D=4b1111; // Dont miss this line
case ( {A, B, enable} )3b000: D[0] = 0;3b010: D[1] = 0;
3b100: D[2] = 0;3b110: D[3] = 0; // Other cases???
endcase
endendmodule
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Behavioral modelling
A behavioral model of a module is anabstraction of how the module works.
always
defines a processSuspend execution of this always processuntil a change occurs one of variable in thesensitive list.
Procedural statement C programming-like Conversely, structural descriptions are
concurrent statements.
Within an always process, the left sideof = must be declared as register.Register does not always need a physical
storage.
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Verilog
module name( port list)Declarartion of signals
Interconnections of low-level modules or primitivesassign p= a&bassign always@(...) begin.endalways@(...) begin
..end
endmodule
Concurrent
running
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Why use behavioral descrption?
Use behavioral model on early designstage.HDLs are designed originally for
simulation
Write testbench Partial behavioral descriptions can be
synthesized to circuits.
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Create a Testbench For a Module
testbench
Test Generator
AndMonitor
Design Under
Test(DUT)
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module_testBench
module testBench;
wire w1, w2, w3, w4, w5;binaryToESeg d (w1, w2, w3, w4, w5);
test_bToESeg t (w1, w2, w3, w4, w5);
endmodule
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Test module
module test_bToESeg(output reg A, B, C, D, input eSeg);
initial // two slashes introduce a single line commentbegin$monitor ( $time,,"A = %b B = %b C = %b D = %b, eSeg = %b",
A, B, C, D, eSeg);//waveform for simulating the nand lip lop#10 A = 0; B = 0; C = 0; D = 0;#10 D = 1;#10 C = 1; D = 0;#10 $finish;end
endmodule
0 A = x B = x C = x D = x, eSeg = x10 A = 0 B = 0 C = 0 D = 0, eSeg = x12 A = 0 B = 0 C = 0 D = 0, eSeg = 120 A = 0 B = 0 C = 0 D = 1, eSeg = 122 A = 0 B = 0 C = 0 D = 1, eSeg = 0
30 A = 0 B = 0 C = 1 D = 0, eSeg = 032 A = 0 B = 0 C = 1 D = 0, eSeg = 1
I t ti f D si d
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Interconnection of Design andTest Modules
testbench
Test Generator
AndMonitor
Design Under
Test(DUT)
eSeg
A
B
C
D
eSeg
A
B
C
D
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Standard Model of a Moore FSM
00/0 01/1
11/0
0
10
01
1
reset
Comb.
Circuit
State
Registers
OutputInput
Comb.
Circuit
Z
D Q
clk
D Q
clk
~Q1
Q0
Q0
x
x
Q1
clk
reset
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//D flip-flopmodule D_FF(D, Q, CLK, RST);input D, CLK, RST;output Q;reg Q;always @(posedge CLK or
negedge RST)if(~RST)Q = 1'b0;
elseQ = D;
endmodule
module state_machine(x, reset,clk, z);
input x, Reset, clk;
output z;
wire D1, D0;
assign z =~Q1 & Q0;assign D1 =Q0 & x;
assign D0= x | Q1;
D_FF A1(D1, Q1, clk, reset);D_FF A0(D0, Q0, clk, reset);
endmodule
Z
D Q
clk
D Q
clk
~Q1
Q0
Q0
x
x
Q1
clk
reset
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behavioral model of FSM
module fsm(output reg z,
input x, clk, reset
reg [1:0] curStste, nextStste;always @(x, curState) beginz=~curState[1] & curState[0];nextState=0;if (curState ==0)
if (x) nextState=1;if (curState ==1)
if (x) nextState=3;if (curState ==3)
if (x) nextState=3;else nextState =1;
endend
00/0 01/1
11/0
0
1 0
01
1
reset
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D_FF
always @(posedge clk, negedge reset) begin
if (~reset)
curState
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Module Hierarchy
board
Display driver
m16 m555
A counter example
clk
count
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Top module
module boardWithConcatenation;
wire clock, eSeg, w3, w2, w1, w0;
m16 counter ({w3, w2, w1, w0}, clock);m555 clockGen (clock);
binaryToESeg disp (eSeg, w3, w2, w1, w0);
initial
$monitor ($time,,,"count=%d, eSeg=%d", {w3, w2,
w1, w0}, eSeg);endmodule
instantiate
Bus concatenation
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m16 (Counter)
module m16
(output reg [3:0] ctr = 1, input clock);
always @(posedge clock)ctr
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A clock generator (simulation)
module m555
(output reg clock);
initial
#5 clock = 1;
always#50 clock = ~ clock;
endmodule
Rules for Synthesizable
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Rules for SynthesizableCombinational Circuits
All inputs to your combinationalfunction must be listed in the
sensitive list.
Combinational output(s) must beassigned to every control path.
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module synAutoSensitivity (input a, b, c,output reg f);always @( a, b ,c)
if (a == 1)f = b;
elsef = c;
endmodule
always @( *)
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module synAutoSensitivity (input a, b, c,output reg f);always @(*) begin
f = c;if (a == 1)
f = b;endendmodule
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Inferred Latches
amodulesynAutoSensitivity
(input a, b, c,
output reg f);
always @(*)if (a == 1)
f = b & c ;// else f = ?
endmodule
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Use case Statement
Using Case StatementUsing full_case (attributes) explicitly
specify (truth table form) or a defaultitem to fully specify.
Specify Dont Care situations for inputand output.
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Use case Statement (cont.) Truth table method
List each inputcombination
Assign to output(s) ineach case item.
module fred(output reg f,input a, b, c);
always @ (a or b or c)case ({a, b, c})
3b000: f = 1b0;
3b001: f = 1b1;3b010: f = 1b1;3b011: f = 1b1;3b100: f = 1b1;3b101: f = 1b0;3b110: f = 1b0;3b111: f = 1b1;
endcaseendmodule
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Use case Statement (cont.)
module fred(output reg f,
input a, b, c);always @(a or b or c)case({a,b,c})
3b000: f = 1b0;3b101: f = 1b0;3b110: f = 1b0;default: f = 1b1;
endcaseendmodule
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Specify dont care
Rules
You cant sayif (a == 1bx)this has meaning insimulation, but not in
synthesis.However, an unknown x
on the right-hand sidewill be interpreted as adont care. The inverse function was implemented;
xs taken as ones.
00 01 11 10
0
1
ab
c 1 1
11 1
0x
x
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Specify dont care (cont.)
module caseExample((output reg f,
input a, b, c);always @ (a or b or c)case ({a, b, c})
3b001: f = 1b1;
3b010: f = 1b1;3b011: f = 1b1;3b100: f = 1b1;3b110: f = 1b0;3b111: f = 1b1;default: f = 1bx;
endcase
endmodule
Rules for Synthesizable Sequential
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Circuits
The sensitive list includes only the edgesof the clock, reset and preset conditions.
Inside the always block, the reset andpreset conditions are specified first. if (~reset),,,,
Any register assigned to in the sequentialalways block will be implemented using flip-flops.
The
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Fli Fl i f
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Flip Flop inferences
module synDFF( q, clock, d);input clock, d;output q;
reg q;always @(posedge clock,
negedge reset, posedgeset)
beginif (~reset)
q
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Conclusion
Required from the presence ofan edge specifier, the tool infersa flip flop. All registers in thealways block are clocked by thespecified edge.
No affect.Inferred flipflop
Not allowed.There must existat least one controlpath where anoutput is not assign
to. From thisomission,the toolinfers a latch.
Interred latch
Not allowed. The whole input setmust be in the sensitivity list.Theconstruct @(*) assure this.
An output must beassigned to in allcontrol path
Combinational
Edge Specifiers in Sensitivity ListOutput Assign ToType of Logic
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