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UC Berkeley EE241 B. Nikolic
High Performance Signaling
Sources:
Dally, Poulton, Digital Systems Engineering,
Cambridge Univ. Press, 1998.
Johnson, Graham, High-Speed Digital Design, Prentice-Hall, 1993.
Bakoglu, Circuits, Interconnections and Packaging for VLSI,
Addison-Wesley, 1990.
Rabaey, EE241 lecture notes 1998.
UC Berkeley EE241 B. Nikolic
Limits of Electrical Signaling
Horowitz, Yang, Sidiropoulos,High-Speed Electrical Signaling: Overview and Limitations,
IEEE Micro, 1/98
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UC Berkeley EE241 B. Nikolic
Multiplexed Transmitter
Different on- and off-chip bandwidths
Transmitters have to drive low impedance
UC Berkeley EE241 B. Nikolic
Multiplexer
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UC Berkeley EE241 B. Nikolic
Tx Multiplexer
Pulse width limited Overlapped signals
From Horowitz
UC Berkeley EE241 B. Nikolic
Performance Limit
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UC Berkeley EE241 B. Nikolic
Demultiplexing Receiver
UC Berkeley EE241 B. Nikolic
Demultiplexing Data
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UC Berkeley EE241 B. Nikolic
PLLs vs. DLLs
UC Berkeley EE241 B. Nikolic
PLL and DLL ResponseResponse to a supply step
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UC Berkeley EE241 B. Nikolic
Delay Element and Interpolator
UC Berkeley EE241 B. Nikolic
Phase Picking
Phase-picking data recovery
Clock waveforms are oversampling the data stream
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UC Berkeley EE241 B. Nikolic
Cable properties
Frequency response12-meter and 6-meter RG-55U
Time domain response of a squarepulse into 12m cable
UC Berkeley EE241 B. Nikolic
Predistorted Pulse
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UC Berkeley EE241 B. Nikolic
4-PAM Data Eye
UC Berkeley EE241 B. Nikolic
Power and Ground Distribution
GND
VDD
Logic
GND
VDD
Logic
GND
VDD
(a) Finger-shaped network (b) Network with multiple supply pins
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UC Berkeley EE241 B. Nikolic
Power Distributionl Supply current is brought on
chip at specific locations
on the edge for most chipswhich areperipherally
bonded
distributed over the area ofthe chip for area bonded(C4,
solder ball) chips
l Loads consume this current at
different locations on the chip
at different timesl There is often a large parasitic
inductance associated with
each bond-wire or solder-ball
(0.1-10nH)
l Current is distributed from
the bond pads to the loads
on thin metal wires
0.04/ typical
l Load currents may be very
high
average current may be as
large as 20A for veryhotchips (50W at 2.5V)
peak current may be 4-5x
this amount (100A!)l L di/dt of bond wire and IR
drop across on-chip wires
are often a major source of
supply noiseFrom [Dally]
UC Berkeley EE241 B. Nikolic
On-Chip Bypass Capacitors
Much of the difference between peak and
average current may be supplied by local,
on-chip bypass capacitors
Bypass capacitors are also critical in
mitigating the effects of the supply bond-
wire inductance
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