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LAB 2
Introduction to VHDL and Operation of Full Adder/Subtractor
Using Xilin IS! "ro#ect $a%igator and
$e&s2 F"'A De%elop(ent Board
Ac)no*ledge(ents+ Developed by Bassam Matar, Engineering Faculty at Chandler-Gilbert Community
College, Chandler, Arizona Funded by NSF
$!!D+ A !idening gap e"ists bet!een !hat being taught in schools and s#ills currently being utilized by the!or#$orce %he &obs o$ the $uture are not labor intensive, they are brain intensive %echnicians and engineers no
longer !ire circuits or assemble a chip $rom scratch' they use so$t!are to run modern e(uipment %raditionally,
hard!are digital circuits re(uire at least $ive or si" )%ransistor %ransistor *ogic, %%*+ Cs %he !iring is o$tenvery comple" and messy Digital test e(uipment is usually needed to ma#e the system $unctional %%* Cs
technology is over thirty years old An FGA design minimizes the amount o$ electrical !iring and eliminated
the use o$ complicated test e(uipment %his type o$ technology allo!s students to concentrate on digital
principles and not on the electrical !iring *arger and more comple" pro&ects can be underta#en no! that thetedious manual procedures are automated .e !ill cover FGAs in detail later in the course /o!ever, in
general, an FGA is a chip that allo!s you to recon$igure it !ith any design %hus, i$ you ma#e a mista#e in
your design, you don0t need to replace !ires or chips, as you might have done using %%* nstead, you simplyrecon$igure the FGA !ith each updated design
Lab Su((ar&+ n previous labs, you became $amiliar !ith %%* technology and bread boarding n thislab, you !ill get $amiliar !ith modern !ay o$ digital technology using one o$ the leading digital design so$t!are
23ilin"4 and inter$acing !ith 5partan $e&s2 development board Combinational *ogic Circuits are used to
ma#e decisions based on a series o$ true statements that can be laid out in a truth table n previous years the67"", $amily )%%*+ circuits !ere used to design and build basic combinational logic circuits n this lab
activity, !e !ill 1+ use the so$t!are application 3ilin" ro&ect 8avigator 5E to dra! a schematic o$ $ull adderand then program it to the $e&s2 FGA device, 9+ :ou !ill be able to implement the same design using
hard!are language programming );/D*+ and
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Special Safet& 0e1uire(ents
5tatic electricity can damage the FGA devices used in this lab >se appropriate E5D methods to protect thedevices Be sure to !ear a grounded !rist-strap at all times !hile handling the electronic components in this
circuit
8o serious hazards are involved in this laboratory e"periment, but be care$ul to connect the components !ith
the proper polarity to avoid damage
Lab "reparation
• evie! your *D lecture $rom your class
• evie! 2ntroduction to 3ilin"4 previous lab
• ead %as#1 and !or# the $ull adder schematic $rom %as# 9 as prelab assignment
• >sing 3ilin" so$t!are, dra! the adder=subtractor circuit as sho!n in tas# < o$ this lab• Create the adder=subtractor 2>CF4 $ile that maps the input and output signals to the 8e"ys9 FGA
• Ac(uire re(uired hard!are components=e(uipment
• rint out the laboratory e"periment procedure that $ollo!s
!1uip(ent and aterials
Each team o$ students !ill need the test e(uipment, tools, and parts speci$ied belo! 5tudents should !or# inteams o$ t!o or three
est !1uip(ent and "o*er Supplies 3uantit
&
%he $ollo!ing items $rom the 3ilin"
• $ree so$t!are IS! WebPACK ( ***4ilin4co(5 that can be installed on
your personal computer or $ull version o$ 3ilin" in your classroom
• 8e"ys9 FGA #it including do!nload and po!er cable
• Free Digitlent Adept so$t!are
http==!!!digilentinccom=roducts=Detailc$m
8avath9,,9rodADE%9
1
Additional 0eferences+
1 3ilin" 8e"ys9 FGA e$erence Manual and 5chematic $romhttp==!!!digilentinccom=roducts=Detailc$mrod8E3:59
9
http://www.xilinx.com/http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,66,828&Prod=ADEPT2http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,66,828&Prod=ADEPT2http://www.digilentinc.com/Products/Detail.cfm?Prod=NEXYS2http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,66,828&Prod=ADEPT2http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,66,828&Prod=ADEPT2http://www.digilentinc.com/Products/Detail.cfm?Prod=NEXYS2http://www.xilinx.com/
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as) 1.
Getting to know FPGA $e&s2 board.
%he 8e"ys-9 is a po!er$ul digital system design plat$orm built around 3ilin" 5partan 5B port A list o$ the #ey $eatures
and their location on the board is listed belo!
Figure 1 FGA 8e"ys9 Board
5=9 mouse=#eyboard port
Hn-Board @I M/z Hscillator
C*JK@IM/z )B+
5even 5egme
Display
FGA C
Done *ED
E"pansion conn
eset Button
>5B Connector
o!er n
%!o 5-9
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User I/O
%he 8e"ys9 board includes several input devices, output devices, and data ports, allo!ing many
designs to be implemented !ithout the need $or any other components
Figure 9 FGA 8e"ys9 inputs and outputs Inputs: Slide Switches and Pushbuttons
Four pushbuttons and eight slide s!itches are provided $or circuit inputs ushbutton inputs arenormally lo!, and they are driven high only !hen the pushbutton is pressed 5lide s!itches generate
constant high or lo! inputs depending on their position ushbutton and slide s!itch inputs use a
series resistor $or protection against short circuits )a short circuit !ould occur i$ an FGA pin assignedto a pushbutton or slide s!itch !as inadvertently de$ined as an output+
Figure
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%as) 2+
I(ple(ent Full Adder sc6e(atic using Xilin IS! 7247 tools for $e&s2 F"'A board+
"art 7+lease re$er to previous lab on ho! to use 3ilin" 5E 191 so$t!are
1 .e need to set up our pro&ect correctly to re$lect $e&s2 FGA board
Design !ntr& Instructions
1 Hpen 3ilin" 5E 191 edition so$t!area 5elect 5tart
b All rograms
c 3ilin" 5E Design 5uite 191d 5E Design %ools
d ro&ect 8avigator
%he starting !indo!s should loo#
li#e this
Figure 7 3ilin" 5tarting .indo!
@
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9 Create a ne! pro&ect by selecting
File $rom the main menu
$e* "ro#ect
a n the 8e! ro&ect !indo!, na(e
your pro&ect Full_Adder in the pro&ectname te"t bo"
b n the "ro#ect Location selection bo",
enter the $older or directory !here
your pro&ect !ill be saved >se yourname as $or Student_Name and locate
the place !here you !ant to save all
your $iles )ie CN+c >nder op8Le%el Source &pe, select
HDL and clic# 8e"t as sho!n in
$igure @
Figure @ 8e! ro&ect .indo!
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@ Create the Full Adder circuit lease
re$er to previous lab $or more details onho! to create the schematic
Attach input and output pins to the circuit
and label them as sho!n
Figure Full Adder Circuits
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6 Hnce both $iles are created
)5chematic and >CF+, select
"ro#ectAdd Source and select both
$iles to be included as part o$ your pro&ect
Hnce you select the $iles and hit HJ,
you should get the $ollo!ing screen
Figure 1I Adding Full Adder 5chematic and >CF to the pro&ect
Double clic# on ,'enerate "rogra((ing File- under theimplement design on the le$t hand side $ all goes !ell, you
should get green chec# mar#s on ,"rogra((ing File'eneration 0eport- as sho!n
Figure 11 Generate rogramming File
R
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R %he so$t!are that !e !ill use $or
con$iguring the FGA is named Adept ,
$rom digilentinccom %o Access Adept
so$t!are, 5elect 5tart
rograms
DigilentAdeptAdept
1IChoose 8e"ys 9 board $rom theConnect roduct option
Chec# you >5B connection i$ you are not
able to locate the name 8e"ys 9
Clic# on bro!se and select full=adder4bit
$rom your pro&ect directory and clic# on
open
:ou !ill prompt !ith a !arning screen,
ignore it selecting yes
8o! clic# on progra( button ne"t toBro!se
!ou will pro"pt with the sa"e warning
screen as beore# ignore it selecting $es.
Figure 19 rogramming 8e"ys 9 FGA board
%he program gets do!nloaded to the FGA board
At this point the FGA should be programmed and ready $or test %est it by sliding the programmed s!itches
up and do!n $or H8 and HFF 5ee i$ the appropriate *EDs $or the t!o outputs turn on /ere is a truth tablethat should guide you !ith your test
1I
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S>?;5 ?A5
'7@
S>?75 ?B5
H7@
S>?25 ?.in5
7@
LD; ?SU5
7C
I I I HFF
I I 1 H8
I 1 I H8
I 1 1 HFF
1 I I H8
1 I 1 HFF
1 1 I HFF
1 1 1 H8
Figure 1
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as) 9+
I(ple(ent Full Adder *it6 ?VHDL5 using Xilin IS! tools for $e&s2 F"'A board+
;/D* is an acronym inside o$ an acronym %he S;0 stands $or ;ery /igh 5peed ntegrated Circuit );/5C+and S/D*0 stands $or /ard!are Descriptive *anguage ;/D* is a po!er$ul language !ith numerous language
constructs that are capable o$ describing very comple" behavior needed $or today0s programmable devices
"art 7+
.lose t6e pre%ious pro#ect and create a ne* one
1 Create a ne! pro&ect byselecting
File $rom the main menu
$e* "ro#ect
d n the 8e! ro&ect
!indo!, name your pro&ect
Full_Adder_&' in the
pro&ect name te"t bo"e n the "ro#ect Location
selection bo", enter the
$older or directory !here
your pro&ect !ill besaved >se your name $or
Student_Name and locate
the place !here you !antto save all your $iles )ie
CN+
$ >nder op8Le%el Source
&pe, select HDL instead
o$ schematic and clic#
$et
Figure 1@ 8e! ro&ect !ith ;/D*
19
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Figure 9I ;/D* *ayout o$ input and output
Bet!een begin and end +eha,ior
-line /02, !e need to enter the$ollo!ing e"pression $or Full Adder
Based on our previous schematic
design, the logic e"pression $or theoutput 5um and Cout are
Figure 91 Complete Full Adder ;/D*
Follo! the same steps as be$ore $rom part 1 to include >CF $ile as part o$ your pro&ect 5ynthesize, and
generate the programming to $ile
(e"o $our working hardware to $our tea""ates.
1@
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AS C+ est &our no*ledge
)mplement the *ollowin! +bit adder-subtractor schematic usin! .ilin/ )S0 tools *or Ne/ys1 FP2A board% Also,
implement the circuit with &'%
Create belo! schematic by choosing A(( symbol $rom 3ilin" library o$ devices
Figure 99 Adder=5ubtractor 5chematic
Add inputs and output ports
ser Constraint File ,ucf- that maps the input )A
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@ rogram your design in 8e"ys9 FGA
Demo your design to your instructor and complete the $ollo!ing truth table
ADD/SUB0A. B9 B2 B7 B; A9 A2 A7 A; S9 S2 S7 S; OFL ?&es/no5 .out
1 I 1 I 1 1 I I 1
I I 1 I 1 1 I I 1
6 nclude a copy o$ your schematic, ;/*D and >CF $iles in your lab report
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LAB 0!"O0 '0AD! SH!!
HA0D>A0! LAB 9Operation of Full Adder and Subtractor
Using Xilin IS! "ro#ect $a%igator and
$e&s2 F"'A De%elop(ent Board *it6 VHDL
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nstructor Assessment
Grading Criteria Ma"
ointsoints
0eport >riting 7:
Complete %itle age 1 Hrganization, 8eatness, Clarity and Concision 1I
5tatement o$ *earning Hb&ectives and Hutcomes 7
Description of Assigned as)s >or) "erfor(ed E Outco(e et :
as) 7+ Build, debug and demonstrate the operation o$ Full adder schematic in
3ilin" and 8e"ys9 FGA board Demo your design
9I
as) 2+ Build, debug and demonstrate the operation o$ Full adder VHDL in 3ilin"
and 8e"ys9 FGA board Demo your design
9I
as) 9+ Build, debug and demonstrate the operation o$ a 7 bit adder=subtractor
schematic in 3ilin" and 8e"ys9 FGA board 5imulate your circuit and e"haustivelytest all possible input combinations Demo your design nclude a copy o$ >CF $ile
and timing diagram in your lab report