Impact of Guardband Reduction on Design Process Outcomes
Kwangok Jeong ([email protected])Andrew B. Kahng ([email protected])
Kambiz Samadi ([email protected])
University of California, San Diego
Outline
Motivation
Background
Model Guardband Reduction
Design Flow & Test Cases
Experimental Results
Discussion: Impact on Yield
Conclusion
Is High Yield ALWAYS Better?
High yield is a general target of IC manufacturing But, more design effort and larger guardband are
required to make a chip immune to process / environment variations
99% Yield
70% Yield
Which is the better process?
Foundry 1 Foundry 2
Failed chip
Which is the better process?
How Much Benefit Comes From DFM? Many techniques claim to reduce guardband
by X%. Gupta et. al (DAC ’04): 40% guardband reduction by
adopting iso-dense variational timing analysis Sylvester et. al (VLSITSA’99): 60% of BEOL guardband
reduction
What is the value or cost of guardband? Designer: Minimize guardband Foundry: Maximize guardband
The impact of guardband on design process outcomes has never been quantified before.
How to decide it?
Outline
Motivations
Background
Model Guardband Reduction
Design Flow & Test Cases
Experimental Results
Discussion: Impact on Yield
Conclusion
Why do we need guardband? Cloud of uncertainties
Guardband should cover the uncertainties High coverage of variations lead to high yield Variability tolerance has been increased (cf. ITRS 2005)
Defocus/Dose Variation Misalignment
TemperatureVariation
Reliability
Non-Rectangular ShapesLine-End Shortening
Crosstalk
IR-drop
Imperfect regulatorsNon-Uniform CD
Erosion/Dishing in CMP
Electro-Migration
Hot-Carrier Injection
NBTI
Alpha-Particle
Line Edge Roughness
Mask CD Error
Wafer flatness Lens Aberration
Flare
FEOL(Front-End of Line)
BEOL(Back-End of Line)
Delay / LeakageVariation
Capacitance/ Resistance Variation
Guardband vs. Design Outcomes
Delay of the setup critical path must be fast at the worst corner
Increasing drive strength of cells
Setup critical
Setup critical
Hold critical
Delay of the hold critical path must be slow at the best cornerInserting delay cells
Increasing
Guard-
band
Slower @WC
Faster @BC
RobustTiming
Opt.
IncreasedArea
IncreasedRuntime
Increase cost
Increase cost
Outline
Motivations
Background
Model Guardband Reduction
Design Flow & Test Cases
Experimental Results
Discussion: Impact on Yield
Conclusion
Traditional Guardband Example of the guardband
We model the reduction of both FEOL and BEOL guardband
Process
Voltage Temp.FEOL BEOL
NMOS PMOS Cap. Res.
WORST Slow Slow Max. Min. Low(e.g. 0.9V)
High(e.g. 125C)
BEST Fast Fast Min. Max High(e.g. 1.1V)
Low(e.g. -40 C)
FEOL Guardband: Liberty Model Scaling Cell delay and Transition time:
M x M table Function (Input slew, Output load)
Input capacitance: 1 x 1 table
Guard Band Reduction Reduce guardband evenly
between best and worst cornerspin(Z) {
direction : output; max_capacitance : 0.0693; function : "(A1 A2)"; timing() { related_pin : "A1"; timing_sense : positive_unate; cell_rise(delay_template_7x7) { index_1 (“i1, i2, i3, i4, i5, i6, i7");// Input slew index_2 (“j1, j2, j3, j4, j5, j6, j7");// Output load values(“v11, v12, v13, v14, v15, v16, v17", \ “v21, v22, v23, v24, v25, v26, v27", \ “v31, v32, ...);}
Valuebest Valueworst
False derating using ‘k_factor’
0
Valuebest Valueworst
Example: 40% guardband reduction
0
FEOL Guardband Reduction Goal: Entry-by-Entry BC-WC Guardband Reduction
1 2 3 4
1 1 1 1 1
2 2 2 2 2
3 3 3 3 3
4 4 4 4 4
1 2 3 4
2 4 4 4 4
4 6 6 6 6
6 8 8 8 8
5 10 10 10 10
1 2 3 4
2 2 2 2 2
3 3 3 3 3
4 4 4 4 4
5 5 5 5 5
1 2 3 4
2 2.1 2.1 2.1 2.1
3 3.15 3.15 3.15 3.15
4 4.2 4.2 4.2 4.2
5 5.25 5.25 5.25 5.25
1 2 3 4
2 3.9 3.9 3.9 3.9
3 5.85 5.85 5.85 5.85
4 7.8 7.8 7.8 7.8
5 9.75 9.75 9.75 9.75
Original Best Original Worst
Index Matched Best
New Best New Worst
Inter/extra-polation w/ worst indices
Move toward worst value
Move towardbest value
Input: index-matched best/worst-case libraries and x% guardband reduction
Output: guardband reduced best/worst-case libraries.
for all the cells in the best/worst-case libraries:
for each entry in a best-case table (valuebest ):
(valuebest=valuebest+ x/200 (valueworst-valuebest)
for each entry in a worst-case table (valueworst ):
(valueworst=valuebest- x/200 (valueworst-valuebest )
Input: best/worst-case libraries.
Output: index-matched best-case library.
for all the cells in the best-case library:
Find the corresponding cell in the worst case library.
interpolate/extrapolate the new best-case timing table entries using the best/worst-case values.
copy the slew rate index of the worst-case table on to that of the best-case table.
BEOL Guardband: SOCEncounter Resistance: worst case is 1.16X greater than best
Major parameter: Temperature Capacitance: worst case is 1.11X greater than best
Major parameter: Process
Capacitance ComparisonResistance Comparison
Worst= Best * 1.16
Worst= Best * 1.11
* Using OSTRICH from CADENCEBest (-40C, 1.1V)
Worst (125C, 0.9V)
Best (-40C, 1.1V)
Worst (125C, 0.9V)
BEOL Guardband: Star-RCXT Resistance: worst case is 1.17X greater than best
Major parameter: Temperature Capacitance: worst case is 1.13X greater than best
Major parameter: Process
Capacitance ComparisonResistance Comparison
Worst= Best * 1.17
Worst= Best * 1.13
* Using Star-RCXT from SYNOPSYSBest (-40C, 1.1V)
Worst (125C, 0.9V)
Best (-40C, 1.1V)
Worst (125C, 0.9V)
BEOL Guardband Reduction
Best STAR-RCXT BEST SOCE
Resistance 1 + (1.13 - 1)
(x / 200)
1 + (1.11 - 1)
(x / 200)
Capacitance 1 + (1.17 - 1)
(x / 200)
1 + (1.16 - 1) (x / 200)
Worst STAR-RCXT Worst SOCE
Resistance 1 - (1 - 1 / 1.13)
(x / 200)
1 + (1.11 - 1) (x/200)
Capacitance 1 - (1 – 1 / 1.17) (x / 200)
1 + (1.16 - 1)
(x / 200)
Outline
Motivations
Background
Model Guardband Reduction
Design Flow & Test Cases
Experimental Results
Discussion: Impact on Yield
Conclusion
Design Flow
Synthesis
Scan Insertion
Floorplan
Placement
Timing Optimization
CTS
Timing Optimization
Routing
Timing Optimization
Setup?
Signoff
Setup?
Setup
HoldNo
Yes
No
Yes
No
Yes
No
Yes
Cadence RTL Compiler
Synopsys DFT Compiler
Cadence SOC Encounter
Cadence SOC Encounter
Cadence SOC Encounter
Cadence SOC Encounter
Synopsys STAR-RCXT, PrimeTime
Cadence SOC Encounter
Cadence SOC Encounter
Testcases and Figures of Merit
Testcases
Metrics Quality of Results
Area, # Instances, Wirelength, etc.
Design Cycle Runtime, # violations, TNS, WNS, etc.
Category Items
Design Jpeg, Aes, 5xJpeg
Guardband Reduction 0%, 10%, 20%, 30%, 40%, 50%
Technology 90nm, 65nm
Timing Mode Function, Scan
Timing Check Worst/Best, Setup/Hold
Outline
Motivations
Background
Model Guardband Reduction
Design Flow & Test Cases
Experimental Results
Discussion: Impact on Yield
Conclusion
BEOL Guardband vs. FEOL Guardband (1)
FEOL Guardband is much larger than BEOL’s
FEOL: Worst Case Delay ~ 2 x Best Case Delay
BEOL: Worst Cap. ~ (1.11~1.13) x Best Cap.
Valuebest Valueworst
Example: 50% guardband reduction on FEOLWorst case delay will be reduced by about 25%
0
100% 200%
Valuebest Valueworst
Example: 50% guardband reduction on BEOLWorst case capacitance will be reduced by less than 2%
0100% 106%
Impact of Guardband Reduction
FEOL Reducing guardband
greatly affects the stage delay and the timing gap between best and worst
BEOL Reducing guardband would
not affect timing much
From these observations, we can conclude FEOL will have more impacts on design outcomes.
CaseGB
reductionTiming corner
Total path
delay (ns)
Average Stage delay (ns)
- 0%Worst 3.520 0.147
Best 1.435 0.060
FEOL
10%Worst 3.406 0.142
Best 1.525 0.064
40%Worst 3.069 0.128
Best 1.813 0.076
50%Worst 2.960 0.123
Best 1.910 0.080
BEOL
10%Worst 3.515 0.146
Best 1.437 0.060
40%Worst 3.502 0.146
Best 1.443 0.060
50%Worst 3.497 0.146
Best 1.445 0.060
FEOL+
BEOL
10%Worst 3.410 0.142
Best 1.523 0.063
40%Worst 3.085 0.129
Best 1.804 0.075
50%Worst 2.979 0.124
Best 1.899 0.079
Impact on Quality of Results (1): Area
40% of GB Reduction
AREA FEOL BEOLFEOL+BEOL
Average Reduction
13 % 2 % 13 %
Maximum Reduction
17 % 6 % 18 %
FEOL Only
70.0
75.0
80.0
85.0
90.0
95.0
100.0
105.0
110.0
0 10 20 30 40 50
Guardband reduction (%)
Norm
aliz
ed A
rea (
%) AES(90)
JPEG(90)
5XJPEG(90)
AES(65)
JPEG(65)
5XJPEG(65)
BEOL Only
70.0
75.0
80.0
85.0
90.0
95.0
100.0
105.0
110.0
0 10 20 30 40 50
Guardband reduction (%)
Nor
maliz
ed A
rea (
%) AES(90)
J PEG(90)
5XJ PEG(90)
AES(65)
J PEG(65)
5XJ PEG(65)
FEOL+BEOL
70.0
75.0
80.0
85.0
90.0
95.0
100.0
105.0
110.0
0 10 20 30 40 50
Guardband reduction (%)
Nor
maliz
ed A
rea (
%) AES(90)
J PEG(90)
5XJ PEG(90)
AES(65)
J PEG(65)
5XJ PEG(65)
FEOL only BEOL only
FEOL+BEOL
Impact on Quality of Results (2): Wirelength
40% of GB Reduction
Wirelength FEOL BEOLFEOL+BEOL
Average Reduction
12 % 2 % 12 %
Maximum Reduction
18 % 7 % 21 %
FEOL Only
70.0
75.0
80.0
85.0
90.0
95.0
100.0
105.0
110.0
0 10 20 30 40 50
Guardband reduction (%)
Nor
maliz
ed W
irel
engt
h (
%)
AES(90)
J PEG(90)
5XJ PEG(90)
AES(65)
J PEG(65)
5XJ PEG(65)
BEOL Only
70.0
75.0
80.0
85.0
90.0
95.0
100.0
105.0
110.0
0 10 20 30 40 50
Guardband reduction (%)
Nor
maliz
ed W
irel
engt
h (
%)
AES(90)
J PEG(90)
5XJ PEG(90)
AES(65)
J PEG(65)
5XJ PEG(65)
FEOL+BEOL
70.0
75.0
80.0
85.0
90.0
95.0
100.0
105.0
110.0
0 10 20 30 40 50
Guardband reduction (%)
Nor
maliz
ed W
irel
engt
h (
%)
AES(90)
J PEG(90)
5XJ PEG(90)
AES(65)
J PEG(65)
5XJ PEG(65)
FEOL only BEOL only
FEOL+BEOL
Impact on Design Cycle Time
Total design cycle time = f(runtime, iteration) Iteration depends on the timing
characteristics # Violations
How many paths designer should concern
Total negative slack (TNS) How much effort of timing optimization will be required
Worst negative slack (WNS) Feasibility of timing convergence
Impact on Design Cycle Time (1): Runtime
40% of GB Reduction
Runtime FEOL BEOLFEOL+BEOL
Average Reduction
28 % 2 % 28 %
Maximum Reduction
44 % 15 % 41 %
FEOL Only
40.0
50.0
60.0
70.0
80.0
90.0
100.0
110.0
120.0
0 10 20 30 40 50
Guardband reduction (%)
Nor
maliz
ed R
untim
e (
%)
AES(90)
J PEG(90)
5XJ PEG(90)
AES(65)
J PEG(65)
5XJ PEG(65)
BEOL Only
40.0
50.0
60.0
70.0
80.0
90.0
100.0
110.0
120.0
0 10 20 30 40 50
Guardband reduction (%)
Nor
maliz
ed
Runt
ime
(%)
AES(90)
J PEG(90)
5XJ PEG(90)
AES(65)
J PEG(65)
5XJ PEG(65)
FEOL+BEOL
40.0
50.0
60.0
70.0
80.0
90.0
100.0
110.0
120.0
0 10 20 30 40 50
Guardband reduction (%)
Nor
maliz
ed R
untim
e (
%)
AES(90)
J PEG(90)
5XJ PEG(90)
AES(65)
J PEG(65)
5XJ PEG(65)
FEOL only BEOL only
FEOL+BEOL
Impact on Design Cycle Time (2): Violations
40% of GB Reduction
Reduction of T.V.
FEOL BEOLFEOL+ BEOL
Setup Hold Setup Hold Setup Hold
# Violation 100%
91 %
6 % 0 %100 %
90%
WNS 100 %
77 %
10 %
-2 %100 %
76 %
TNS 100 %
99 %
22 %
0 %100 %
99 %
FEOL only
0
20
40
60
80
100
120
0% 10% 20% 30% 40% 50%
Guardband Reduction
Nor
mal
ized
Val
ue # Viols (Setup)WNS (Setup)TNS (Setup)# Viols (Hold)WNS (Hold)TNS (Hold)
FEOL+BEOL
0
20
40
60
80
100
120
0% 10% 20% 30% 40% 50%
Guardband Reduction
Nor
mal
ized
Val
ue # Viols (Setup)WNS (Setup)TNS (Setup)# Viols (Hold)WNS (Hold)TNS (Hold)
(90nm Jpeg case)
(90nm Jpeg case)
BEOL only
0
20
40
60
80
100
120
0% 10% 20% 30% 40% 50%
Guardband Reduction
Nor
mal
ized
Val
ue # Viols (Setup)WNS (Setup)TNS (Setup)# Viols (Hold)WNS (Hold)TNS (Hold)
(90nm Jpeg case)FEOL only (90nm jpeg) BEOL only (90nm jpeg)
FEOL+BEOL (90nm jpeg)
Outline
Motivations
Background
Model Guardband Reduction
Design Flow & Test Cases
Experimental Results
Discussion: Impact on Yield
Conclusion
Impact on Random Defect YieldOverall yield is defined by Random Defect Yield
Strong function of die area (A)
x
x
Ad
Ad
x
x
xProbxp
)1(
)(
)(!
)(
)chipon defects ofNumber ()(
Binomial Probabilistic Distribution Function
0xfor good die
)1( AdYr
factor clustering:
densitydenfect :
die a of Area :
d
A
sr YYY
Impact on Parametric YieldParametric Yield vs. Guardband
Ys can be estimated by considering normal distribution with
best case and worst case being set at -3σ and +3σ
For x% of guardband reduction, Ys is defined as,
For 0% guardband reduction: Ys=0.9973
For 40% guardband reduction: Ys=0.9281
2
)01.01(3
2
)01.01(3
2
1%)(
xerf
xerfxYs
about 7% yield loss
Impact on Yield: Scenario 1Scenario1: Parametric yield is constant
Adopting manufacturing-aware techniques (i.e., iso-dense timing analysis, better process equipments, etc.) foundries can reduce design guardband
40% guardband reduction results in 10% increase in total number of good dies
%RGBOriginaldie area (cm^2)
logic area
(cm^2)
% logic area
reduction
die area after RGB
(cm^2)
Ys(3 sigma)
Yr YGross
die/waferGood
die/wafer
0 0.850 0.480 1.000 0.850
0.997
0.844 0.841 759 639
10 0.850 0.480 0.936 0.819 0.849 0.847 789 668
20 0.850 0.480 0.912 0.808 0.851 0.849 801 680
30 0.850 0.480 0.895 0.800 0.852 0.850 809 688
40 0.850 0.480 0.869 0.787 0.854 0.852 823 701
50 0.850 0.480 0.850 0.778 0.856 0.854 833 711
A
r
A
rN gross
2
22
@ α=Inf., d=0.2/um^2, 300mm wafer
Impact on Yield: Scenario 2 Scenario 2: Guardband reduction in design
process (Actual guardband of fabrication is unchanged) Parametric yield will decrease Random defect yield will increase
20% guardband reduction results in 4% increase in total number of good dies per wafer
# of good dice per wafer vs. RGB
138
140
142
144
146
148
150
152
154
156
158
0 10 20 30 40 50 60
RGB (%)
# o
f g
oo
d d
ice
pe
r w
afe
r
no clustering
alpha=0.42
alpha=0.43
alpha=0.44
alpha=0.45
alpha=0.5
alpha=1
alpha=10
alpha=1000
Conclusions
We quantify impact of guardband reduction Typical outcome: 13%,12% and 28% reductions in
standard-cell area, total wirelength and SP&R runtime metrics from 40% reduction in library model guardband
100% reduction in number of timing violations for a netlist that is synthesized with original library and extraction guardbands this improvement can be very significant in improving timing closure and design cycle turnaround time
4% increase in the number of good dies per wafer by 20% artificial reduction from 3sigma guardband
Our results suggest that there is justification for the design, EDA and process communities to enable guardband reduction as an economic incentive for manufacturing-friendly design practices
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