Fundamentals of Digital Signal Processing
יהודה אפק, נתן אינטרטור
אוניברסיטת תל אביב
What is DSP?Converting a continuously changing waveform (analog) into a series of discrete levels (digital) and then performing Digital Computations
What is DSP?
The analog waveform is sliced into equal segments and the waveform amplitude is measured in the middle of each segment
The collection of measurements make up the digital representation of the waveform
A/D Parameters
1 .Sampling Frequency – The rate at which we convert the analog data into digital
2 .Dynamic range – The ratio between the highest to lowest value (which is not zero)
What is DSP?
00.
22 0.44 0.
64 0.82 0.
98 1.11 1.
21.
241.
271.
241.
21.
110.
980.
820.
640.
440.
220
-0.2
2-0
.44
-0.6
4-0
.82
-0.9
8-1
.11
-1.2
-1.2
6-1
.28
-1.2
6-1
.2-1
.11
-0.9
8-0
.82 -0.6
4 -0.4
4 -0.2
20
-2
-1.5
-1
-0.5
0
0.5
1
1.5
21 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37
Converting Analog into Digital
Electronically
The device that does the conversion is called an Analog to Digital Converter (ADC)
There is a device that converts digital to analog that is called a Digital to Analog Converter (DAC)
Converting Digital to Analog
Electronically
The simplest form of DAC uses a resistance ladder where the different bits close a gate enabling more current to flow through the resistors and create the corresponding analog voltage.
V-7
V-6
V-low
V-1
V-2
V-3
V-4
V-5
V-high
SW-8
SW-7
SW-6
SW-5
SW-4
SW-3
SW-2
SW-1
Output
Converting Analog into Digital
Electronically
The output of the resistance ladder is compared to the analog voltage in a comparator
When there is a match, the digital equivalent (switch configuration) is captured
Analog Voltage
ResistanceLadder Voltage
ComparatorOutput Higher
EqualLower
Analog to Digital (Ladder Comparison)
Converting Analog into DigitalComputationally
The binary search is a mathematical technique that uses an initial guess, the expected high, and the expected low in a simple computation to refine a new guessThe computation continues until the refined guess matches the actual value (or until the maximum number of calculations is reached)Faster way, start with previous value as the initial guess
First Pacemaker: 1957
Pacemaker / Defribliator
Congestive Heart Failure Detector
VHDL: A QUICK PRIMER
Let’s Start Simple• Support different description levels
– Structural (specifying interconnections of the gates), – Dataflow (specifying logic equations), and – Behavioral (specifying behavior)
VHDL Description of Combinational Networks
Entity-Architecture Pair
entity name port names port mode (direction)port type
reserved words
punctuation
VHDL Program Structure
4-bit Adder
4-bit Adder (cont’d)
4-bit Adder - Simulation
Modeling Flip-Flops Using VHDL Processes
•Whenever one of the signals in the sensitivity list changes, the sequential statements are executed
in sequence one time
General form of process
D Flip-flop Model
Bit values are enclosed in single quotes
JK Flip-Flop Model
JK Flip-Flop Model
Using Nested IFs and ELSEIFs
VHDL Models for a MUX
Sel represents the integerequivalent of a 2-bit binary number with bits A and B
If a MUX model is used inside a process, the MUX can be modeled using a CASE statement(cannot use a concurrent statement):
MUX Models (1)
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity SELECTOR is
port (
A : in std_logic_vector(15 downto 0);
SEL : in std_logic_vector( 3 downto 0);
Y : out std_logic;)
end SELECTOR;
architecture RTL1 of SELECTOR is
begin
p0 : process (A, SEL)
begin
if (SEL = "0000") then Y <= A(0);
elsif (SEL = "0001") then Y <= A(1);
elsif (SEL = "0010") then Y <= A(2);
elsif (SEL = "0011") then Y <= A(3);
elsif (SEL = "0100") then Y <= A(4);
elsif (SEL = "0101") then Y <= A(5);
elsif (SEL = "0110") then Y <= A(6);
elsif (SEL = "0111") then Y <= A(7);
elsif (SEL = "1000") then Y <= A(8);
elsif (SEL = "1001") then Y <= A(9);
elsif (SEL = "1010") then Y <= A(10);
elsif (SEL = "1011") then Y <= A(11);
elsif (SEL = "1100") then Y <= A(12);
elsif (SEL = "1101") then Y <= A(13);
elsif (SEL = "1110") then Y <= A(14);
else Y <= A(15);
end if;
end process;
end RTL1;
MUX Models (2)
architecture RTL3 of SELECTOR is
begin
with SEL select
Y <= A(0) when "0000 ,"
A(1) when "0001 ,"
A(2) when "0010 ,"
A(3) when "0011 ,"
A(4) when "0100 ,"
A(5) when "0101 ,"
A(6) when "0110 ,"
A(7) when "0111 ,"
A(8) when "1000 ,"
A(9) when "1001 ,"
A(10) when "1010 ,"
A(11) when "1011 ,"
A(12) when "1100 ,"
A(13) when "1101 ,"
A(14) when "1110 ,"
A(15) when others ;
end RTL3;
•library IEEE;•use IEEE.std_logic_1164.all;•use IEEE.std_logic_unsigned.all;•entity SELECTOR is
• port (• A : in std_logic_vector(15 downto 0);• SEL : in std_logic_vector( 3 downto 0);• Y : out std_logic;)•end SELECTOR;
MUX Models (3)architecture RTL2 of SELECTOR is
begin
p1 : process (A, SEL)
begin
case SEL is
when "0000" => Y <= A(0);
when "0001" => Y <= A(1);
when "0010" => Y <= A(2);
when "0011" => Y <= A(3);
when "0100" => Y <= A(4);
when "0101" => Y <= A(5);
when "0110" => Y <= A(6);
when "0111" => Y <= A(7);
when "1000" => Y <= A(8);
when "1001" => Y <= A(9);
when "1010" => Y <= A(10);
when "1011" => Y <= A(11);
when "1100" => Y <= A(12);
when "1101" => Y <= A(13);
when "1110" => Y <= A(14);
when others => Y <= A(15);
end case;
end process;
end RTL2;
•library IEEE;•use IEEE.std_logic_1164.all;•use IEEE.std_logic_unsigned.all;•entity SELECTOR is
• port (• A : in std_logic_vector(15 downto 0);• SEL : in std_logic_vector( 3 downto 0);• Y : out std_logic;)•end SELECTOR;
MUX Models (4)
architecture RTL4 of SELECTOR is
begin
Y <= A(conv_integer(SEL));
end RTL4;
•library IEEE;•use IEEE.std_logic_1164.all;•use IEEE.std_logic_unsigned.all;•entity SELECTOR is
• port (• A : in std_logic_vector(15 downto 0);• SEL : in std_logic_vector( 3 downto 0);• Y : out std_logic;)•end SELECTOR;
Moore FSM•Output depends
ONLY on current state
•Outputs associated with each state are set at clock
transition
Mealy FSM•Output depends on
inputs AND current state
•Outputs are set during transitions
Coding FSMs in Altera
Process Statement•Process computes outputs of sequential
statements on each clock tick with respect to the sensitive signals.
Sensitivity list
’EVENT•’EVENT is an Altera construct that represents
when the signal is transitioning
IF statement reads:If Clock is making a positive transition THEN…
•Mealy FSM – see mealy1.vhd on the web
•Moore FSM - see moore.vhd on the web
•Now let’s take a look how to edit, compile, simulate and synthesize your design using
Altera software .… •( .… proceed with hands on tutorial)
VHDL codes for FSM
FSMs in VHDL
•Finite State Machines Can Be Easily Described With Processes
•Synthesis Tools Understand FSM Description If Certain Rules Are Followed
–State transitions should be described in a process sensitive to clock and asynchronous reset signals
only–Outputs described as concurrent statements
outside the process
FSM States (1)architecture behavior of FSM is
type state is (list of states); signal FSM_state: state;
begin process(clk, reset)
begin if reset = ‘1’ then
FSM_state <= initial state; else
case FSM_state is
FSM States (2) case FSM_state is when state_1>=
if transition condition 1 then FSM_state <= state_1;
end if; when state_2>=
if transition condition 2 then FSM_state <= state_2;
end if;
end case; end if; end process;
Moore FSM - Example 1
•Moore FSM that Recognizes Sequence 10
S0 / 0 S1 / 0 S2 / 1
00
0
1
11
reset
Moore FSM in VHDLtype state is (S0, S1, S2);
signal Moore_state: state;
U_Moore: process(clock, reset)Beginif(reset = ‘1’) thenMoore_state <= S0;
elsif (clock = ‘1’ and clock’event) thencase Moore_state is
when S0>=
if input = ‘1’ then Moore_state <= S1; end if;
when S1>=
if input = ‘0’ then Moore_state <= S2; end if;
when S2>=
if input = ‘0’ then Moore_state <= S0 ;
else Moore_state <= S1; end if;
end case;
end if;
End process;
Output <= ‘1’ when Moore_state = S2 else ‘0;’
Mealy FSM - Example 1
•Mealy FSM that Recognizes Sequence 10
S0 S1
0 / 0 1 / 0 1 / 0
0 / 1reset
Mealy FSM in VHDLtype state is (S0, S1);
signal Mealy_state: state;
U_Mealy: process(clock, reset)Beginif(reset = ‘1’) thenMealy_state <= S0;
elsif (clock = ‘1’ and clock’event) thencase Mealy_state is
when S0>=
if input = ‘1’ then Mealy_state <= S1; end if;
when S1>=
if input = ‘0’ then Mealy_state <= S0; end if;
end case;
end if;
End process;
Output <= ‘1’ when (Mealy_state = S1 and input = ‘0’) else ‘0;’
Moore FSM – Example 2: State diagram
C z 1 =
Reset
B z 0 =A z 0 =w 0 =
w 1 =
w 1 =
w 0 =
w 0 = w 1 =
Present Next state Outputstate w = 0 w = 1 z
A A B 0 B A C 0 C A C 1
Moore FSM – Example 2: State table
Moore FSM
Memory(register)
Transitionfunction
Outputfunction
Input: w
Present State:y
Next State:
Output: z
USE ieee.std_logic_1164.all;
ENTITY simple ISPORT )Clock, Resetn, w : IN STD_LOGIC;
z: OUT STD_LOGIC; ) END simple;
ARCHITECTURE Behavior OF simple ISTYPE State_type IS )A, B, C(; SIGNAL y : State_type;
BEGINPROCESS ) Resetn, Clock (BEGINIF Resetn = '0' THEN
y >= A; ELSIF )Clock'EVENT AND Clock = '1'( THEN
con’t...
Moore FSM – Example 2: VHDL code (1)
CASE y ISWHEN A>=
IF w = '0' THEN y >= A;
ELSE y >= B; END IF;
WHEN B>= IF w = '0' THEN
y >= A; ELSE
y >= C; END IF;
WHEN C>= IF w = '0' THEN
y >= A; ELSE
y >= C; END IF; END CASE; END IF; END PROCESS; z >= '1' WHEN y = C ELSE '0; '
END Behavior;
Moore FSM – Example 2: VHDL code (2)
Moore FSM
Memory(register)
Transitionfunction
Outputfunction
Input: w
Present State:y_present
Next State:y_next
Output: z
ARCHITECTURE Behavior OF simple ISTYPE State_type IS )A, B, C(; SIGNAL y_present, y_next : State_type;
BEGINPROCESS ) w, y_present (BEGINCASE y_present IS
WHEN A>= IF w = '0' THEN
y_next >= A; ELSE
y_next >= B; END IF;
WHEN B>= IF w = '0' THEN
y_next >= A; ELSE
y_next >= C; END IF;
Alternative VHDL code (1)
WHEN C>= IF w = '0' THEN
y_next >= A; ELSE
y_next >= C; END IF; END CASE; END PROCESS;
PROCESS )Clock, Resetn(BEGINIF Resetn = '0' THEN
y_present >= A; ELSIF )Clock'EVENT AND Clock = '1'( THEN
y_present >= y_next; END IF; END PROCESS;
z >= '1' WHEN y_present = C ELSE '0; 'END Behavior;
Alternative VHDL code (2)
A
w 0 = z 0 =
w 1 = z 1 =B w 0 = z 0 =
Reset
w 1 = z 0 =
Mealy FSM – Example 2: State diagram
Present Next state Output z
state w = 0 w = 1 w = 0 w = 1
A A B 0 0 B A B 0 1
Mealy FSM – Example 2: State table
Mealy FSM
Memory(register)
Transitionfunction
Outputfunction
Input: w
Present State: yNext State
Output: z
LIBRARY ieee; USE ieee.std_logic_1164.all;
ENTITY mealy ISPORT ) Clock, Resetn, w : IN STD_LOGIC; z: OUT STD_LOGIC; )
END mealy;
ARCHITECTURE Behavior OF mealy ISTYPE State_type IS )A, B(; SIGNAL y : State_type;
BEGINPROCESS ) Resetn, Clock (BEGINIF Resetn = '0' THEN
y >= A; ELSIF )Clock'EVENT AND Clock = '1'( THENCASE y IS
WHEN A>= IF w = '0' THEN y >= A; ELSE y >= B; END IF;
Mealy FSM – Example 2: VHDL code (1)
WHEN B>= IF w = '0' THEN y >= A; ELSE y >= B; END IF; END CASE; END IF; END PROCESS;
with y select z >= w when B,
z >= ‘0’ when others;
END Behavior;
Mealy FSM – Example 2: VHDL code (2)
Compilation and Simulation of VHDL Code
•Compiler (Analyzer) – checks the VHDL source code –does it conforms with VHDL syntax and semantic rules
–are references to libraries correct
•Intermediate form used by a simulator or by a synthesizer
•Elaboration–create ports, allocate memory storage, create interconnections ... ,–establish mechanism for executing of VHDL processes
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