Texas A&M University 1 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
Jose Silva-MartinezJanuary 2019
FUNDAMENTALS OF ANALOG TO DIGITAL CONVERTERS: PART II
SAMPLE AND HOLD
Texas A&M University 2 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
ZOH vs. Track-and-Hold
• Zero acquisition time
• Infinite bandwidth
• Not realistic
• T/2 acquisition time
• Finite bandwidth
• Practical
Texas A&M University 3 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
Notice in the afore equation that the delay due to exp(-jfT) has being ignored
In practice, this term corresponds to a signal delay of T/2 seconds!
Texas A&M University 4 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
Clocking issues: Aperture errorLets consider a sinewave signal sampled with a S&H
Aperture error: reasons for this effect?
Texas A&M University 5 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
A0pk
0A0pkAin
0pk
Ain
tVErrorApertureMax
tcostVtvdt
dErrorAperture
tsinVsignalusoidalsinaofcaseIn
tvdt
dErrorAperture
Aperture error is proportional to signal slew-rate: Peak value times frequency
minsignal
ApkA0pk
Ain
TtV2tVAEMax
tvdtdErrorAperture
Aperture Error (Clock Jitter)
Texas A&M University 6 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
Clocking issues: Aperture errorObvious questions: What is the good, bad or ugly? Nature of tA?
i) Why this AE is relevant?ii) Is this a systematic error or a signal dependent
error?iii) What are the practical implications? More noise?
Distortion?iv) Can this error be eliminated?
Hint: Error is signal dependent in a non-linear fashion
tcostVtvdtdAE
tsinVcasetheFor
0A0pkAin
0pk
Texas A&M University 7 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
Clocking issues: Aperture errorDesigning for AE under the quantization error
1Nsignal
A
1N
signalS
pk
signalA
S
signal
ApkA0pk
2
1
T
tor
2
T
2
q
V2
Tt
thenlevelonquantizatihalf2
qAEMaxFor
T
tV2tVAEMax
minmin
min
),(
levelsonquantizatiofNumber36
1
T
t
signal
A
*.Rule of Thumb:
Texas A&M University 8 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
tcostfVAE
tcostfVtcostfVAE
tsinVcasetheFor
AFS
AFSApk
pk
0222
0222
0000
0
2
2signal
22s
21n22
220
22FS2
2A
20
22FS
2
2T
0
022
A20
22FS
2
T
tq2A
jittererrortimetheistt2
fVA
becomeserroramplitudesquaremeantheThen
2
1tfVsquaremeanAE
dtttfVsquaremeanAE0
)(
cos/
2
signal
21n22
2s2
22s2
T
t231
12
qtotalq
A12
qtotalq
Hence, the total (quantization+aperture) noise
2signal
21n22
reductionT
t23110SNR log*
The SNR degradation can then be computed as:
Clock Jitter issues: SNR degradation
Texas A&M University 9 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
2signal
21n22
reductionT
t23110SNR log*
signal
jitter
signal T
T
T
t
Clock Jitter issues: SNR degradation
Texas A&M University 10 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
S/H, T/H: Formal Math
Texas A&M University 11 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
Texas A&M University 12 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
Texas A&M University 13 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
o
S
S
i
• MOS technology is naturally suitable for implementing T/H.
• The lowpass SC network determines the tracking bandwidth of the T/H.
• “Top-plate” sampling leads to signal-dependent switch on-resistance.
Ron
0 VDDVi
VTnVTp
PMOS
NMOS
CMOS ithDDoxon VVV
LWCR 1
Texas A&M University 14 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
Tracking Bandwidth (TBW)
on
Si o
S Ron
0 VDDVi SonS CRR 1TBW
• Tracking bandwidth determines how promptly Vo can follow Vi.
• Typically TBW is many times greater than the max signal bandwidth.
• Notice that Ron is signal dependent, TBW is signal dependent too
• You should consider the worst case (Ron-maxima); remember Murphy’s Law!
Texas A&M University 15 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
Dispersion
djHdt
jHt
g
p
:delay Group
:delay Phase
• Magnitude response
• Non-uniform phase delay
• Non-uniform group delay
Texas A&M University 16 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
Dispersion
• Waveform distortion mainly due to non-uniform phase- and group-delay.
• Shape of waveform not very sensitive to the lowpass magnitude responseas long as the signal bandwidth is on the order of the TBW.
Ron
CSVi Vo
RS
Texas A&M University 17 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
Signal-Dependent Ron
o
S
S
i
• Fixed levels gate signal leads to signal-dependent switch on-resistance→ signal-dependent TBW → extra waveform distortion.
• Signal-dependent Ron and dispersion are both insignificant if TBW issufficiently large (>> fin, depending on the T/H accuracy).
Ron
0 VDDVi
VTnVTp
PMOS
NMOS
CMOS ithDDoxon VVV
LWCR 1
Texas A&M University 18 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
T/H: Practical issues
• Sufficient tracking bandwidth → negligible tracking error
• Well-defined sampling instant (asserted by clock rising/falling edge)
• Zero track- and hold-mode offset errors
Texas A&M University 19 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
• Finite tracking bandwidth → tracking error, T/H memory
• Track-mode offset (can be signal-dependent)
12
T/H: Practical issues
Texas A&M University 20 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
Acquisition Time (tacq)
on
Si o
S
SonS CRR TBW
1
Short L, thin tox, large W, large Vov, small Vi all help reduce Ron.
Accuracy tacq
0.5% (7b) ≥ 5
0.1% (10b) ≥
0.01% (13b) ≥
chithDDoxithDDox
on QL
VVVWLCL
VVVLWC
R
221
Texas A&M University 21 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
T/H Errors (T-to-H Transition)
• Pedestal error (often signal-dependent) resulted from switch turn-offnonidealities (clock feedthrough and charge injection).
• Aperture delay – the delay ∆t b/t the hold command and the hold action
• Aperture jitter – the random variation in ∆t (i.e., sampling clock jitter)
12
Texas A&M University 22 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
Sampling Switch CF and CI
Ф
VDD
0
Vin+Vth
Switch on Switch off
Clock feedthrough Charge injection
Fast turn-offSlow
turn-off
DDSgs
gs VCC
CV
Sgs
inthDDox
CCVVVWLCV
2
thinSgs
gs VVCC
CV
0V
Texas A&M University 23 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
T/H Pedestal Error
thDDSgs
oxDD
Sgs
gsi
Sgs
oxo
osio
VVCCWLCV
CCC
VCCWLCV
VVV
21
211
1
thSgs
gsi
Sgs
gso
osio
VCC
CV
CCC
V
VVV
1
1
Slow turn-off:
Fast turn-off:
Check these results!
Texas A&M University 24 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
T/H Speed-Accuracy Tradeoff
S
ch
CQV
21
Pedestal error:
TBW:S
ch
Son CLQ
CRTBW 2
1
221 22 L
QCL
CQ
TBWV
ch
S
S
ch
Therefore:
Technology scaling improves T/H performance!
Texas A&M University 25 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
Aperture Delay (∆t)
• Fixed aperture delay is usually not a problem in a single-channel T/H.
• Non-uniform aperture delay among interleaved T/H channels are thedominant sampling error source (∆t1, ∆t2… are also called samplingclock skew)
CH 1
CH 2
Φ1
Φ2
Vin
Φ1
Φ2
Texas A&M University 26 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
Aperture Jitter
Ref: M. Shinagawa, Y. Akazawa, and T. Wakimoto, "Jitter analysis of high-speedsampling systems," IEEE Journal of Solid-State Circuits, vol. 25, pp. 220-224,issue 1, 1990.
Texas A&M University 27 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
Aperture Jitter
22
1222
222
0
222 tT
i
AtAdttcosA
Ttt
tcosAttsinAtVt
onary"Cyclostati"
.ttcosAttsinA
tcostsintcosAtsintsinA
tsintcosAtcostsinA
ttsinAtVi
small for
222
21 2
22
2222 122 t
tAASNR
Texas A&M University 28 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
106
107
108
1090
20
40
60
80
100
120
140
Input Freq [Hz]
SNR
[dB
] t = 0.1ps t = 1ps t = 10ps t = 100ps
Aperture Jitter
tπfσLOGSNR 220 10
Texas A&M University 29 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
T/H Errors (Hold Mode)
• Hold-mode droop caused by off-switch/diode/gate leakage
• Hold-mode input feedthrough (i.e., due to capacitive coupling)
12
Texas A&M University 30 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
Evaluating T/H Performance
kT/C noise:
SNDR:
22
222
2
2 VtAV
VSNDRN
i
SSN C
kTdfRCfj
kTRV
0
22
2114
Noise Distortion
CS √kT/C
1pF 64μV
100pF 6.4μV
10fF 640μV
T = 300K
Jitter
Texas A&M University 31 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
Top-Plate Sampling
o
S
S
i
Pros• Simple, minimum number of devices• Wideband, zero track-mode offset
Cons• Signal-dependent tracking bandwidth• Signal-dependent charge injection and clock feedthrough• Signal-dependent aperture delay (sampling point)
Texas A&M University 32 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
CMOS Switch
• Ron of the NMOS and PMOS devices complement each other.
• Ron still depends on Vin and is sensitive to N/P matching.
• Large parasitic capacitance due to PMOS switch.
Ron
0 VDDVi
VTnVTp
PMOS
NMOS
CMOS
o
S
i
Texas A&M University 33 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
Clock Bootstrapping
• Constant gate overdrive voltage VGS = VDD for the switch.
• Ron to the first order does not depend on Vin.
• NMOS device only, less parasitic capacitance.
• Drawbacks:
• Charge pump is needed (Complexity)
• (Stress over the SiOx) Gate voltage will be VDD+Vin-max
Ron
0 VDDVi
1
DD
Texas A&M University 34 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
Clock Bootstrapping
Ref: A. M. Abo and P. R. Gray, "A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline ADC," IEEEJournal of Solid-State Circuits, vol. 34, pp. 599-606, issue 5, 1999.
Texas A&M University 35 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
Dummy Switch
• Initial size of dummy chosen with the assumption of a 50/50 splitof Qch; usually (W/L)dummy < ½(W/L)switch in practice.
• The nonlinear dependence of CI on Zi, CS, and clock slew rate makes it difficult to achieve a precise cancellation.
• Ф_ rising edge must trail Ф falling edge.
o
S
i
Texas A&M University 36 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
Balanced Switch + Dummy
o
S
i
S
Ref: L. A. Bienstman and H. J. De Man, "An eight-channel 8 bit microprocessorcompatible NMOS D/A converter with programmable scaling," IEEE Journalof Solid-State Circuits, vol. 15, pp. 1051-9, issue 6, 1980.
• TBW
• Parasitics
Texas A&M University 37 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
Signal-Dependent Aperture Delay
• Non-uniform sampling due to signal-dependent aperture delay causesdistortion.
• Large slew-rate (SR) of clock edge and small Vin mitigate the effect.
DD
i th i
th i
SRtVtAtV
tAtV
io
i
sin
,sin
Texas A&M University 38 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
Signal-to-Distortion Ratio
tASR
tASR
tAt
tASRVtVtVt i
oi
2sin21cossin
cos
2
.cossin
sincoscossin
sin
SRVtA
SRVtA
SRVtA
SRVtA
SRVtAtV
ii
ii
io
small for
22
2
22
2 22
22
ASRSR
AASDR
← 2nd-order
Texas A&M University 39 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
Fully-Differential T/H
• All even-order distortions are cancelled, including the signal-dependentaperture delay-induced distortion.
• Actual cancellation is limited by the P/N mismatch (1-5% typically).
fin 0.5GHzVDD 1.8V
tf 0.1nsA 0.5V
SDR (SE) 24.2dBSDR (DIFF) ?
o+
S+
i+
o-
S-
i-
1
2
Texas A&M University 40 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
Bottom-Plate Sampling
• Bottom-plate switch opens slightly earlier than the top-plate switches.• CF and CI of switch Φe are much less signal-dependent!• Bootstrapping the top-plate switch further helps.• For A/D converters of more than 8-bit resolution.• Less tracking bandwidth due to more switches in series.• Signal swing at node X is not completely zero!
Texas A&M University 41 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
Flip-Over (Flip-Around) SHA
Texas A&M University 42 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
Flip-Over (Flip-Around) SHA
• Non-inverting, 1X closed-loop gain
• Nonoverlapping two-phase clock with early sampling phase
• CF and CI to the 1st order independent of Vin and cancelled differentially
• Large open-loop gain of op-amp ensures the linearity of the SHA.
CMFB not shown
Texas A&M University 43 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
Inverting SHA
Closed-loop gain determined by the ratio CS/CH (mismatch?)
CMOS or bootstrapped
switches are required
when passing signals
with large swing
Ref: R. C. Yen and P. R. Gray, “A MOS switched-capacitor instrumentation amplifier,”IEEE Journal of Solid-State Circuits, vol. 17, pp. 1008-1013, issue 6, 1982.
Texas A&M University 44 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
Inverting SHA (Track-Mode)
• CF and CI to the 1st order independent of Vin and cancelled differentially
• Φ1e switch is equivalent to two switches of L/2 channel length.
Texas A&M University 45 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
Inverting SHA (Hold-Mode)
• For 1X gain, the feedback factor (β) is half that of the flip-over SHA.• Floating switch Φ2 in hold-mode → flexible input common mode• Useful for single-ended to differential conversion
Vo+
Vo-
CS+
Ф2CS
-
Ф2
Ф2
CH+
CH-
• CM
• DM
Texas A&M University 46 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
Equivalent Circuits (Hold-Mode)
• Floating switch Φ2 in hold-mode → flexible input common mode
• Useful for single-ended to differential conversion
DM CM
Texas A&M University 47 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
AZ Flip-Around SHA
• Bottom-plate sampling• Op-amp offset compensated by autozeroing• Stability in track-mode and fast settling in hold-mode
Vi+ Vo
+
Vo-Vi
-
CS+
Ф2CS
-
Ф2Ф1
Ф1
Ф1e
Ф1e
Vos
Texas A&M University 48 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
Closed-Loop SHA
• Closed loop system• Stability• Speed• Offset and noise due to Gm
• Effects of the clock feed-through? How the switch operates?
Voltage mode Current mode
Why C2 and M2?Advantages? Drawbacks?
Texas A&M University 49 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
Closed-Loop SHA
• A two-stage Miller-compensated op-amp → well-known design• CF and CI to the 1st order independent of Vin if A2 is large (VX≈0)• Vo always active and valid• Large slew-rate of A1 needed for fast tracking
Ref: K. R. Stafford et al., "A complete monolithic sample/hold amplifier," IEEE Journalof Solid-State Circuits, vol. 9, pp. 381-387, issue 6, 1974.
ViVo
CS
A2
Ф
A1
Ф
Texas A&M University 50 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
Open-Loop SHA
• Typically 1X buffer gain to widen the TBW• Can utilize either top-plate (faster) or bottom-plate sampling• Suitable for very high-speed, low-resolution S/H applications.
Top-plate sampling Bottom-plate sampling
Texas A&M University 51 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
Open-Loop SHA
Texas A&M University 52 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
Linearized amplifier
Texas A&M University 53 Spring, 2019
Fundamentals on ADCs: Part 2 Jose Silva-Martinez
Open-Loop SHA
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