Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A
SeyedNematollahAhmadian,SeyedGhassemMiremadi
BehavioralModelingandSimulation(BMAS)Conf.September2010
SharifUniversityofTechnologyDepartmentofComputerEngineering
DependableSystemLab[DSL]
1
Outline
Dependability MixedSignalFlow BehavioralFaultModeling FaultModels
SingleEventTransient/Upset(SET/SEU) PowerLineDisturbance(PLD) ElectroMagneticInterference(EMI)
Results
2
DependabilityandReliability
DependabilityandReliability Notjustwords!
Aneffectivetechniquefortheexperimentaldependabilityevaluation
Weproposeasimulation-basedfaultinjectionmethodinmixed-signalenvironment.
3
PreviousFaultInjectionTools
Levelofabstraction
HDL Circuit HDL CircuitDoes not include enough details For accurate modeling
Too slow, too old. cannot include verification method like
testbenches, etc.
solution:Mixed-signal fault injection
4
Flow
FaultinjectionandsimulationisperformedinMixed-Signalenvironment Performance/Accuracytradeoff
MoreaccuratethanRTLsimulationFasterthanSPICEsimulation
FaultinjectiononSoCswithanalogcoresPLLs,DLLs,SRAMs,…
5
Flow
SPICEsimulationnearthefaultsite: accuratefaultsimulation
HDLSimulation(elsewhere) Motive:Mostofthefaultmanifestthemselvesasanderror
outsidethefaultsite HDLsimulationprovidesenoughaccuracytocontinuesimulation.
Originaltestbenches/verificationscriptsareintact Fastersimulation.CancompensatefortheSPICEsimulation
penalty.
6
FaultModeling
Wedevelopfaultmodelsinbehavioralmodelinglanguages(suchasVerilog-A) Easymodeling Reducedevelopmenttime Accuratesimulations Accesstointernalnodes/structureoftransistor/electricalelement
7
Tool-chainarchitecture
Mixed-signalthree-levelofabstraction
FaultsareembeddedinsideVerilog-Amodel. ResultedfaultmodelsareinsertedtoCircuitasanexternalcomponent
Design Under Test Unit Under TestConverted to SPICE
Replaced device modelWith
Fault Injection
Unit under test
FaultyCell/
device
HDL level Circuit Level Gate Level
Verilog/VHDLModelSim 6.5 SE
SPICE netlistSynopsys hsim
Verilog-A modelSynopsys hsim
8
Faultmodels
Behavioralfaultmodeling SingleEventTransients/Upset(SET/SEU) Electro-MagneticInterference(EMI) PowerLineDisturbance(PLD)
Ourflowsupportsotherfaultmodelsaswell.
9
SETFaultModeling
Cause:hittingahigh-powerparticleintotransistorsdiffusionarea.
Effect:transientcurrentspikeondiffusion,singleeventtransientandupset.
10
Electro-MagneticInterferenceModeling
EMorRFinducedinterference
ModeledasaContinues-waveRFIsuperimposedonspecificnodes. Input Clock …
11
PowerLineDisturbanceModeling
CommonPLDs: Powersupplynoise Overshoot,Undershoot
GroundBouncing
12
Flow:Initialization/Injection
13
Flow:Simulation/Evaluation
14
ExperimentalSetup
Weusedthefollowing3rdpartytoolsandIPs: HDLSimulator:ModelSim6.5SE SpiceSimulator:SynopsysHSIM2008.09 Process:TSMC0.25μm
Ourfaultcharacteristics: SET:Q=10pc,withTO=TB=10ns,Randominjection,Twoexponentialmodel
EMI:100MHzCWRFsignal,Vpeak=0.5V,100nspulseenvelope,Randominjection
PLD:100nsduration,Voltageshortage(from2.5Vto0V)onVDDline,Randominjection
15
ResultsofSystemFailures
Counter FSM ALU SRAM UART AVERAGE0
10
20
30
40
50
60
70
80
90
100
PLDEMISET
16
Thankyou!
Questions?
Thankyouforyourattention.
17
Top Related