© 2013 TSMC, Ltd
TSMC Property
EUV Lithography
The March toward HVM
Anthony Yen
9 September 2016
© 2013 TSMC, Ltd
TSMC Property
1
λ=11 nm, provided by
synchrotron radiation
Ring
Aperture
W/C Multilayer Coating Optics
Wafer
Si Stencil Mask
SR
Hiroo Kinoshita, “30 years have passed from the first experiment,”
International Symposium on EUVL, Maastricht, the Netherlands, 6 Oct. 2015
8X, ring-field
Schwarzschild optics;
exposure carried out by
scanning mask and wafer
1st EUV lithography setup and results, 1986
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2
Bell Lab’s setup and results, 1990
Pitch = 100 nm
J. E. Bjorkholm et al., JVST B 8, 1509, Nov/Dec 1990
0.7 mm Si
membrane;
0.5 mm Ge
absorber
20X
Schwazschild
NA = 0.08
Under the leadership of Rick Freeman and Bill Brinkman, based on initial investigations by
Silfvast and Wood, a Bell Lab team was assembled to work on EUVL in 1988
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3
Hawryluk et al., JVST B7, 1702, Nov/Dec 1989
Reflective EUV masks proposed and fabricated Lawrence Livermore National Laboratory, 1989
Kinoshita et al. also succeeded in fabricating ML masks in 1989, published in JVST B 7, 1648 (1989)
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4
Troy W. Barbee, Jr., Proc. SPIE 563, 2 (1985)
Critical component in EUVL: multilayer reflector technology
n = 1 – d; k = b
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5
EUV LLC Organizational Structure, mid-90s
from EUV LLC: An Historical Perspective, by Chuck Gwyn and Stefan Wurm
in EUV Lithography, edited by Vivek Bakshi, SPIE Press 2009
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6
Culmination of EUV LLC work – ETS, early 2000s
0.1 NA, 4 mirrors, 24x32.5 mm imaging field
from EUV LLC: An Historical Perspective, by Chuck Gwyn and Stefan Wurm
in EUV Lithography, edited by Vivek Bakshi, SPIE Press 2009
Schematic drawing Initial assembly
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7
13.5 nm wavelength was selected around 1999 – 2000
from EUV Source Requirements for EUVL, by K. Ota, Y. Watanabe, V. Banine, H. Franken
in EUV Sources for Lithography, edited by Vivek Bakshi, SPIE Press 2006
Xe Sn
Li
Reflectivity of an 11-mirror imaging system and spectra of Xe, Sn, Li
10 11 12 13 14 Wavelength (nm)
Refl
ecti
vit
y a
nd
Sp
ectr
a D
en
sit
y (
arb
. u
nit
s)
Mo/Si ML
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TSMC Property
8
ASML’s ADT in image qualification, Spring 2006
Hans Meiling et al., “First performance results of the ASML alpha demo tool,”
Proc. SPIE 6151, 615108 (2006)
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9
TSMC participation of imec’s EUV Program 10/2007
ADT Scanner
DPP Source
1st light: 4/2007
Tool accepted: 6/2008
Photos courtesy of imec
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TSMC Property
10
NXE3100 Arrives in Taiwan, 7/2011
One of several scanner shipments arriving in Taiwan
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TSMC Property
11
NXE3100 Installation Nearly Complete
Hsinchu, October 2011
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12
NXE3300: Installation Complete
Hsinchu, October 2013
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13
Mid-module of NXE3350 Arriving at TSMC
Hsinchu, January 2016
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14
Progress on EUV source power E
UV
Pow
er
(W)
Year
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15
210W w/ in-spec dose, on a development source
Slide courtesy of ASML
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16
Carl Zeiss Starlith 3300/3400 Optics
Slide courtesy of Carl Zeiss
Photo Source: Fraunhofer IOF
ML coated collector mirror
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17
Improvements in Sustaining EUV Power by maintaining collector mirror cleanliness
1st Round of
Improvements
2nd Round of
Improvements
3rd Round of
Improvements
4th Round of
Improvements
*estimated
77 Gp (-0.78%/Gp)
95 Gp (-0.43%/Gp)
35 Gp (-1.2%/Gp)
30 Gp
(-1.4%/Gp)
Collector usage (G-pulses)
*130Gp (-0.4%/Gp)
5th Round of
Improvements
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18
Daily EUV Wafer Exposure Trend
1/2016 8/2016
NXE3350 single tool
champion data
Day 1 Day 2 Day 3
1000
Wafe
rs p
er
Day
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0
100,000
200,000
300,000
400,000
500,000
600,000
20
14
05
20
14
10
20
14
15
20
14
20
20
14
25
20
14
30
20
14
35
20
14
40
20
14
45
20
14
50
20
15
03
20
15
08
20
15
13
20
15
18
20
15
23
20
15
28
20
15
33
20
15
38
20
15
43
20
15
48
20
15
53
20
16
05
20
16
10
20
16
15
20
16
20
20
16
25
20
16
30
To
tal n
um
be
r o
f w
afe
rs e
xp
osed
:
Week
> 545,000 wafers exposed on NXE:33x0B systems
by customers
Slide courtesy of ASML
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20
Can we keep the mask clean?
(a)
(b)
(c)
(d)
Inner pod
Inner pod
Outer pod
(a) Conductive layer
(b) Low thermal expansion material
(c) Mo/Si multilayer
(d) Absorber
Dual-Pod manufactured by Gudeng Precision Industrial Co.
(b)
(c)
(d)
EUV Mask (downward facing) and associated Dual-Pod
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21
Continual reduction of mask native defects
Resolution of inspection:23 nm SEVD
0 1 2 3 4 5 6 7 8 9 10 11 12 13
De
fec
ts p
er
Bla
nk
2014 2016 2015 2017
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22
TSMC EUV pellicle development
𝑀𝑒𝑚𝑏𝑟𝑎𝑛𝑒 𝑡ℎ𝑖𝑐𝑘𝑛𝑒𝑠𝑠 = 50𝑛𝑚 𝑇𝑟𝑎𝑛𝑠𝑚𝑖𝑠𝑠𝑖𝑜𝑛 = 85%
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23
Slide courtesy of JSR
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24
BF: 0nm 20nm 40nm 60nm -20nm -40nm -60nm
27.0 mJ/cm2
13.2 nm CD
4.6 nm LWR
NXE3300, Dip45x
26nm Pitch, 13nm L/S
DOF@10%EL: 140 nm
Non-CAR Resist: 13nm L/S @ 26 mJ/cm2 w/ Process Window
Slide courtesy of Inpria, in collaboration with imec
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25
EUV single exposure replaces immersion multiple patterning
2D Metal layer at 32nm pitch achieved with Quasar illumination
48nm pitch / 24nm CD
ArFi Triple Patterning
EUV Single Exposure
Dose: 20 mJ/cm2
Slide courtesy of ASML, in cooperation with imec
Quasar illumination
Pupil Fill ratio 20%
32nm pitch / 16nm CD
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26
Exposure tools and their approximate resolution limits
Exposure Tool
Type
DUV
(248)
DUV
(193)
DUV
(immersion)
EUV
(current)
EUV
(future)
Wavelength 248 nm 193 nm 193 nm 13.5 nm 13.5 nm
N.A. 0.93 0.93 1.35 0.33 0.55
Approx. Min.
Printable Pitch 160 nm 120 nm 80 nm 26 nm 16 nm
For lines and spaces; resolution is somewhat lower for hole-type
patterns
EUV options being explored to extend Moore’s law
Node N: 1st generation EUV single patterning
Node N+1: low-k1 EUV single patterning
Node N+2: EUV double patterning or high-NA EUV single patterning
Node N+3: high-NA, low-k1 EUV single patterning
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27
10/2003
ASML made
1st immersion scanner
the 1150i with NA = 0.75
11/2004
Immersion a tool
1250i
NA = 0.85
Nov 2004
TSMC made 1st
functioning 90nm
chip with 1150i
10/2005
1400i
NA = 0.93
6/2006
1700i
NA = 1.2
March 2002 1st immersion proposal
(Burn Lin, TSMC)
Wafer
Last Lens Element
Mirror Mirror
VacuumFilterPump
Tank CoverFluid
Inlet
Fluid Outlet
Fluid
Replenishing
Hole
Drain
Fluid
July 2006 1st 65nm
product yield
Immersion Lithography Development at TSMC
Dec 2004 1st 1250i moved
into TSMC
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28
2009 2010 2011 2012 2013 2008 2014 2015 2016
NXE3400
scanners
for 5-nm node
imec’s ADT passed
acceptance test
6/2008
NXE3100 installation
complete 10/2011 NXE3300 installation
complete 10/2013
ADT scanner, resists, masks, pellicles, integration, etc.
Resists, mask blanks, AIMS tool, etc.
Actinic mask blank inspector
Metal-1 layer 20-nm node
Exposed on ADT
2010
Metal-1 layer 10-nm node
2013
EUV Lithography Development at TSMC
Co-funding of EUV development
NXE3350
move-in 1/2016
Via layer 7-nm node
2015
Via layer 5-nm node
2016
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