EEG CIRCUIT DESIGN
ECE, UAEEG CIRCUIT DESIGN
Micro-Power EEG Acquisition SoC[10]Electrode circuit
EEG sensing
Interference
Instrumentation amplier block diagramAmplifier & Filter
Chopper stabilized LNA (a) core topology and (b) complete topology
Two-stage op-amp with embedded chopper-modulators used in CS-LNA
Equivalent circuit model for CS-LNA EEG recordings in manExamples of records and results of analysis made by Braintune (St. Petersbuurg) hardware/software. EEG Probe SystemHardware Block DiagramXFMRSumLo1AM ModAM ModLo2GainGainToPCDual ChannelLow Noise AmplifierBoardDual ChannelAM ModulatorBoardChan 1Chan 1DRLRef GndNyquist Theorem
The highest frequency which can be accurately represented is one-half of the sampling rate.The sampling rate here is below the Nyquist frequency, so the result of sampling is nothing like the input:aliasing.For practical purposes the sampling rate should be 10 higher than the highest frequency in the signal.
EEG is a difference in potential between two electrodes
If two electrodes are active, it is called bipolar recording.If one electrode is silent, it is called monopolar recording. The reference sites: ear lobe, mastoid, nose.Bipolar vs. monopolar recordingsMonopolar recording is used in research, because it enables the researcher to localize the event of interest.
Bipolar recording is used in BF, because it reduces shared artifacts. Electrodes should be placed on the sites with the strongest gradients of the potentials under training. EMG and eye blink artifacts in EEGThese types of artifacts can be detected by visual inspection. Eye blinks can be excluded from data analysis.EMG should be taken into account during spectral analysis.
EEG recorded at Cz
EEG is a mixture of waves at different frequencies and amplitudes. EEG recorded at T5
At each time interval several sine-waves at different frequencies may be present in the signal.Quality control of EEG recording1) EEG amplifies must be calibrated with daily checks2) acquisition parameters must be checked daily and keep the same3) the same procedures must be employed in all individuals4) all artifacts must be eliminated or taken into account prior to spectral analysis. EMG ArtifactEMG artifact starts as low as 12 Hz and ranges to 300 Hz. Most of the spectrum lies between 30-150 Hz. Sites F3, F4, T3, T4, P3, P4 can pick up EMG the massester and temporalis muscles. Posterior electrodes can pick up EMG from occipitalis, trapezius and supraspinal muscles. To avoid this type of artifact one can relax or position the head properly or change slightly the position of electrode. Fz, Cz, Pz can give a relatively pure EEG signal.EKG artifactECG artifacts occur from the electrodes that pick up activity from underlying pulsating blood vessels in the scalp.EKG artifact gets more prevalent with aging.
The noise from the standard AC electrical line current This noise can be diminished by the proper grounding of the equipment (both computer and amplifies).It could be also eliminated by a so called notch filter which selectively removes 50 (60 for the US) Hz activity from the signal.This noise could be attenuated by obtaining good contact of electrodes with the scalp. The electrode impedance less than 10 kOhms is desirable.
EEG recording in man
Eyes opened condition.Examples of different waves.Reviewing EEGEEG is characterized by:1) voltage2) frequency (is used for BF)3) spatial location (is used for BF)4) inter-hemispheric symmetries 5) reactivity (reaction to state change) 6) character of waveform occurrence (random, serial, continuous) 6) morphology of transient events
Reviewing EEG: voltageAmplitude is the voltage in microvolts measured from the peak of the wave to the trough of the wave. Varies from 10 mcV to 100 mcV with average around 20-50 mcV.
Reviewing EEG: frequencySpectrums reflect the amount of energy in a certain frequency range of EEG.Term monorhythmic means that a particular portion of EEG shows a rhythmic component in a singular frequency.Term polyrhythmic means that several rhythmic frequencies are present in EEG. The presence of large-amplitude delta-activity may indicate infarct or other lesion.Reviewing EEG: frequencySlow (0-4 Hz) and high (more 20 Hz) frequency bands of EEG may pick up artifacts, such as eye movements and muscle activity, and therefore should be evaluated with caution. Despite the use of artifact rejection algorithms, the failure to accurately distinguish true physiological rhythmicity from the artifacts is a serious shortcoming of current software systems and requires the expert assessment. Reviewing EEG: transient events A transient is an isolated form or feature that stands out from the background activity.It is called a spike if it has the duration less than 70 msec. It is called a sharp wave if it has the duration between 70 and 200 msec.The presence of large amplitude spikes and waves may indicate the presence of epilepsy. Maps of EEG spectrums in standards bands
Eyes opened condition.
EEG recording in man
Eyes closed condition.Enhancement of alpha waves.Maps of EEG spectrums
Eyes closed conditionEEG spectrums
Three conditions (EC, R, M) are compared to Eyes Opened condition.Two peaks (in theta and alpha band) with different scalp distribution are observed.Reading and math produce big (but different) changes in alpha band and small changes in theta and beta bands.Note that alpha activities are different for all four conditions both in distribution and frequency.EEG spectrums in individual bands
Regular theta - idling rhythmIrregular theta - working activityReading and math produce alpha rhythms that are different in frequency and location.EEG as a sequence of micro-states
EEG consists of series of short-lasting quasi-stationary epochs corresponding to what Lehmann et al. (1987) have called brain functional micro-states.EEG reflects the changes in the state of neuronal networks rather than specific aspects of information processing.Normal distribution
When many independent random factors act in an additive manner to create variability, data will follow a bell-shaped distribution called the Gaussian distribution. This distribution is also called a Normal distribution. Although no data follows that mathematical ideal, many kinds of data follow a distribution that is approximately Gaussian
Dysfunction as a deviation from normal distribution
If we measure some parameter in the population with some brain dysfunction, then this parameter must has a different, not Gaussian distribution.There are statistical tests that measure this difference.Bimodal distribution in ADHD?Clinicians who diagnose this disorder have been criticized for merely taking a percentage of the normal population who have the most evidence of inattention and continuous activity and labeling them as having a disease. In fact, it is unclear whether the signs of ADHD represent a bimodal distribution in the population or one end of a continuum of characteristics. This is not unique to ADHD as other medical diagnoses, such as essential hypertension and hyperlipidemia, are continuous in the general population, yet the utility of diagnosis and treatment have been proven. Nevertheless, related problems of diagnosis include differentiating this entity from other behavioral problems and determining the appropriate boundary between the normal population and those with ADHD. Life span normative EEG database (LNDB)There are at least four eyes-closed LNDB:1) E. Roy John et al. (1977)2) Frank Duffy et al. (1994)3) Robert Thatcher et al. (1987)4) Barry Sterman et al. (199?)
Three goals of LNDB1) to assess the neurological basis for the patients complains (the issue of organicity)2) to identify the weakness of electrophysiological organization of the brain (the issue of neurotherapy design)3) to evaluate the efficacy of treatment ( the issue of treatment evaluation)Thatcher, 1999Active and passive conditions for NDB1) Eyes opened and eyes closed conditions are often used in NDB, because of simplicity and relative uniformity of recording conditions.2) Active tasks depend of many uncontrolled factors, such as intensity of stimuli, the subjects involvement, the distance from stimuli, etc. There are no standards for active conditions.What is an EEG?EEG stands for electroencephalogramEEG signals are created by measuring the difference in electrical currents across neuron membranesElectrodes attached to the body pick up these signalsThere can be a only a few electrodes or many attached to the head
37EEG signalsMany naturally occurring signals in the human body effect EEG signalsFrequency Analysis helps to separate the different signals38
Types of EEG signalsEEG signals have been classified into 4 categories:Delta0.3 to 4 HzDreamless sleepTheta4 to 8 HzAssociated with thoughts which produce dreamsAlpha8 to 13 HzResult of unfocused thoughtsBetaabove 13 HzResult of interactions with environment
39Electrode placementElectrode placement can effect signals received40
Related ResearchCreating a Brain Computer Interface (BCI) has been a goal for researchers since computers were first introducedBCIs could help patients with motor disabilities use computers or mobility platformsWhat is necessary:AmplificationFilteringClassificationControl4141Related Research (cont.)Large programs researching BCIs:Wadsworth Center in AlbanyGraz University of Technology in AustriaProblems facing the programs:Data transfer rateEfficiencyDifferences between test subjectsLearning curve for new users424243Design Block Diagram
Adrian Smith, Daniel Shinn,Ken Grove,
Project ECE 4006 - Group N144Amplifier BoardBuilt in previous semesterBased on Thomas Colluras design, founder of BrainmasterTwo stage amplifier7805 voltage regulator power supplyCan use 9V battery or 6V-35V DC power supply45Amplifier Schematic
46Amplifier DesignStage 1
Gain of 50Common Mode Rejection RatioProvides noise reduction and signal centeringStage 2
Gain of 390Capacitors stabilize power supply47Amplifier Parts ListResistors:(1) 10K 1/4W 5%(2) 1K 1/4W 5%(3) 130K 1/4W 5%(2) 200K 1/4W 5%(2) 10M 1/4W 5%(2) 200K 1/4W 5%(1) 51K 1/4W 5%
Integrated Circuits:(3) OP-90 amplifiers(1) 620AN amplifier(1) LM7805C voltage regulator
Capacitors: (1) 0.47uF 400V polypropylene (P474J)(3) 0.1uF 400V polypropylene (P104J)(2) 0.001uF 400V polypropylene (P103J)(1) 10uF 6.3VDC Tantalum
Other:(1) Set of 3 conductor signal leads
48Analog-Digital ConverterCurrent board is a Keithley DAS-1701ST Installed in borrowed computerMust be moved but face PCI interface problemKeithley KPCI-1307 card is the proposed solution
49Keithley KPCI-1307100k samples/sec16 single ended or 8 differential inputsAutoZero capability filters out drift32 digital I/O3 clock/timerdrivers includedVHDL program or DriverLINX software optionsPrice : $68050VHDL ImplementationDownload code to Flex10k20 chip on Altera boardBoard receives signals from the KPCI-1307 and controls mechanical devices 5051DriverLINX ImplementationCreate DLLs for data acquisition and signal routingInterface can be programmed inCC++Visual BasicActive X
52Overview of Completed ObjectivesEEG AmplifierOrder partsAssembly TestingData Acquisition BoardOrder boardInstallation of boardInstallation of drivers and software
53EEG Amplifier (Parts)Resistors:(1) 10K 1/4W 5%(2) 1K 1/4W 5%(3) 130K 1/4W 5%(2) 200K 1/4W 5%(2) 10M 1/4W 5%(2) 200K 1/4W 5%(1) 51K 1/4W 5%Capacitors: (1) 0.47uF polypropylene (P474J) [$1.62](3) 0.1uF polypropylene (P104J) [$0.74](2) 0.001uF polypropylene (P103J) [$0.45](1) 10uF 6.3VDC Tantalum [$0.52]Integrated Circuits:(3) OP-90 amplifiers [$2.35] (DIP package was not available when placing orders so SOIC package was substituted with the use of an 8-pin SOIC to DIP adapter. Price reflects cost of DIP package, as this should be ordered in future semesters.)(1) 620AN amplifier [$5.92](1) LM7805C voltage regulator [$0.43]Other:(1) Set of 3 conductor signal leads [$14.40](3) Disposable electrodes for each testing session [$0.24](1) Pre-holed circuit board [$8.49] 54Data Acquisition Board - Installation
KPCI-3107 16 analog single-ended or 8 analog differential. 32 digital outputs PCI interfaceCAB-1284CC-2STP-3655KPCI-3107 (DriverLINX software)Real-time data acquisition (with test panels)Analog/Digital I/O programming uses C++, VB, and Active XReal-time Triggering via driver allows user to specify trigger voltage and action to take after device is triggered.
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Final Testing WaveformsAIO Test Panel with Sine Wave input to Channel AThe test panel allowed for verification that the acquisition board was functioning correctlyEyebrow and eye blinks were recorded and graphed using the A/D board.57Final Testing Waveforms
58
Board at End of Semester A/D Board Amplifier connected to A/D board with electrodes A/D board connected to Computer
59Ideas for Continuing the ProjectBuild a low-noise case for STP-36 break-out boards.Calibrate gain for the EEG Amp input signal into an analog differential input channel. Research and learn how to use programming knowledge into a DriverLINX program.Program driver for KPCI-3107 board to output needed digital signal.Block diagram of the system
EEG Signal Acquisition Module
Where to place the electrodes? The electrodes are placed according to the international standard 10-20 system. The electrode position of 16 channels placed as shown in Fig. of frontal area (F3 and F4), central area (C3, Cz and C4), parietal area(P3, Pz and P4) The grounding electrode and referencing electrode are placed at forehead and right ear lobe respectively.EEG signal are digitized at 1024 samples/sec, resolution 16bit/sample.Signal were analog bandpass filtered between 1.5 and 100 Hz.FPGA ArchitetureFPGA- Field-programmable gate-arrayDesigners ChoiceDigital designer has various optionsSSI (small scale integrated circuits) or MSI (medium scale integrated circuits) componentsDifficulties arises as design size increasesInterconnections grow with complexity resulting in a prolonged testing phaseSimple programmable logic devicesPALs (programmable array logic)PLAs (programmable logic array)Architecture not scalable; Power consumption and delays play an important role in extending the architecture to complex designsImplementation of larger designs leads to same difficulty as that of discrete componentsDesigners ChoiceQuest for high capacity; Two choices availableMPGA (Masked Programmable Logic Devices)Customized during fabricationLow volume expensiveProlonged time-to-market and high financial riskFPGA (Field Programmable Logic Devices)Customized by end userImplements multi-level logic functionFast time to market and low risk
FPGA A Quick LookTwo dimensional array of customizable logic block placed in an interconnect arrayLike PLDs programmable at users siteLike MPGAs, implements thousands of gates of logic in a single deviceEmploys logic and interconnect structure capable of implementing multi-level logicScalable in proportion with logic removing many of the size limitations of PLD derived two level architectureFPGAs offer the benefit of both MPGAs and PLDs!
FPGA A Detailed LookBased on the principle of functional completenessFPGA: Functionally complete elements (Logic Blocks) placed in an interconnect frameworkInterconnection framework comprises of wire segments and switches; Provide a means to interconnect logic blocksCircuits are partitioned to logic block size, mapped and routedA Fictitious FPGA Architecture(With Multiplexer As Functionally Complete Cell)Basic building block
Design Steps Involved in Designing With FPGAsUnderstand and define design requirementsDesign descriptionBehavioural simulation (Source code interpretation)SynthesisFunctional or Gate level simulationImplementationFittingPlace and RouteTiming or Post layout simulationProgramming, Test and Debug
Field ProgrammabilityField programmability is achieved through switches (Transistors controlled by memory elements or fuses)Switches control the following aspectsInterconnection among wire segmentsConfiguration of logic blocksDistributed memory elements controlling the switches and configuration of logic blocks are together called Configuration MemoryTechnology of Programmable ElementsVary from vendor to vendor. All share the common property: Configurable in one of the two positions ON or OFFCan be classified into three categories:SRAM basedFuse basedEPROM/EEPROM/Flash basedDesired properties:Minimum area consumptionLow on resistance; High off resistanceLow parasitic capacitance to the attached wireReliability in volume productionProduct FPGA vs ASICComparison:FPGA benefits vs ASICs:- Design time: 9 month design cycle vs 2-3 years- Cost: No $3-5 M upfront (NRE) design cost. No $100-500K mask-set cost- Volume: High initial ASIC cost recovered only in very high volume products
Due to Moores law, many ASIC market requirements now met by FPGAs- Eg. Virtex II Pro has 4 processors, 10 Mb memory, IO
Resulting Market Shift:Dramatic decline in number of ASIC design starts:- 11,000 in 97- 1,500 in 02
FPGAs as a % of Logic market:- Increase from 10 to 22% in past 3-4 years
FPGAs (or programmable logic) is the fastest growing segment of the semiconductor industry!!
71150nm / 200mm ASICsFPGA/ASIC Crossover Changes Production VolumeCost90nm / 300mm ASICs150nm / 200mm FPGAs90nm / 300mm FPGAsFPGA Cost AdvantageASIC Cost Advantage
FPGA Cost AdvantageASIC Cost Advantage
FPGA Cost Advantage 72This graph shows the impact of the rapid technology evolution (click)The significant saving in silicon cost helps closing the gap in unit cost between ASICs and FPGAs, moving the crossover towards higher volume (click)In addition, the starting cost for each generation of silicon technology skyrockets, which further moves out the crossover.Taxonomy of FPGAs
Development of a Low-Cost FPGA-Based SSVEP BCI Multimedia Control SystemIEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 4, NO. 2, APRIL 2010FPGA-Basedlow-cost eld-programmable gate-array (FPGA)-based braincomputer interface (BCI) multi-media control system
Low costSmall sizeFlexibleReal-time control
Use their brainwave to communicate with or control multimedia devices
Customized stimulation panela light-emitting diode stimulation panel instead of cathode ray tube or liquid-crystal display
stronger steady-state visual evoked potential (SSVEP)
SSVEP-based BCI multimedia control system Brainwave-acquisition circuitSSVEP acquisition
System Schema
Block diagram
Simulation panel
Implement and results
Implement and results
Implement and results
a Capacitively Coupled Sensor Readout Circuit [5]Contact-less
Capacitively coupled sensor
Without any need for gel
Electronic readout circuit
Circuit design
Circuit designCapacitive SensorInstrumentation AmplierNotch FiltersSecond Amplication StagePCB Layout
Circuit design
Design Of An Electronic Device for bci [4]Describes the single electronic stage for the conditioning of the analog acquired signal.
Circuit designPower supply Acquisition and signal conditioning Processing and transmission of digital data to PC. Circiut design
Input Guarding Configuration
EEG Machine ByThe All-American Boys Featuring Slo-Mo
Motaz AlturayefShawn ArniAdam BiermanJon OhmanGoals and PerspectiveGoals:Design an EEG (Electroencephalography) machine to promote the generation of user selected brainwave frequenciesAccesible Frequency ranges (Theta, Alpha, Beta) Using Audio and Video Feedback to synchronize brain
Block Diagram Description
Physiology and Input Design
Physiology of NeurofeedbackBrain waves divided into distinct frequency bands:Delta: 0-3 Hz, Associated with slow wave sleepTheta: 4-7 Hz, Associated with drowsiness or arousalAlpha: 8-13 Hz, Associated with relaxed concentration or contentmentBeta: 14-30 Hz, Associated with intense concentration, high levels of thought activity Physiology ContinuedSynchronization of Brain waves is possibleExternal stimuli used to synchronize brain wave frequenciesOur project will use both audio and video stimuli to synchronize wavesCan be used to train an individual to put themselves in desired stateElectrode Input DesignFive electrode two channel EEG headband for signal monitoringDesign compiled from multiple schematicsUsing active electrodesPowered either with lithium batteries or hard line to main boardSmall voltage values require ultra low noise devicesAmplification, Filtering, and A/DDone at main boardAmplifier strengthens microvolt signals to usable levelsSignal passes through low-pass and high pass filters to remove DC components and higher frequency noise and brain wavesPossibly sent through band-pass filters as wellDigitized using low noise A/D converterDesign AspectsLow signal levels require very low noise devicesBattery powering could introduce too much signal noise unless properly shieldedTwo channels sufficient to measure frequency contentDifferential voltage measurementsFifth electrode along scalp midline to create unbiased groundRisksToo much noise in systemWill distort signal and render it uselessCan use commercial electrodes, conductive pasteFilters should assist in removing noise, also use shielding techniques for battery and twisted pairs for wiresTwo channels insufficient for measurementPossible to build more channelsFilters drop off too shallowly to isolate bandsOnly a problem if band-pass filtering is employed (Additional Feature)Flash Memory and System Outputs
Physiological Effects of OutputsAlter brain frequency through external stimulusAuditory stimulus is most effectiveProduce a stimulating frequency equal to that of the desired brain frequency stateBinaural beats: Auditory processing artifacts, the perception of which arises in the brain independent of physical stimuliVisual stimulus is another common optionA screen or monitor flashes an image at the rate of the desired brain frequency stateMemory OptionsTwo typesRAM (Volitile)ROM (Non-Volitile)SD Card FlashEasy to loadBoard Mounted Flash More permanentSpansion Memory8 MBIT Storage3.0V SupplyNo Bus ContentionMemory controller in Altera FPGAController allows access to program and read data from memoryController will also transfer data to audio/video controller for outputOutput Flow
RisksNot enough room in Flash for both audio and video signalsCan revert to SD Card where more space is availableHigh risk of epileptic seizures with a flashing monitorWarning must be presentedAuditory signal can be used exclusively
PC : (Matlab or LabView)Analyze the brainwave for frequency content and find the dominant frequency.Two Approaches of doing this: Signal as a whole and do Power Spectral Density (PSD) analysis.Divide the signal into 4 frequency bands then do PSD.RisksNot being able to debug the code with real brainwave signals.Synchronising the PC output with the whole system.
Processor Flow Diagram
Store User Input in memorySample Analog Input Nyquist: 100 Hz but fasterConvert A2DStore Digital Input (DI) in memoryMemory size 5 seconds at 500 Hz sampling rate with sample size 32 bits -> approx 80kbPull DI from memory Send DI to PCReceive Dominant Frequency (DF) from PCStore DF in memoryCompare User Input to DFAcquire memory address for Audio and Visual effectsOutput Audio address to Audio controllerOutput Video address to Video controllerRestart process & WAIT timeIt takes minutes to affect brainwave change so will rerun every minute
108Altera DE2 Development Board I/O needs Readily available32-bit Nios II embedded processor & SOPC Builder configuration & integrationQuartus II - Scalable environment
DE2 RisksRisksToo much reliance on built-in featuresInput data usable? (ADC conversion)Potential usage of development boards many options may spread team too thin
Alternate choice MSP430
Processor TestingInput SignalsUser Input on LEDsVerify Electrode/ADC sample and store, as audio outputCheck DF result and store using 7-segment displays/LEDsShow difference between UI and DF on LED/7 segment
Processor TestingOutput SignalStored Electrode/ADC signal to PC, output as audio on PC
Wait StateBetween samples illuminate LED
Budget
114Topics[9]Exp. design and ERPsSPM for EEG-MEG2D interpolation1st level analysis2nd level analysisTime as another dimensionTime-frequency analysisConclusion
114115Popular approaches to M/EEG Data
Event-Related Potentials (ERP) & Event-Related Fields (ERF)
ERP/F Quantification ApproachesPeaks, latency, area-under-curve
Spectral Analysis (a.k.a. time-frequency)
Connectivity115116What is the ERP/ERF?
Def: the average (across trials/subjects) potential/field at the scalp relative to some specific event in time
Stimulus/EventOnset116117What is the ERP/ERF?
Def: the average (across trials/subjects) potential at the scalp relative to some specific event in time
Averaging117118What is the ERP/ERF?
Def: the average (across trials/subjects) potential at the scalp relative to some specific event in time
Reflects reliable changes in potential that are strongly time-locked to stimulus onset (i.e. are synchronous over trials)Non-time-locked activity is lost to averaging118119Interpreting ERP/ERF Waveforms
sensorERP/ERF waveforms are often interpreted in terms of their constituent components
Component (def) - Scalp-recorded electrical activity that is generated by a given patch of cortex engaged in a specific computational operation+++---+++---119A Real-Time Wireless BrainComputer Interface System for Drowsiness DetectionChin-Teng LinChe-Jui ChangShao-Hang HungChih-Feng Chao
IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 4, NO. 4, AUGUST 2010ApplicationDrowsy level detection
Safe car driving to alert tired drivers
real-time drowsiness monitoring can prevent trafc accidents effectivelySystem
Convenience wearable
Circuit designA preamplier, A band-pass lterAn analog-to-digital converter (ADC)Designed to amplify and lter the EEG signal
The gain of the EEG amplier and acquisition unit was set to about 5040 times with the frequency band of 0.1100 Hz. Procedure of EEG preprocessing
Design of a Compact Amplifier [11]DESIGN CONSIDERATIONSA. Effects of InterferenceB. Amplifier requirements
System design
System designA. Amplifier designB. Filter StagesC. Driven right leg circuitD. Power Supply designE. Construction of the system
Design on Sampling Circuit [12]A sampling circuit of EEG signal based on AT89C2051 single-chip is designed
signal condition, signal acquisitionserial communication interface
BASIC CHARACTERISTICS OF EEG
SAMPLING CIRCUITA. Signal Condition
Circuit
Ciucuit
Performances1) Amplifier gain is variable with 5000, 10000, 20000, or 30000.
2) Common mode rejection ratio is 102dB.
3) Pass-band frequency is with 0.12Hz-35.4Hz.
4) Input impedance is 113M.
References[1] http://en.wikipedia.org/wiki/EEG[2] Design of a Compact Amplifier and Signal Conditioning Module for Wireless EEG Monitoring, Ashwin K. Whitchurch Member, IEEE, Jose K. Abraham[3] Novel Hydrogel-Based Preparation-Free EEG Electrode, Nicolas Alexander Alba, Robert J. Sclabassi, Mingui Sun, IEEE TRANSACTIONS ON NEURAL SYSTEMS AND REHABILITATION ENGINEERING, VOL. 18, NO. 4, AUGUST 2010 [4] Design Of An Electronic Device For Brain Computer Interface Applications, . Palumbo,P. Vizza,P. Veltri, MeMeA 2009 - International Workshop on Medical Measurements and Applications [5] Design and Evaluation of a Capacitively Coupled Sensor Readout Circuit, toward Contact-less ECG and EEG, Daniel Sard, Andrzej Cichockiand Atila Alvandpour, 2010 IEEE[6] Design of Portable Multi-Channel EEG Signal Acquisition System , Lin ZHU, Haifeng CHEN, Xu ZHANG, IEEE
References[7] Design and Implementation of a Wireless Multi-Channel EEG Recording, R. Dilmaghani, M. Ghavami, K. Cumar, A Dualeh, S. Gomes Da Sousa, R. Salleh Mohd, CSNDSP 2010 [8] Development of a Low-Cost FPGA-Based SSVEP BCI Multimedia Control System, Kuo-Kai Shyu, Member, IEEE, Po-Lei Lee, Ming-Huan Lee, Student Member, IEEE, IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 4, NO. 2, APRIL 2010[9] Joseph Brooks (ICN)Maria Joao (FIL) Methods for Dummies 2007Wellcome Department For Neuroimaging[10] A Micro-Power EEG Acquisition SoC With Integrated Feature Extraction Processor for a Chronic Seizure Detection System, Naveen Verma, Ali Shoeb, Jose Bohorquez, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 4, APRIL 2010[11]Design of a Compact Amplifier and Signal Conditioning Module for Wireless EEG Monitoring, Ashwin K. Whitchurch (a), Member, IEEE, Jose K.Abraham (a), Senior Member, IEEE, Meghana A. Lonkar , 2007 IEEE Region 5 Technical Conference, April 20-21, Fayetteville, AR[12]Design on Sampling Circuit of EEG Signal Based on AT89C2051 Single-chip, Xiao-dong Zhang,Zhen-hai Zhang, 2009 Fourth International Conference on Innovative Computing, Information and Control
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Two Eyebrow Raises
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Two Eyebrow Raises
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Two Jaw Clinches
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Two Blinks
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Two Blinks
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Two Eyebrow Raises
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Two Jaw Clinches
PreprocessingFeature Extraction by FD (CEM)Classification (Detection)Signal AcquisitionApplication InterfaceBrain Computer InterfaceSignal Processing Feedback
GNDNASIONGND
REF
T6T5P3 PZP4T4T3C3CZ C4FZF3F4F8F7 FP1 FP2O2O1CPU
PC/FOURIER
WAVEFORM MONITOR
RAM
FLASH
AUDIO/VIDEOOUTPUTS
USER INPUTS
ELECTRODEINPUTS
Electrode Input 1
Electrode Input 2
Low-PassFilter
High-PassFilter
Preamplifier
Amplifier
Preamplifier
Amplifier
Low-PassFilter
High-PassFilter
Summer/Averager
A/DConverter
Processor
Sheet1PCBs (3)100DAQ150Electrode Tips & Wires50Serial Cable10Serial Port & Controller20A2D Port & Controller25Onboard Memory10Audio Port, Controller & Headphones70Video Port, Controller & Monitor300SD Card, Card Slot & Controller80FPGA100USB Blaster Controller40Power20Misc50Total$1,025
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