Dr.-Ing. Xu Jiang„Protection Schemes for Modular Multilevel Converter

Based High Voltage Direct Current Transmission System Converters “

Promotionsprüfung am 28.11.2018

Motivation

First blocking of FBSM Protection schemes based on new MMC converters

The development of suitable high‐voltage DC (HVCD) breakers is an important element in thedesign of HVDC transmission systems as fault protection in DC systems is more complicated thanin AC systems. The lack of zero crossing between DC voltage and current is a serious challenge,making it more difficult to realize insulation and arc extinguishment than in AC systems.Traditional mechanical circuit breakers have long switching times (tens of milliseconds) thatmake it difficult to meet the protection requirement of a DC system.

In recent years, several new HVDC breakers and relevant protection schemes have beenproposed. These topologies and protection schemes have a variety of advantages anddisadvantages. This dissertation compares different fault current protection schemes with regardto power loss, switching time, the number of semiconductor elements and so on; proposes anew protection scheme; and discusses the overvoltage protection scheme of insulated‐gatebipolar transistors (IGBTs) in multilevel modular converters (MMCs; called random first blocking),With this method, there are many possible fault‐current slopes after the first blocking. Thethreshold current can be determined using this method.

Protection schemes independent of HVDC converters

HVDC systems and their protection

Thyristor converters are widely employed as rectifiers in linear constant current (LCC)–based drives to provide anadjustable DC current. A thyristor converter can work in either rectifying or inverting mode. When the fault occurs inLCC HVDC, the thyristors are all blocked. Thyristors can be turned off at the zero crossing point of current.

For two‐level and three‐level VSCs, large capacitors are installed at the DC side. They smoothen the DC voltage andmake sure that the DC side reacts like a voltage source. However, when the DC fault occurs, due to the discharging ofthe DC link capacitors, substantial overcurrent is generated due to the rapid decrease in DC voltage. On the other hand,when the fault is detected, fully controllable switches are all blocked. However, the anti‐paralleled diodes act as anuncontrolled rectifier, which cannot block the fault current.

For modular multilevel converter (MMC), because of its modularized structure, it is easy to realize hundreds voltagelevels to approximate AC voltage and the THD can be reduced to a great extent. Hence, only small filters are needed ormay even be omitted. However, the MMC with half‐bridge cannot block the current path during the DC fault, becausethe diodes act as an uncontrolled rectifier. In order to realize the protection of HVDC system, different protectionschemes are proposed.

All‐solid HVDC breaker

short switching time, the over‐current can be limited very fast

the conduction loss of semiconductor devices is very large

Resonant HVDC breaker

during normal operation, the resonant HVDC breaker has no extra loss

there is always plasma between the contact of the mechanical switch

Hybrid HVDC breaker

low power loss during normal operation, the switching time is limited within several milliseconds

the over‐current is sometimes too large, and the IGBTs in the main switch must be designed specifically

Protection schemes based on classical MMC converters

Full bridge sub‐module Clamp‐double sub‐module(CDSM)

Five‐level cross‐connected cell type(FLCC)

C1

C2

S1

S2

S3

S4

S5 S6

Uc

Uc

Four‐level MMC cell type(FLCT)

Hybrid MMC

Full‐bridge (FB) MMCs are the firstmodified MMCs to block the faultcurrent. However, the hardware cost ofFB‐MMCs is twice that of HB‐MMCs,and the loss power of FB‐MMCs islarger than HB‐MMCs’ as well. In orderto block the fault current and solve theproblem of high hardware costs andloss power, clamp‐double (CD) MMCshave been developed. However, CD‐MMCs cannot work under over‐modulation. In order to realize faultride‐through capability, lowerhardware costs and loss power, andovermodulation, other kinds of MMCshave been invented, including a five‐level cross‐connected cell type and afour‐level MMC cell type; hybrid MMCsare also typical.

Due to the stray inductance in thecircuit (Fig. (b)), if all IGBTs areblocked simultaneously in each FBSMafter the fault, IGBTs will withstandovervoltage (Fig. (c)). In order toreduce the stress of IGBTs, therandom first blocking of the right andleft sides is used. As illustrated in Fig.(d), if the right side is blocked first,the current will flow through IGBT1and IGBT3 first. The second blockingwill occur shortly thereafter. In thisway, the stress of the IGBTs can bereduced.If the first blocking is random, theoutput voltages of FBSM after thefirst blocking may also be random.There are thus many possible outputvoltages in each arm after the firstblocking.

Because the fault current slope is the function ofoutput voltage in each arm, there are a large numberof possible fault current slopes after the first blocking.The maximum possible fault current can be calculated.

For different cases, the possible maximum faultcurrents can be calculated. In order to attain a suitablethreshold current, the iterative method is used. If themaximum turn‐off current of the IGBTs is 3500 A, thethreshold current is determined to be 3067 A.

Conclusion

t1: Short‐circuit fault occurs.t2: IGBTs in MMCs are blocked; thyristors are turned on.t3: IGBTs in the main switch are blocked.t4: Fault current in UFD decays to 0; UFD is turned off.

The duration of the AC side short circuit may be limited. However, in extreme cases, the long decay time of the DC fault current may affect the restart of the HVDC system. 

One‐arrestor version for double‐thyristor‐switch MMC sub‐module

Two‐arrestor version for double‐thyristor‐switch MMC sub‐module

UDC

LArm

LArm

iL,1

IDC,I

iL,2

iL,3

iArm,1P iArm,2P iArm,3P

iArm,1N iArm,2N iArm,3N

LArmLArm

LArmLArm

Converterphase

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

Con

vert

erar

m

UCim

1

2P1

P2

M

M

M

IGBT1s

Ultra Fast Diconnector

(UFD)

Arrestor1

AC-Net

DC line

Diodes

Arrestor2

Fre

ewhe

elin

g di

odes

for

D

C s

hort

cir

cuit

IDC,II

ID

IGB

T2s

t1: Short‐circuit fault occurs.t2: IGBTs in MMC are blocked; thyristors are turned on.t3: IGBTs in main switch are blocked.t4: Fault current in UFD decays to 0; UFD is turned off.t5: IGBT2s in diodes branch are turned off.

If all IGBT2s are turned off, the fault current will commutate to Arrestor2 and decay rapidly.

Simulation results of one‐arrestor version Simulation results of two‐arrestor version

According to the simulation results, when the fault location increases, the fault current decay time alsoincreases. Compared with the one‐arrestor version, the two‐arrestor version has a shorter fault current decaytime.

1. Different HVDC breakers have different advantages and disadvantages. The design of HVDC breakers is a trade‐off between switching time, loss power and so on.

2. The fault ride‐through capability of MMCs leads to large power loss and high hardware costs. MMCs, which can work under overmodulation state, have even greater loss and cost.

3. All MMCs with fault ride‐through capability can use the first blocking method to reduce the stress of semiconductor devices. A suitable threshold current can limit the maximum fault current and ensure antidisturbance ability.

4. The new MMC protection scheme combines MMC topology and HVDC breakers, giving it the advantages of these protection schemes.