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Page 1: Design and Implementation of VLSI Systems (EN1600) lecture09

S. Reda VLSI Design

Design and Implementation of VLSI Systems(EN1600)lecture09

Prof. Sherief RedaDivision of Engineering, Brown University

Spring 2008

[sources: Weste/Addison Wesley – Rabaey/Pearson]

Page 2: Design and Implementation of VLSI Systems (EN1600) lecture09

S. Reda VLSI Design

Summary of transistor operation

NMOS transistor PMOS transistor

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S. Reda VLSI Design

DC transfer characteristics

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S. Reda VLSI Design

PMOS on (linear), NMOS off

Vin0

Vin0

Idsn, |Idsp|

VoutVDD

• Vin = 0

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S. Reda VLSI Design

PMOS on (linear), NMOS on (saturation)

Vin1

Vin1Idsn, |Idsp|

VoutVDD

• Vin = 0.2VDD

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S. Reda VLSI Design

PMOS on (linear ~ sat) and NMOS (sat)

Vin2

Vin2

Idsn, |Idsp|

VoutVDD

• Vin = 0.4VDD

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S. Reda VLSI Design

PMOS on (sat) NMOS on (linear)

Vin3

Vin3

Idsn, |Idsp|

VoutVDD

• Vin = 0.6VDD

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S. Reda VLSI Design

PMOS on (off ~ linear) and NMOS on (linear)

Vin4

Vin4

Idsn, |Idsp|

VoutVDD

• Vin = 0.8VDD

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S. Reda VLSI Design

NMOS on (linear) and PMOS cut off

Vin5Vin0

Vin1

Vin2

Vin3Vin4

Idsn, |Idsp|

VoutVDD

• Vin = VDD

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S. Reda VLSI Design

Summary of voltage transfer function

AB

C

ED

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S. Reda VLSI Design

Noise margins

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S. Reda VLSI Design

CMOS inverter noise margins

desired regionsof operation

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S. Reda VLSI Design

What is the impact of altering the PMOS width in comparison to the NMOS width on the DC char?

Vin3

Idsn, |Idsp|

VoutVDD

Vin3

Vin3

n+ n+

p-type body

W

L

tox

SiO2 gate oxide(good insulator, ox = 3.9)

polysilicongate

Vin3

If we increase (decrease) the width of PMOS compared to NMOS for the same input voltage, a higher (lower) output voltage is obtained

Vin

Vout

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S. Reda VLSI Design

Impact of skewing transistor sizes on inverter noise margins

Increasing (decreasing) PMOS width to NMOS width increases (decreases) the low noise margin and decreases (increases) the high noise margin

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S. Reda VLSI Design

Pass transistor DC characteristics

As the source can rise to within a threshold voltage of the gate, the output of several transistors in series is no more degraded than that of a single transistor

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S. Reda VLSI Design

Summary

Ideal transistor characteristicsNon-ideal transistor characteristics Inverter DC transfer characteristics Simulation with SPICE and integration with L-Edit