Cyclic Combinational Circuits:Cyclic Combinational Circuits:Analysis for Synthesis Analysis for Synthesis
Marc D. Riedel and Jehoshua Bruck
California Institute of Technology
Combinational Circuits
The outputs depend only on the present values of inputs.
time tinputs
1x
2x
mx
CombinationalCircuit
),,( 11 mxxf ),,( 12 mxxf
),,( 1 mn xxf
time (t+Δt)outputs
}1,0{}1,0{:, mjfj}1,0{, ixi
Generally acyclic (i.e., feed-forward) structures.
Combinational Circuits
0
1
0
1
0
1
1
1
1
0
0
1
1
1
0
1
0
0
Circuits With Cycles
01 1
? ? ?
0: non-controlling for OR1: non-controlling for AND
May depend on timing.May have unstable/unknown outputs.
Cyclic Combinational Circuits
Cyclic circuits can be combinational.
Example due to Rivest (1977):
a b c a b c
f1 f2 f3 f4 f5 f6
Cyclic Combinational Circuits
b c b c
f1 f2 f3 f4 f5 f6
1 1
Cyclic circuits can be combinational.
Example due to Rivest (1977):
Cyclic Combinational Circuits
b c b c
f1 f2 f3 f5 f6
1 1
1
Cyclic circuits can be combinational.
Example due to Rivest (1977):
Cyclic Combinational Circuits
b c b c
f1 f2 f3 f5 f6
a a
f4
Cyclic circuits can be combinational.
Example due to Rivest (1977):
Cyclic Combinational Circuits
b c b c
f1 f2 f3 f4 f5 f6
0 0
Cyclic circuits can be combinational.
Example due to Rivest (1977):
Cyclic Combinational Circuits
b c b c
f2 f3 f4 f5 f6
0 0
0
Cyclic circuits can be combinational.
Example due to Rivest (1977):
Cyclic Combinational Circuits
There is feedback is a topological sense, but not in an electrical sense.
b c b c
f2 f3 f4 f5 f6f1
a a
Cyclic circuits can be combinational.
Example due to Rivest (1977):
Cyclic Combinational Circuits
There is feedback is a topological sense, but not in an electrical sense.
b c b ca a
)( cba )( bac )( cab cab cba bac
Cyclic circuits can be combinational.
Example due to Rivest (1977):
Cyclic Combinational Circuits
Cyclic circuits can be smaller than acyclic circuits.
21
• We have constructed a family of cyclic circuits that are the size.
32• Rivest constructed a family of cyclic circuits that are
the size of any equivalent acyclic circuits (1977).
• We have proposed a general methodology for the synthesis of cyclic combinational circuits.
• Benchmark circuits were optimized significantly: improvements of up to 30% in the area (literal count).
For details see The Synthesis of Cyclic Combinational Circuits, DAC’03.
Most circuits can be optimized with cycles.
Cyclic Combinational Circuits
Illustrative Example
abcd
efgh
Circuit
Lookup Table for Digits of d c b a h g f e
inputs outputs
0 0 0 0 0 3 0 0 1 1 1 0 0 0 1 1 0 0 0 1 2 0 0 1 0 4 0 1 0 0 3 0 0 1 1 1 0 0 0 1 4 0 1 0 0 5 0 1 0 1 5 0 1 0 1 9 1 0 0 1 6 0 1 1 0 2 0 0 1 0 7 0 1 1 1 6 0 1 1 0 8 1 0 0 0 5 0 1 0 1 9 1 0 0 1 3 0 0 1 1 10 1 0 1 0 5 0 1 0 1 11 1 0 1 1 8 1 0 0 0 12 1 1 0 0 9 1 0 0 1 13 1 1 0 1 7 0 1 1 1 14 1 1 1 0 9 1 0 0 1 15 1 1 1 1 3 0 0 1 1
h
g
f
e
)( dcbdcbacda ))(()( dbcdcbadbdbac
)()( bccbaddbbca )( caddcab
h
g
e
f
Multilevel acyclic network:
Example: Digits of
)( dcbdcbacda ))(( dabdachcba
)( gdeagda bdahga
h
g
f
e
Cost: 33(literal count)
Multilevel cyclic network:
Cost: 31(literal count)
e
g
hf
))(( cddcaf )( cbdaeahcba
)( bcdbagda )( bhdchaf
h
g
f
e
Is it combinational?
Example: Digits of
Inputs d,c,b,a = [0,0,0,0]:
))(( cddcaf )( cbdaeahcba
)( bcdbagda )( bhdchaf
h
g
f
e
= 1
= g
= 0
= 0
Outputs h,g,f,e = [0,0,1,1](3 is the first digit of )
e
g
hf
= 1
= 0
= 0
= 1
Example: Digits of
Inputs d,c,b,a = [1,1,1,1]:
))(( cddcaf )( cbdaeahcba
)( bcdbagda )( bhdchaf
h
g
f
e
= 1
Outputs h,g,f,e = [0,0,1,1](3 is the 16th digit of )
= +hf
= f= he
= 1
= 0
= 0
e
g
hf
= 1
Example: Digits of
There are cycles in a topological sense, but none are sensitized in an electrical sense.
e
g
hf
Analysis
e
g
hf
Combinationality Analysis:ensure that there are no sensitized cycles.
Timing Analysis:find the length of sensitized paths.
Analysis
?
Synthesis
Cost 40 (literal count)
h )( dcbdcbacda g ))(()( dbcdcbadbdbac f )()( bccbaddbbca e )( caddcab
))(( cddcaf h )( cbdaeahcba g
)( bcdbagda f )( bhdchaf e
Cost 31 (literal count)
Goal: optimize a multi-level network representation.Strategy: introduce cycles in the substitute/minimize step.
network N1 network N2
Analysis
Malik (1994), Shiple et al. (1996), and Edwards (2003) have addressed the analysis of cyclic combinational circuits.
Prior work:
• Determine if a cyclic circuit is combinational for all input assignments in the “care” set.
• Perform analysis symbolically (using BDD’s).
Central step in synthesis:
Analysis
Novel algorithm based on a “first-cut” approach.
Observation: for each input assignment, in every strongly-connected component at least one node must be fully defined independently of the others.
e
g
hf
Marginal
Given a node function
the marginal
specifies, in terms of X, when F is fully defined independently of Y.
e
g
hf
),( YXF
YF
X: primary input variablesY: internal variables
Marginal
e
g
hf
For input assignments that satisfy
bdcahfe ),(
e is fully defined, independently of f, h.
For example, consider
The marginal can be computedefficiently (with BDD’s)
)( b hdchaf e
Analysis
Cut each node from the network, and apply the algorithm recursively.
e
g
hf
eN
First-Cut Analysis:
Analysis
e
g
hf
and eN is combinational
and fN is combinational
and gN is combinational
and hN is combinational
Necessary and sufficient condition:
Eitherhfe ),(
orgf
heg ),(or
or
fh
Analysis for Synthesis
Advantage of Recursive Formulation:
Optimal local solution (subject to constraints) is part of optimal global solution (subject to constraints).
Attack problem by breaking network into components.
3N2N
1N
e
h
f
g
Analysis for Synthesis
g )( cbeafhfa
Design f, g component:
f )( gdeahga
Not combinational.Exclude all solutions with this component.
Exclude non-combinational components.
Design e, f, g component:
Combinational.Focus on h.
e
f
g h
)( cbdaeahcba )( bcdbagda
)( bhdchaf
g
f
e
Analysis for Synthesis
Cache combinational components.
e
f
g h
?
Analysis for Synthesis
Combinational.Focus on h.
Design e, f, g component:
)( cbdaeahcba )( bcdbagda
)( bhdchaf
g
f
e
Cache combinational components.
e
f
g h
Analysis for Synthesis
Combinational.Focus on h.
Design e, f, g component:
)( cbdaeahcba )( bcdbagda
)( bhdchaf
g
f
e
Cache combinational components.
?
e
f
g h
Analysis for Synthesis
Combinational.Focus on h.
Design e, f, g component:
)( cbdaeahcba )( bcdbagda
)( bhdchaf
g
f
e
Cache combinational components.
?
e
f
g h
Analysis for Synthesis
Combinational.Focus on h.
Design e, f, g component:
)( cbdaeahcba )( bcdbagda
)( bhdchaf
g
f
e
Cache combinational components.
?
e
f
g h))(( cddcaf h
Combinational.
Analysis for Synthesis
Design e, f, g component:
)( cbdaeahcba )( bcdbagda
)( bhdchaf
g
f
e
Cache combinational components.
?
Combinational.Focus on h.
Implementation: CYCLIFY Program
• Incorporated synthesis methodology in a general logic synthesis environment (Berkeley SIS package).
• Trials on wide range of circuits– randomly generated– benchmarks– industrial designs.
• Consistently successful at finding superior cyclic solutions.
Benchmark Circuits
Cost (literals in factored form) of Berkeley SIS Simplify vs. Cyclify
Circuit # Inputs # Outputs Berkeley Simplify Caltech Cyclify Improvementdc1 4 7 39 34 12.80%ex6 8 11 85 76 10.60%p82 5 14 104 90 13.50%t4 12 8 109 89 18.30%bbsse 11 11 118 106 10.20%sse 11 11 118 106 10.20%5xp1 7 10 123 109 11.40%s386 11 11 131 113 13.70%dk17 10 11 160 136 15.00%apla 10 12 185 131 29.20%tms 8 16 185 158 14.60%cse 11 11 212 177 16.50%clip 9 5 213 189 11.30%m2 8 16 231 207 10.40%s510 25 13 260 227 12.70%t1 21 23 273 206 24.50%ex1 13 24 309 276 10.70%exp 8 18 320 262 18.10%
(best examples)
Benchmarks
Example: EXP circuit
Cyclic Solution (Caltech CYCLIFY): cost 262
Acyclic Solution (Berkeley SIS): cost 320
cost measured by the literal count in the substitute/minimize phase
Discussion
• Most combinational circuits can be optimized with cycles.• Optimizations are significant.
Cyclic Combinational Circuits:
Symbolic framework for analysis:
• Analyze combinationality and timing.• Tightly integrated with synthesis.
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