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Page 1: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

CMOS Device Model

• Objective– Hand calculations for analog design– Efficiently and accurately simulation

• CMOS transistor models– Large signal model– Small signal model– Simulation model– Noise model

Page 2: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

Large Signal Model• Nonlinear equations for solving dc values of

device currents given voltages• Level 1: Shichman-Hodges (VT, K', , and

NSUB)• Level 2: with second-order effects (varying

channel charge, short-channel, weak inversion, varying surface mobility, etc.)

• Level 3: Semi-empirical short-channel model• Level 4: BSIM models. Based on automatically

generated parameters from a process characterization. Good weak-strong inversion transition.

Page 3: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

Transconductance when VDS is small

Page 4: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

Transconductance when VDS is small

Page 5: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

Transconductance when VDS is small

Page 6: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

Effect of changing VDS for a large VGS

Page 7: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

Effect of changing VDS for a given VGS

Page 8: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

Effect of changing VDS for a given VGS

Page 9: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

Effect of changing VDS for various VGS

VGS<=VT

Page 10: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

Effect of changing VDS for various VGS

Page 11: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

Effect of changing VDS for various VGS

Page 12: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

MOST Regions of Operation

• Cut-off, or non-conducting: VGS <VT

– ID=0

• Conducting: VGS >=VT

– Saturation: VDS > VGS – VT

– Triode or linear or ohmic or non-saturation: VDS <= VGS – VT

)-)V - V((vL

WμC i DSV

DSTGSox

D 2

2

2

2) - V(v

L

WμC i TGS

oxD

Page 13: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

With channel length modulation

)λV() - V(vL

WμC i DSTGS

oxD 1

22

) 22(0 | |φ - | |v| |φ V V fBSfTT

L

WK

L

WμC ox '

Page 14: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

Capacitors Of The Mosfet

Page 15: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

CBD and CBS include both the diffusion-bulk junction capacitance as well as the side wall junction capacitance. They are highly nonlinear in bias voltages.

C4 is the capacitance between the channel and the bulk. It is highly nonlinear and depends on the operation of the device. C4 is not measurable from terminals.

Page 16: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

/2

Page 17: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

Gate related capacitances

Page 18: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.
Page 19: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.
Page 20: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

Small signal model

Page 21: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

Typically: VDB, VSB are in such a way that there is a reversely biased pn junction.

Therefore: gbd ≈ gbs ≈ 0

Page 22: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

In saturation:

But

Page 23: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

In non-saturation region

Page 24: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

High Frequency Figures of Merit T

• AC current source input to G• AC short S, D, B to gnd• Measure AC drain current output• Calculate current gain• Find frequency at which current gain = 1.

• Ignore rs and rd, Cbs, Cbd, gds, gbs, gbd all have zero voltage drop and hence zero current

• Vgs = Iin /jw(Cgs+Cgb+Cgd) ≈ Iin /jwCgs

• Io = − (gm − jw Cgd)Vgs ≈ − gmVgs

• |Io/Iin| ≈ gm/wCgs

Page 25: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

• At T, current gain =1

• T ≈ gm/(Cgs+Cgd)≈ gm/Cgs

• or

Page 26: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

• AC current source input to G• AC short S, D, B to gnd• Measure AC power into the gate• Assume complex conjugate load• Compute max power delivered by the transistor• Find maximum power gain• Find frequency at which power gain = 1.

High Frequency Figures of Merit max

Page 27: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

• max: frequency at which power gain becomes 1

PL=

Page 28: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

BSIM models• Non-uniform charge density• Band bending due to non-uniform gate voltage• Non-uniform threshold voltage

– Non-uniform channel doping, x, y, z– Short channel effects

• Charge sharing• Drain-induced barrier lowering (DIBL)

– Narrow channel effects– Temperature dependence

• Mobility change due to temp, field (x, y)• Source drain, gate, bulk resistances

Page 29: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

“Short Channel” Effects

• VTH decreases for small L

– Large offset for diff pairs with small L

• Mobility reduction:– Velocity saturation

– Vertical field (small tox=6.5nm)

– Reduced gm: increases slower than root-ID

Page 30: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

Threshold Voltage VTH

• Strong function of L– Use long channel for VTH matching

– But this increases cap and decreases speed

• Process variations– Run-to-run– How to characterize?– Slow/nominal/fast– Both worst-case & optimistic

Page 31: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

Effect of Velocity Saturation

• Velocity ≈ mobility * field

• Field reaches maximum Emax

– (Vgs-Vt)/L reaches ESAT

• gm become saturated:– gm ≈ ½nCoxW*ESAT

• But Cgs still 2/3 WL Cox

• T ≈ gm/Cgs = ¾ nESAT /L

• No longer ~ 1/L^2

Page 32: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

Threshold Reduction• When channel is short, effect of Vd extends to S• Cause barrier to drop, i.e. Vth to drop• Greatly affects sub-threshold current: 26 mV Vth

drop current * e• 100~200 mV Vth drop due to Vd not uncommon

100s or 1000 times current increase

• Use lower density active near gate but higher density for contacts

Page 33: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

Other effects• Temperature variation• Normal-Field Mobility Degradation• Substrate current

– Very nonlinear in Vd

• Drain to source leakage current at Vgs=0– Big concern for static power

• Gate leakage currents– Hot electron– Tunneling – Very nonlineary

• Transit Time Effects

Page 34: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

Consequences for Design • SPICE (HSPICE or Spectre)

– BSIM3, BSIM4 models– Accurate but inappropriate for hand analysis– Verification (& optimization)

• Design:– Small signal parameter design space:

• gm, CL (speed, noise)

• gm/ID, ID (power, output range, speed)

• Av0= gmro (gain)

– Device geometries from SPICE (table, graph);

– may require iteration (e.g. CGS)

Page 35: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

Sweep V1Measure vgs

Intrinsic voltage gain of MOSFET

Intrinsic voltage gain = gm/go = vds/vgs for constant Id

Page 36: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

Electronic Noise• Noise phenomena• Device noise models• Representation of noise (2-ports):

– Motivation– Output spectral density– Input equivalent spectral density– Noise figure– Sampling noise (“kT/C noise”)

• SNR versus Bits• Noise versus Power Dissipation

– Dynamic range– Minimum detectable signal

Page 37: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

Noise in Devices and Circuits

•Noise is any unwanted excitation of a circuit, any input that is not an information-bearing signal.• External noise: Unintended coupling with other parts of the physical world; in principle, can be virtually eliminated by careful design.• Intrinsic noise: Unpredictable microscopic events inherent in the device/circuit; can be reduced, but never eliminated. •Noise is especially important to consider when designing low-power systems because the signal levels (typically voltages or currents) are small.

Page 38: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

Noise vs random process variations

• random process variations– Variations from one device to another– For any device, it is fixed after fabrication

• Noise– Unpredictable variations during operation– Unknown after fabrication– Remains unknown after measurement during

operation– May change with environment

Page 39: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

Time domain description of noise

Page 40: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

What is signal and what is noise?

Page 41: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

)()()( tntstx

srmsT

s PSrmsSdttsT

P )(,)(1

02

nrmsT

n PNrmsNdttnT

P )(,)(1

02

Signal and noise power:

Page 42: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

Physical interpretation

power

If we apply a signal (or noise) as a voltage source across a one Ohm resistor, the power delivered by the source is equal to the signal power.

Signal power can be viewer as a measure of normalized power.

Page 43: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

Signal to noise ratio

)(log20)(log10 1010rms

rms

n

s

N

S

P

PSNR

SNR = 0 dB when signal power = noise power

Absolute noise level in dB:w.r.t. 1 mW of signal power

)log(10dB30

mW1log10din

n

nmn

P

PP

B

Page 44: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

SNR in bits• A sine wave with magnitude 1 has power

= 1/2.• Quantize it into N=2n equal levels between

-1 and 1 (with step size = 2/2n)• Quantization error uniformly distributed

between +–1/2n

• Noise (quantization error) power=1/3 (1/2n)2

• Signal to noise ratio = 1/2 ÷ 1/3 (1/2n)2 =1.5(1/2n)2 = 1.76 + 6.02n dB or n bits

Page 45: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

-1<=C<=+1

C=0: n1 and n2 uncorrelatedC=1: perfectly correlated

Page 46: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

Adding uncorrelated noises

Adding correlated noises

Page 47: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

For independent noises

Page 48: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

Frequency domain description of noise

T

TTn dttntn

TR )()(

2

1lim)(

))(()()( nnn RfSfPSD F

dffPSDP nn )(

dffPSDP nn )(0

Given n(t) stationary, its autocorrelation is:

The power spectral density of n(t) is:

For real signals, PSD is even. can use single sided spectrum: 2x positive side

↑ single sided PSD

Page 49: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

)()( fXtx

dffXdttx

22)()(

)()( fPSDR xx

dffPSDRdttx xx

T

TT

)()0()(lim

2

Parseval’s Theorem:

If

If x(t) stationary,

Page 50: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

Interpretation of PSD

PSDx(f)

Pxf1 = PSDx(f1)

Page 51: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.
Page 52: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.
Page 53: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

Types of “Noise” • “man made”

– Interference– Supply noise– …– Use shielding, careful layout, isolation, …

• “intrinsic” noise– Associated with current conduction– “fundamental” –thermal noise– “manufacturing process related” – flicker noise

Page 54: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

Thermal Noise • Due to thermal excitation of charge carriers in a

conductor. It has a white spectral density and is proportional to absolute temperature, not dependent on bias current.

• Random fluctuations of v(t) or i(t)• Independent of current flow• Characterization:

– Zero mean, Gaussian pdf– Power spectral density constant or “white” up to about

80THz

Page 55: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

Thermal noise dominant in resisters

Example:R = 1kΩ, B = 1MHz, 4µV rms or 4nA rms

Page 56: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

HW

Equivalently, we can model a real resistor with an ideal resistor in parallel with a current noise source. What rms value should the current source have?

Show that when two resistors are connected in series, we can model them as ideal series resistors in series with a single noise voltage source. What’s the rms value of the voltage source?

Show that two parallel resistors can be modeled as two ideal parallel resistors in parallel with a single noise current source. What’s the rms value of the current source?

Page 57: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

Noise in Diodes Shot noise dominant– DC current is not continuous and smooth but

instead is a result of pulses of current caused by the individual flow of carriers.

It depends on bias, can be modeled as awhite noise source and typically larger than

thermal noise. − Zero mean – Gaussian pdf – Power spectral density flat – Proportional to current – Dependent on temperature

Page 58: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

Example:ID= 1mA, B = 1MHz, 17nA rms

Page 59: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

MOS Noise Model

Page 60: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

Flicker noise

–Kf,NMOS 6 times larger than Kf,PMOS

–Strongly process dependent

−when referred to as drain current noise, it is inversely proportional to L2

Page 61: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

BJT Noise

Page 62: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

Sampling Noise • Commonly called “kT/C” noise

• Applications: ADC, SC circuits, …

von

R

C

Used:

Page 63: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

Filtering of noise

H(s)x(t) y(t)

|H(f )|2 = H(s)|s=j2f H(s)|s=-j2f

Page 64: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

Noise Calculations 1) Get small-signal model2) Set all inputs = 0 (linear superposition)

3) Pick output vo or io4) For each noise source vx, or ix Calculate Hx(s) = vo(s) / vx(s) (or … io, ix)5) Total noise at output is

6) Input Referred Noise: Fictitious noise source at input: 22

,2

, )(/ sAvv Toneffin

Page 65: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

Example: CS Amplifier

CL

VDD

RL

Von=(inRL +inMOS)/goT

goT = 1/RL + sCL

LBnR RTki

L

142

mBnMOS gTki3

242

Page 66: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

o=1/RLCL

Page 67: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

Some integrals

Page 68: CMOS Device Model Objective –Hand calculations for analog design –Efficiently and accurately simulation CMOS transistor models –Large signal model –Small.

HW

In the previous example, if the transistor is in triode, how would the solution change?

HW

If we include the flicker noise source, how would that affect the computation? What do you suggest we should modify?

HW

In the example, if RL is replaced by a PMOS transistor in saturation, how would the solution change? Assume appropriate bias levels.


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