Clockless Chips

INTRODUCTION

How fast is your personal computer?

When people ask this question, they are typically referring to the frequency of a minuscule clock inside the computer, a crystal oscillator that sets the basic rhythm used throughout the machine. In a computer with a speed of one gigahertz, for example, the crystal "ticks" a billion times a second. Every action of the computer takes place in tiny steps, each a billionth of a second long. A simple transfer of data may take only one step; complex calculations may take many steps. All operations, however, must begin and end according to the clock's timing signals.

The use of a central clock also creates problems. As speeds have increased, distributing the timing signals has become more and more difficult. Present-day transistors can process data so quickly that they can accomplish several steps in the time that it takes a wire to carry a signal from one side of the chip to the other. Keeping the rhythm identical in all parts of a large chip requires careful design and a great deal of electrical power. Wouldn't it be nice to have an alternative?

Clockless approach, which uses a technique known as asynchronous logic, differs from conventional computer circuit design in that the switching on and off of digital circuits is controlled individually by specific pieces of data rather than by a tyrannical clock that forces all of the millions of the circuits on a chip to march in unison. It overcomes all the disadvantages of a clocked circuit such as slow speed, high power consumption, high electromagnetic noise etc. For these reasons the clockless technology is considered as the technology which is going to drive majority of electronic chips in the coming years.

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Clockless Chips

A BRIEF HISTORY

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CONCEPT OF CLOCKS

The clock is a tiny crystal oscillator that resides in the

heart of every microprocessor chip. The clock is what which sets the basic rhythm used throughout the machine. The clock orchestrates the synchronous dance of electrons that course through the hundreds of millions of wires and transistors of a modern computer.

Such crystals which tick up to 2 billion times each second in the fastest of today’s desktop personal computers, dictate the timing of every circuit in every one of the chips that add, subtract, divide, multiply and move the ones and zeros that are the basic stuff of the information age.

Conventional chips (synchronous) operate under the

control of a central clock, which samples data in the registers at precisely timed intervals. Computer chips of today are synchronous: they contain a main clock which controls the timing of the entire chips.

One advantage of a clock is that, the clock signals to the devices of the chip when to input or output. This functionality of the synchronous design makes designing the chip much easier. There are problems that go along with the clock, however.

Clock speeds are now in the gigahertz range and there is not much room for speedup before physical realities start to complicate things. With a gigahertz clock powering a chip, signals barely have enough time to make it across the chip before the next clock tick. At this point, speedup up the clock frequency could become disastrous. This is when a chip that is not constricted by clock speeds could become very valuable.

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Clockless Chips

WORKING OF A SYNCHRONOUS CIRCUIT

This is the working model of a particular synchronous circuit. A synchronous circuit looks for a particular signal of the clock. In this case, the circuit is looking for the leading edge of the clock pulse. As we see in the figure, all actions in this circuit take place only on the leading edge of the clock cycle. Especially when transferring the data on to the registers the computations settle down and wait for the next leading edge of the clock to occur. Then only the data will be transferred to the next register.

The figure gives a clear idea of how conventional chips operate under the control of a central clock, which samples data in the registers at precisely timed intervals. The only thing the designers have to think about is how to complete one operation during a single tick of the clock. It is extremely important to design the circuits in such a fashion that all the computations must settle down and be ready for the next logical operation before the next clock tick.

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Clockless Chips

PROBLEMS OF SYNCHRONOUS CIRCUITS

One problem is speed. A chip can only work as fast as its

slowest component. Therefore, if one part of the chip is especially slow, the other parts of the chip are forced to sit idle. This wasted computing time is obviously detrimental to the speed of the chip.

New problems with speeding up a clocked chip are just around the corner. Clock frequencies are getting so fast that signals can barely cross the chip on one clock cycle. When we get to the point where the clock cannot drive the entire chip, we'll be forced to come up with a solution. One possible solution is a second clock, but this will incur overhead and power consumption, so this is a poor solution. It is also important to note that doubling the frequency of the clock does not double the chip speed, therefore blindly trying to increase chip speed by increasing frequency without considering other options is foolish.

The other major problem with a clocked design is power consumption. The clock consumes more power than another other component of the chip. The most disturbing thing about this is that the clock serves no direct computational use. A clock does not perform operations on information; it simply orchestrates the computational parts of the computer.

New problems with power consumption are arising. As the number of transistors on a chip increases, so does the power used by the clock. Therefore, as we design more complicated chips, power consumption becomes an even more crucial topic. Mobile electronics are the target for many chips. These chips need to be even more conservative with power consumption in order to have a reasonable battery lifetime.

The natural solution to the above problems, as you may have guessed, is to eliminate the source of these headaches: the clock.

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Clockless Chips

CONCEPT OF CLOCKLESS CHIPS

The main concept behind a clockless design is evident from the name itself. That is, they don’t have a global clock which synchronizes its actions. So there must be some control mechanism which should synchronize the components inside a clockless chip to ensure correct working of the chip. The clockless chips rely up on handshaking signals, handoff signals & sometimes a local clock to synchronize the actions.

By throwing out the clock, chip makers will be able to

escape from the problems of the synchronous circuits. Clockless chips draw power only when there is useful work to do, enabling a huge savings in battery-driven devices; an asynchronous-chip-based pager marketed by Philips Electronics, for example, runs almost twice as long as competitors' products, which use conventional clocked chips.

Like a team of horses that can only run as fast as its slowest member, a clocked chip can run no faster than its most slothful piece of logic; the answer isn't guaranteed until every part completes its work. By contrast, the transistors on an asynchronous chip can swap information independently, without needing to wait for everything else. The result? Instead of the entire chip running at the speed of its slowest components, it can run at the average speed of all components. At both Intel and Sun, this approach has led to prototype chips that run two to three times faster than comparable products using conventional circuitry.

Another advantage of clockless chips is that they give off very low levels of electromagnetic noise. The faster the clock, the more difficult it is to prevent a device from interfering with other devices; dispensing with the clock all but eliminates this problem.

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WORKING OF ASYNCHRONOUS CIRCUIT

Clockless (also called asynchronous, self timed or event driven) chips dispense with the timepiece. The figure below gives an idea of working of an asynchronous circuit. In this particular scheme (which is called a duel rail circuit which will be discussed later), data moves instead under the control of local "handshake" signals (lines below) that indicate when work has been completed and is ready for the next logic operation.

As we can see above there is the usual logical circuitry and instead of a clock signal which controls the circuit, there are two lines on the top and bottom. The wires are used to transfer the data bits and the control bits together. So there is no separate control signal going across the circuit. The control signal is encoded within the data that is being transferred. This control signals act as handshaking and handoff signals which indicates when the component is ready for the next logical operation.

There are different ways to implement an asynchronous circuit. The next part is about various types of implementation.

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TYPES OF IMPLEMENTATIONS

There are mainly three kinds of implementations of an asynchronous circuit. They are the following.

1. BOUNDED DELAY METHOD2. DELAY INSENSITIVE METHOD3. NULL CONVENTIONAL LOGIC(NCL)

The simplest implementation of asynchronous design is the Bounded-Delay method. This design is very similar to synchronous design; in Bounded-Delay design we assume that we know the largest amount of time for each component to perform its task. Knowing the bounds of the delay time allows for computations to be sped up.

The Delay-Insensitive method, which is quite the opposite of Bounded-Delay, does not assume any bounds on time. As a result, handshaking is needed between components.

Another way of implementing an asynchronous design is to use NULL Convention Logic (NCL). This convention uses a NULL state when data is in the reset phase, as opposed to DATA in the set phase. The theory behind NCL is simple. If a gate has any inputs that are NULL, then this gate has an output which is NULL. Once the gate gets all its inputs, that are all its inputs are DATA, then the output of the gate is DATA. In this way, the gates do not need to be clocked because they do their computation as soon as possible.

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THE GENERAL MODEL

The general model of an asynchronous design implementation is shown above. In this circuit we can see a logic circuit which does the same operation as in the synchronous circuit. This is the actual logic which does all the calculation.

Attached to this logic circuit is the completion detection unit which helps the circuit to proceed in a controlled fashion i.e. without an error. This completion detection unit indicates when the circuit has completed its action and when it is ready for the next action.

The input signal in the combinational logic part and the “go” signal in the completion detection circuit reach the unit simultaneously. When the combinational logic is done with the input signal, a “done” signal is produced by the completion detection circuit. This signal is an indication given by the completion detection circuit for the signal to pass to the next step. In some cases the “done” signal acts as the “go” signal to the completion detection circuit of the next stage.

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BOUNDED DELAY

The above circuit shows the working model of a bounded delay circuit. Bounded delay method is quite similar to the design of synchronous circuits. In bounded delay method we assume that we know the maximum time a component takes to complete its working. So this is kept in mind while designing an asynchronous circuit. I.e. the circuit is designed in such a way that the control will be transferred to the next circuit only when the previous component completes its work. To do this we introduce the maximum time which a circuit takes as the prototype delay.

In the circuit we can see that, comparing with the general model, the circuit which introduces the prototype delay acts as the completion detection circuit in bounded delay method. That is, a component is considered to have finished its working when the introduced delay is over.

But this kind of implementation has a disadvantage. Here we are assuming the maximum time taken and this is introduced as the delay. So it is not possible to do early completion even if the circuit doesn’t take the maximum time. So it is forced to wait until the delay is over.

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DELAY-INSENSITIVE METHOD

Contrary to the bounded delay method which assumes bounds on time, the delay-insensitive method doesn’t assume any bounds on time. Therefore communication between independent components is essential. This is done with the help of handshake and hand off signals. These signals indicate when the job of a component is over.

There are many ways in which a delay insensitive method can be done. The most popular and efficient method is the “duel-rail encoding” method. In this method separate channels are open for data and control signals. Signals of both the channels together indicate the control and data signals.

In one method each signal X is encoded with two wires XH & XL. The encoding scheme is shown below

XH=0 XL=0 -- Data not ready. XH=0 XL=1 -- Logical “0”. XH=1 XL=0 -- Logical “1”. XH=1 XL=1 -- Not used.

As we see from the coding above, each wire in the logical circuit will now need two wires to implement a duel-rail circuit. So the input will consist of a total of four wires and the output will consist of two wires. Thus special kind of gates would be required to implement the logics. The AND, OR & NOT gates are shown below.

NOT gate can be implemented simply as the only thing we need to do is to reverse the wires. I.e. CH=XL & CL=XH.

AHAL

BH

CH=AH*BHCL=AL+BL

AHAL

BH

CH=AH+BHCL=AL*BL

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NULL CONVENTIONAL LOGIC

NULL Convention Logic (NCL) is a logic that integrates data transformation and control into a single expression, thus yielding inherently clockless or delay insensitive circuits and systems. “NCL” enables solutions for digital designs facing the critical power, noise, or system integration issues. The following NCL features enable the designer to solve these problems:

NCL uses a combination of multiwire data representation and control/signaling protocol: NCL circuits switch between a voltage based data representation of DATA and a control representation of NULL. This separation between control and data representations provides a self-synchronization throughout the design. No clock is needed.

NCL uses threshold gates with hysteresis: Threshold gates provide the basic building block of NCL designs. Threshold gate inputs and outputs can be in one of two states, DATA or NULL. A threshold gate starting with its output in a NULL state will remain in the NULL state until the specified number of inputs is placed in the DATA state. Once the gate reaches the DATA state, it remains in this state until all of the inputs return to the NULL state. The hysteresis in the threshold gate provides the threshold needed to keep from switching during the intermediate state when the number of inputs in the DATA state is greater than zero, but less than the threshold limit. In addition, hysteresis provides the storage to remain at DATA until all of the inputs have returned to NULL. Since these gates use two values, as traditional Boolean logic does, they can be constructed with traditional CMOS (or Bipolar) processes.

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MERITS OF ASYNCHRONOUS CIRCUITS

There are mainly three advantages of clockless design. They are

Increase in speed. Reduced power consumption. Less electromagnetic noise.

The first of these advantages is speed. Chips can run at the average speed of all its components instead of the speed of the slowest component, as was the case with a clocked design. The transistors on an asynchronous chip can swap information independently, without needing to wait for everything else. At both Intel and Sun micro systems, this approach has led to prototype chips that run two to three times faster than comparable products using conventional circuitry. Therefore the speed of an asynchronous design is not limited by the size of the chip. An example of how much an asynchronous design can improve speed is the asynchronous Pentium designed by Intel in 1997 that runs three times as fast as the synchronous equivalent.

Another crucial advantage of clockless chips is the reduction in power consumption. The reason for this is that asynchronous chips use power only during computations, while a clocked circuit is always running. The Intel Pentium referred above ran three times faster than clocked equivalent with half the power.

The third advantage of the clockless design is that it produces less electromagnetic noise which interferes with the working frequencies of other signals.

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SPEED COMPARISON

The above figure of the bucket brigade can be used to describe the flow of data in a computer. A synchronous computer system is like a bucket brigade in which each person follows the tick tock rhythm of a clock. When the clock ticks, each person pushes a bucket forward to the next person down the line (top). When the clock tocks, each person grasps the bucket pushed forward by the preceding person (middle). An asynchronous system, in contrast, is like an ordinary bucket brigade: each person who holds a bucket can pass it down the line as soon as the next person’s hands are free.

It is quite evident from the above metaphor, why the clockless chip is faster and effective. The clockless chips can run on the average speed of all of its components rather than adopting the speed of the slowest member. This is because of the fact that an action is not restricted by the rules like those in a clocked design.

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POWER & NOISE CHARECTERISTICS

POWER

The above graphics is obtained from the Philips official website. It illustrates the power saving character of the clockless chip. This is an experiment to find out the heat emitted by a chip by placing it under special kind of light. The chip on the left side is a synchronous chip and the one to the right is its asynchronous equivalent. The red spots on the chip indicate the positions where heat is dissipated. It is clear from the figure that the synchronous emit more heat as it has the more number of red spots on the light emission measurements.

It is clear that a chip which produces the more heat would consume more power. Clearly synchronous chips consume more power than the asynchronous equivalent.

The reason for this is that asynchronous chips use power only during computations, while a clocked chip always consumes power because the chip is always running. The clock together with its timing circuits not only take up a good area of the chip, but also account for 30% of the total power consumed by the chip. So removing this would surely give an increase in life of the battery. It is

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also important to note that the idle parts of a clockless chip consume negligible amount of power.

The above said reason is more applicable in the case of mobile electronics where a battery is used to drive the chip. One would think that it is not much of an issue when we consider the case of a computer or other devices which can be plugged. But in this case the chip can cut the cost needed in the design of these equipments by reducing the need for cooling fans, air-conditioning and other cooling equipments in order to prevent overheating. The amount of power saved will depend on the machine’s pattern of activity. Systems with parts that act occasionally benefit more than systems that act continuously. Most computers have components, such as the floating-point arithmetic unit, that often remain idle for long periods.

NOISE

Now a day the demand for mobile devices is getting higher and higher. Everything around is becoming wireless. These devices work by sending and receiving radio signals. When a clocked circuit is used in these types of devices the noise generated by the large frequency of the clock interferes with the working frequency of the mobile devices. In order to avoid errors caused by these noise signals, designers would not be free to provide the scale of integration they wish.

Asynchronous systems produce less radio interference than synchronous machines. Because a clocked system uses a fixed rhythm, it broadcasts a strong radio signal at its operating frequency and at the harmonics of that frequency. Such signals can interfere with cellular phones, televisions and aircraft navigation systems that operate at the same frequencies. Asynchronous systems lack a fixed rhythm, so they spread their radiated energy broadly across the radio spectrum, emitting less at any one frequency.

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OTHER BENEFITES

Yet another benefit of asynchronous design is that it can be used to build bridges between clocked computers running at different speeds. Many computing clusters, for instance, link fast PCs with slower machines. These clusters can tackle complex problems by dividing the computational tasks among the PCs. Such a system is inherently asynchronous: different parts march to different beats. Moving data controlled by one clock to the control of another clock requires asynchronous bridges, because the data may be "out of sync" with the receiving clock.

Finally, although asynchronous design can be challenging, it can also be wonderfully flexible. Because the circuits of an asynchronous system need not share a common rhythm, designers have more freedom in choosing the system's parts and determining how they interact. Moreover, replacing any part with a faster version will improve the speed of the entire system. In contrast, increasing the speed of a clocked system usually requires upgrading every part.

A final advantage of the clockless chip is the ability to provide superior encryption. This is because there is no way for a hacker to track regularly timed signals, which are given away by the clock in a synchronous design. The hackers do not know what to look at. This has significant potential as security becomes an increasing priority. This becomes even more critical as computer all over the world become more closely connected and are sharing confidential material.

Improved encryption makes asynchronous circuits an obvious choice for smart cards—the chip-endowed plastic cards beginning to be used for such security sensitive applications as storage of medical records, electronic funds exchange and personal identification.

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APPLICATIONS

Clockless design is inevitable in the future of chip design because of the two major advantages of speed and power consumption, but where will we first see these designs in use?

The first place we'll see, clockless designs in the lab. Many prototypes will be necessary to create reliable designs. Manufacturing techniques must also be improved so the chips can be mass-produced.

The second place we'll see these chips are in mobile electronics. This is an ideal place to implement a clockless chip because of the minimal power consumption. Also, low levels of electromagnetic noise creates less interference; less interference is critical in designs with many components packed very tightly, as is the case with mobile electronics.

The third place is in personal computers (PCs). Clockless designs will occur here last because of the competitive PC market. It is essential in that market to create an efficient design that is reasonably priced. A manufacturing cost increase of a couple cents per chip can cause an entire line of computers to fail because of the large cost increase passed onto the customer. Therefore, the manufacturing process must be improved to create a reasonably priced chip.

A final place that asynchronous design may be used is encryption devices. The reason for this is there are no regularly timed signals for hackers to look for. This becomes even more critical as computer all over the world become more closely connected and are sharing confidential material. They will be also used in smart cars as they provide excellent security.

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CLOCKLESS PRODUCTS IN THE MARKET

Now of course, the question is why aren't Intel, AMD, and all the other chipmakers scrambling to put together research teams to design asynchronous prototypes? Well, actually, some have. In 1997, Intel developed a prototype of a Pentium style chip that ran 3 times as fast as a clocked equivalent, and used half the power, but lack of a perceived market convinced Intel to abandon the project (Intel's approach to asynchronous design seems to be slow integration-asynchronous circuitry is notoriously easy to integrate into clocked chips-and Intel has done so-including a few clockless elements in the Pentium IV series).

Sharp Corp. built an asynchronous chip for embedded applications in 1997, and Philips has consistently given a hefty budget to its asynchronous design research department for many years.

In the past few years, others have jumped on the bandwagon, including Motorola, who have joined forces with Theseus Logic (one of the first companies founded on the principle of asynchronous design) to produce a 32 bit processor and an 8 bit microcontroller, and MIPS, who have licensed their 32 bit Architecture to Fulcrum Microsystems, a competitor to Theseus.

The latest company to step into this field is a Manchester based company called SELF-TIMED SOLUTIONS which has developed clockless chips for communication devices.

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LIMITATIONS OF ASYNCHRONOUS CIRCUITS

Design difficulties.

Lack of good tools.

Testing difficulties.

DESIGN DIFFICULTIES

The primary drawback to asynchronous design is that it is hard. Control logic must operate in fundamental mode, or a close variant (like burst mode), and the synthesis formalisms are unfamiliar. Architectural design has all the same challenges that concurrent software has; researchers have yet to make concurrent software design a turnkey affair, despite decades of attention.

And of course, there is the basic obstacle that asynchronous design techniques have been out of favor since the 1980s, and are therefore not typically taught in universities. If a microprocessor design company today wanted to use asynchronous logic, they would have to begin by training their engineering staff in the basics.

LACK OF GOOD TOOLS

The predominance of CAD tools oriented towards synchronous design is another chicken-and-egg problem. However, most circuit simulation techniques are independent of synchrony, and existing tools can be adapted for asynchronous use. Also, previous

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academic design efforts have produced the first sprinkling of a dedicated tool base.

TESTING DIFFICULTIES

Testing asynchronous circuits presents several new challenges. For example, a common technique in synchronous testing is to slow or stop the clock, to allow the logic functions to be observed at human speeds. However, gating the request and/or acknowledge signals is a possibility, and it is at least conceivable that dropping Vdd to near the threshold could provide a useful slowing effect (and possibly more useful, since some of the slow-transition effects are preserved, unlike clock dividing).

Additionally, asynchronous circuits have timing requirements that are more constrained than synchronous circuits. Whereas the latter simply have to compute a valid result before the clock edge, asynchronous circuits may have minimum delays too; the prototype delay in a bounded-delay design is such a circuit.

Finally, related to the design difficulties, is the testing of

the possible interleaving scenarios, as in concurrent software. Asynchronous control circuitry must be designed to handle a variety of contingencies regarding timing, and the testing harness must be able to cause at least most of these possibilities.

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CONCLUSION

Why isn’t it popular?

Why doesn’t industry currently use asynchronous designs (with a handful of exceptions)? The main cause is risk. Asynchronous design techniques are sometimes seen as unproven, despite a number of academic (and industry) successes. Further, any asynchronous design will incur additional cost in training engineers to use techniques they didn’t learn in school. Finally, tool development is likely seen as an obstacle.

Moreover, at least up to now, industry has been getting by without asynchronous design. So far, the clocked designs have been feasible (if occasionally expensive), and low power does not yet dominate demand.

Should it be used? My conclusion is an emphatic yes! Clocks are getting

faster, while chips are getting bigger, both of which make clock distribution harder. Chips are also becoming more heterogeneous, with functions like memory and network interfaces being considered, all of which complicates the global timing analysis necessary for a synchronous design. Finally, we are entering an age when processors will be just about everywhere, and this will require very low power designs. It’s just not practical to expect a clean, skew-free clock for every (say) piece of clothing with a processing element.

But this can only happen if more focus, especially at the university level, is given to asynchronous design. Most of today’s designers don’t understand it well enough to use it, and may even regard it with suspicion. It is certainly a challenge, but just as the software community is moving towards more concurrency, the hardware community must move to incorporate asynchronous logic.

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REFERENCE

1. www.scientificamerican.com

2. www.iht.com

3. www.theseus.com

4. www.mips.com

5. www.nytimes.com

6. www.transentric.com

7. www.mdatechnology.net

8. www.cs.columbia.edu/async

9. www.fulcrummicro.com

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APPENDIX-1

CLOCKLESS COMPANIES AND THEIR ACHIEVEMENTS

COMPANY ACHIEVEMENTS GOALS

SUN MICROSYSTEMSPalo Alto, CA

Prototypes have demonstrated two to three times the speed ofStandard chips.

Gradually integrate “islands” of clockless logic into futureGenerations of microprocessors.

INTELSanta Clara, CA

Clockless prototype in 1997 ran three times faster than the conventional chip equivalent, on half the power.

Stay current with clockless R&D.

ASYNCHRONOUS DIGITAL DESIGNPasadena, CA

Founded by students of Caltech’s Alain Martin, who developed the First asynchronous microprocessor.

Produce chips for cell phones and other low-power communications devices; expected to announce plans byYear-end.

THESEUS LOGICMaitland, FL

Patented “null convention logic,” a way of letting clockless chips know when an operation isComplete.

License designs to manufacturers of smart cards and mobile devices; Motorola is a current customer.

PHILIPS ELECTRONICSEindhoven, Netherlands

Markets a clockless chip that gives its pagers up to twice the battery life of competitors.

Clockless chips for mobile devices and smart cards.

SELF-TIMED SOLUTIONS Manchester, England

Founded Steve Furber who has developed clockless chips for communications devices.

Clockless chips for smart cards.

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