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CHAPTER 5INTERNAL MEMORYCSNB123 COMPUTER ORGANIZATION
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Objectives• To study the types of semiconductor main
memory subsystems RAM DRAM SRAM
• ROM• Error correction
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Recall: Chapter 4 – Common Memory Parameters
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Memory Type
Technology Size Access Time
Cache Semiconductor RAM
128-512 KB
10 ns
Main Memory
SemiconductorRAM
4-128 MB 50 ns
MagneticDisk
Hard Disk Gigabyte 10 ms,10 MB/sec
Optical Disk CD-ROM Gigabyte 300 ms,600 KB/sec
MagneticTape
Tape 100s MB Sec-min.,10MB/min
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Semiconductor Main Memory• Basic element of semiconductor main memory
(smm) – memory cell• Cell properties;
2 stable states – 0 and 1 binary Capable of being written to set the state Capable of being read to sense the state
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Memory Cell OperationWrite Read
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Cell
Control
Select Data inCell
Control
Select Sense
Functional Terminal - Capable of carrying an electrical signal
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Three Functional Terminals• Select terminal – select memory cell for read
or write operation• Control terminal – indicates read or write
Write – other terminal provides an electrical signal sets the state of the cell to 1 or 0
Read – that terminal is used for output of the cell’s state
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All memory types in this chapter are random accessIndividual words of memory are directly accessed through wired-in addressing logic
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Semiconductor Memory Types
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Memory Type Category Erasure Write Mechanism Volatility
Random-access
memory (RAM)Read-write memory
Electrically, byte-level Electrically Volatile
Read-only memory (ROM) Read-only
memory Not possibleMasks
Nonvolatile
Programmable ROM (PROM)
Electrically
Erasable PROM (EPROM)
Read-mostly memory
UV light, chip-level
Electrically Erasable PROM (EEPROM)
Electrically, byte-level
Flash memory Electrically, block-level
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SEMICONDUCTOR MEMORY
All semiconductor memory is random accessDRAMSRAM
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Random Access Memory (RAM)• Characteristic
Read/Write – read data from the memory and to write new data into the memory • Use electrical signals
Volatile – must have constant power supply else data lost.
Temporary storage• 2 traditional forms of RAM
DRAM SRAM
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Dynamic RAM (DRAM)• Made with cells that store data as charge on
capacitors• The presence or absence of charge in a
capacitor is interpreted as a binary 1 or 0 Capacitors have tendency of discharging - needs to
periodically charge to maintain data storage• The term dynamic refers to this tendency of
the stored charge to leak away
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DRAM Structure• Figure 5.2 show a typical DRAM
structure for an individual cell that stores 1 bit
• The address line is activated when the bit value from this cell is to be read or written
• The transistor acts as a switch that is closed (allowing the current to flow) if a voltage is applied to the address line
• If no current flows, the switch is open means no voltage is present on the address line.
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DRAM OperationWrite• A voltage signal is applied to
the bit line • A high voltage represent 1,
a low voltage represent 0• A signal is then applied to
the address line allowing a charge to be transferred to the capacitor
Read• Select address line. The transistor
turns on and the charge stored on the capacitor is fed out onto a bit line and to a sense amplifier
• The sense amplifier compares the capacitor voltage to a reference value and determines if the cell contains a logic 1 or logic 0
• The readout from the cell discharges the capacitor which must be restored to complete the operation
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DRAM (Cont.)• Analog device• Capacitor stores any charge value within a
range Threshold value – determine whether the charge
is interpreted as 0 or1
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Static RAM (SRAM)• A digital device• Use the same logic elements as in the
processor• The binary values are stored using traditional
flip-flop logic gate configuration• Data remains as long as power is supplied to it
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SRAM StructureSRAM structure for an individual cell• Four transistors (T1,T2,T3,T4) are cross
connected in an arrangement that produces a stable logic state
• Logic state 1: C1 is high , C2 is low T1 ,T4 are off, T2,T3 are open
• Logic state 0: C1 is low, C2 is high T1,T4 are open, T2,T3 are off
• The SRAM address line is used to open/close a switch Controls two transistors (T5,T6) Apply signal to this line, T5,T6 are
switched on, allowing read/write operation
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SRAM OperationRead• The bit value is read from
line B
Write• The desired bit value is
applied to line B• Its complement is applied at
line B
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DRAM versus SRAM
DRAM• Simpler to build, smaller• More dense• Less expensive• Needs refresh• Larger memory units• Use as main memory
SRAM• Faster• Use as cache memory
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Volatile – need power to preserve data
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Read Only Memory (ROM)• Permanent storage
Nonvolatile• Use in
Microprogramming Library subroutines Systems programs (BIOS) Function tables
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Types of ROM• ROM• PROM• EPROM• EEPROM• Flash memory
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ROM• Data is written during manufacture
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PROM – Programmable ROM• Nonvolatile• Written once
Electrically – supplier or user Perform after fabrication Need special equipment to program
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EPROM – Erasable PROM• Read/write electrically• Before a write operation, empty the cells by
ultraviolet radiation• The erase procedure can be performed
repeatedly• Expensive than PROM
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Flash Memory• Intermediate between EPROM and EEPROM;
cost and functionality• Use an electrical erasing tech; much faster
than EEPROM• Possible to erase just blocks of memory
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EEPROM – Electrical EPROM • Can be written into at any time without
erasing prior contents - updates bytes address• Write operation is longer than read operation• Nonvolatile and flexible in update using
ordinary bus control
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Chip Logic• Each chip contains an array of memory cells• The array is organized into W words of B bits
each.• Example : a 16 –Mbit chip could be organized
as 1 M 16 words. ( word- is a fixed sized group of bits that are handled as a unit by the instruction set and/or hardware of the processor)
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Chip Packaging• An IC is mounted on a
package• There are pins used to
connect to the outside word
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Chip Packaging (Cont.)• 8 –Mbit chip
organization (1M x 8)• The organization is
treated as a one –word-per chip package. (word -16 bits=2 bytes)
• There are 32 pins , one of standard chip package
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Chip Packaging - Pins• Support the following signal lines
Address of word being accessed• For 1M words, a total of 1M (220) pins are needed , address A0-
A19 The data to be read out-have 8 lines (D0-D7) The power supply to the chip (Vcc) A ground pin (Vss) A chip enable (CE) pin - indicate whether or not the
address is valid for this chip A program voltage (Vpp) - supplied during programming
(write op)
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Interleaved Memory• Advance technique used by high-end
motherboards/chipsets to improve memory performance
• Increase bandwidth by allowing simultaneous access to more than one bank of memory
• Improves performance since CPU/processor can transfer more information to/from memory in the same amount of time, and helps ease the CPU-memory bottleneck
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ERROR CORRECTION
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Errors• A semiconductor memory is subject to errors.• Categories;
Hard failures Soft errors
• Example : power supply problem
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Errors – CategoriesHard Failures• A permanent physical
defect so that the memory cells affected cannot reliably store data but become stuck at 0 or 1
Soft Error• A random, nondestructive
event that alters the contents of one or more memory cells without damaging the memory
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Process of Detecting and Correcting Errors
• When data are to be read into memory, a calculation, function f is performed on the data to produce a code
• Both the code and the data are stored• If M –bit word of data is to be stored and the code is of length K bits,
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Process of Detecting and Correcting Errors (Cont.)
• When the previous stored word is read out, the code is used to detect and possibly correct errors
• A new set of K code bits is generated from the M data bits and compared with the fetched code bits
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Process of Detecting and Correcting Errors (Cont.)
• Three results of the comparisons; No errors-the fetched data bits are sent out An error is detected-possible to correct, the data
bits +error correction bits are fed out into a corrector, which produces a corrected set of M bits to be sent out
An error is detected and connect be corrected, this condition is reported
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Process of Detecting and Correcting Errors (Cont.)
• The codes are referred as error-correcting codes
• A code is characterized by the number of bit errors in a word that it can correct and detect
• The simplest error-correcting codes is the Hamming code
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Hamming Code• Use to detect and correct one-bit change in an
encoded code word• Consider the table which has 15 positions.
Data is represented (stored) in every position except 1, 2, 4 and 8. These positions are used to store parity (error correction) bits
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Hamming Code (Cont.)• Using the four parity
(error correction bits) positions we can represent 15 values (1- 15)
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Hamming Code (Cont.)• Data is represented by the 11 non-parity bit• Example:
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Hamming Code (Cont.)• After placing the data in the table, it is in
positions 3, 6, 9, 10, 12, 14 and 15 we have a ‘1’
• Using the previous conversion table we obtain the binary representation for each of these values
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Hamming Code (Cont.)• We then exclusive OR the resulting values
(essentially setting the parity bit to 1 if an odd # of 1’s else setting it to 0
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Hamming Code (Cont.)• The parity bits are then put in the proper locations in
the table providing the following end result:
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•This is the encoded code word that would be sent. •The receiving side would re-compute the parity bits and compare them to the ones received. •If they were the same no error occurred •if they were different the location of the flipped bit is determined.
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Hamming Code (Cont.)• Assumed now bit at location 14 is flipped, 1 to 0, the
calculation for parity is as below:
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Hamming Code (Cont.)• The re-calculated parity information is then
compared to the parity information sent/received
• If they are both the same the result (again using an XOR – even parity) will be all 0’s
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Hamming Code (Cont.)• If a single bit was flipped the resulting number will
the position of the errant bit (check back into table). For example:
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