8/4/2019 Chapter 3 CMOS Class
1/48
1
CMOSDigital Integrated
CircuitsAnalysis and Design
Chapter 3
MOS Transistor
8/4/2019 Chapter 3 CMOS Class
2/48
2
The Metal Oxide Semiconductor (MOS) structure
The structure consists of threelayer The metal gate electrode The insulating oxide (SiO2)
layer
The p-type bulksemiconductor
The basic properties of thesemiconductor
Ap
A
in
A
i
Np,N
neconcptronandholibriumelecthen equil
n Nncentratiodoping cosubstrateAssume the
npnction law:The mass a
0
2
0
2
n=mobile carrier concentration of electronP=mobile carrier concentration of hole
8/4/2019 Chapter 3 CMOS Class
3/48
3
Energy band diagram of a p-type silicon substrate
)-E(Eqq
k functioned the worce is callo free spalFermi leve
heove f rom tctron to mfor an elerequiredThe energy
n
N
q
kTductor, pe semiconFor a n-ty
Nn
qkTductor, pe semiconFor a p-ty
q
-EEpotentialThe Fermi
Fcs
i
DFn
A
iFp
iFF
int
ln
ln Electron affinity of silicon is the potentialDifference between the conduction bandLevel and the vacuum level and is given byqx.
8/4/2019 Chapter 3 CMOS Class
4/48
4
Energy diagram of the combined MOS system
The equilibrium Fermi levels of the semiconductor (Si) substrate
and the metal gate are at the same potential The bulk Fermi level is not significantly affected by the bending
The surface Fermi level moves closer to the intrinsic Fermi level
8/4/2019 Chapter 3 CMOS Class
5/48
5
Example 1
8/4/2019 Chapter 3 CMOS Class
6/48
6
The MOS System under External Bias - accumulation
A negative voltage VG is applied to the gate electrode. The holes in the p-type substrate are attracted to the semiconductor-
oxide surface
The majority carrier concentration > the equilibrium hole concentration The electron concentration (minority carrier) decreases as the negatively
charged electron are pushed deeper into the substrate
The oxide electric field is directed towards the gate electrode
Causing the energy bands bend up-ward near the surface
8/4/2019 Chapter 3 CMOS Class
7/48
7
The MOS System under External Bias depletion
A small positive gate bias VG is applied to the gateelectrode The oxide electric field will be directed towards the substrate Causing the energy bands to bend downward near the surface
The majority carrier (hole) will be repelled back into the substrate
Leaving negatively charged fixed acceptor ions behind (depletionregion)
FsSiAdA
A
FsSi
d
Si
dAFs
x
Si
As
Si
A
Si
s
A
NqxNqQ
Nqx
xNq
dxxNq
d
dxxNqdQ
xd
dxNqdQ
s
F
d
2
2
2
0
8/4/2019 Chapter 3 CMOS Class
8/48
8
FsSiAdA
A
FsSi
d
Si
dAFs
x
Si
As
Si
A
Si
s
A
NqxNqQ
Nqx
xNq
dxxNq
d
dxxNqdQ
xd
dxNqdQ
s
F
d
2
2
2
2
0
Assume that the mobile hole charge in a thin horizontal layer parallel tothe surface is
The change in surfacepotentialRequired to displace thischarge sheet dQ by a distancexd away from the surface canbe found by using Poissonequation
Integrating along the vertical dimensiongives
Thus, the depth of the depletion regionis
And the depletion region chargedensity is given by
8/4/2019 Chapter 3 CMOS Class
9/48
9
The MOS System under External Bias inversion
A further increase in the positive gate bias Increasing surface potentialthe downward bending of the energy bands will increase
The mid-gap energy level Ei becomes smaller than the Fermi level EFp on the surface
The substrate semiconductor in this region become n-type The electron density is larger than the majority hole density Inversion layer, surface inversion Can be utilized for conducting current between two terminal of the MOS transistor
The surface is said to be inverted The density of mobile electrons on the surface becomes equal to the density of holes in the bulk
substrate Requiring the surface potential has the same magnitude, but the reverse polarity, as the bulk Fermi
potential F
Further increase gate voltage electron concentration but not to an increase of the depletiondepth
A
FSi
dmNq
x
22
8/4/2019 Chapter 3 CMOS Class
10/48
10
The physical structure of a n-channelenhancement-type MOSFET
MOS structure polysilicon gate, thin oxide layer, semiconductor
Source, drain n+
-region The current conducting terminals of the device Conducting channel, channel length L, channel width W
The device structure is completely symmetrical with respect to the drain and source
The simple operation of this device Controlling the current conduction between the source and the drain, using the electric field
generated by the gate voltage as a control variable
8/4/2019 Chapter 3 CMOS Class
11/48
11
Circuit symbols for enhancement-type MOSFET
Enhancement-mode MOSFET No conducting region at zero gate bias
Depletion-mode MOSFET A conducting channel already exists at zero gate bias
The abbreviations used for device terminals are G for the gate, D for the drain, S for the source, and B for the substrate
The small arrow always marks the source terminal
8/4/2019 Chapter 3 CMOS Class
12/48
12
Formation of a depletion region
For small gate voltage level
The majority carriers (holes) are repelled back intothe substrate
The surface of the p-type substrate is depleted
Current conduction between S and D is not possible
8/4/2019 Chapter 3 CMOS Class
13/48
13
Formation of an inversion layer
As the gate-to-source voltage is further increased The surface potential reaches -Fp surface inversion will be established conducting
channel between S and D
Allowing current flow, as log as there is a potential difference between S and D
VGSVT0 (threshold voltage) Electrons are attracted to the surface
Contributing to channel current conduction
Further increase gate voltage Not affect the surface potential and the depletion region depth
8/4/2019 Chapter 3 CMOS Class
14/48
14
The threshold voltage
Four physical components of VT0 The work function difference between
gate and the channel
GC= F(substrate)- M for metal gate GC= F(substrate)- F(gate) forpolysilicon gate
The gate voltage component to changethe surface potential(to achieve surfaceinversion) .To change the surface potentialby -2F
The gate voltage component to offsetthe depletion region charge
-QB/Cox
The voltage component to offset thefixed charge in the gate oxide and inthe silicon-oxide interface(due toimpurities and/or lattice imperfections
at the interface) -Qox/Cox
Compared with the p-MOSFET The substrate Fermi potential F is
negative in NMOS, positive in pMOS
The depletion region charge densitiesQB0 and QB are negative in nMOS,positive in pMOS
The substrate bias coefficient ispositive in nMOS, negative in pMOS
The substrate bias voltage VSB ispositive in nMOS, negative in pMOS
Threshold voltage adjustment For n-channel MOS
Implanting p-type impurity VTincreased
Implanting n-type impurity VTdecreased
The amount of change in thethreshold voltage as a result ofextra implant
qNI/Cox where Ni is thedensity of implantedimpurities
ox
oxox
SBFSiAB
tC
VNqQ
22
tcoefficieneffectbodybiassubstrate
C
Nq
VVV
C
Q
C
QV
ox
SiA
FSBFTT
ox
ox
ox
BFGCT
)(
2ewher
effect)body(with22
effect)body(no2
0
00
The depletion region chargeDensity is given as
8/4/2019 Chapter 3 CMOS Class
15/48
15
Example 2
8/4/2019 Chapter 3 CMOS Class
16/48
16
Circuit symbols for n-channel depletion-type MOSFETs
Using selective ion implantation into the channel
The threshold voltage for nMOSFET can be madenegative
Having a conducting channel at VGS=0
8/4/2019 Chapter 3 CMOS Class
17/48
17
Example 3
8/4/2019 Chapter 3 CMOS Class
18/48
18
MOSFET operation: linear region
The MOSFET consists A MOS capacitor, two pn junction adjacent to the channel
The channel is controlled to the MOS gate
The carrier (electron in nMOSFET) Entering through source, controlling by gate, leaving through drain
To ensure that both p-n junctions are reverse-biased initially The substrate potential is kept lower than the other three terminal potentials
When 00 and small ID proportional to VDS Flowing from S to D through the conducting channel
The channel act as a voltage controlled resistor
The electron velocity much lower than the drift velocity limit
As VDSthe inversion layer charge and the channel depth at the drain end start todecrease
8/4/2019 Chapter 3 CMOS Class
19/48
19
MOSFET operation: saturation region
For VDS=VDSAT The inversion charge at the drain is
reduced to zero Pinch offpoint
For VDS>VDSAT A depleted surface region forms adjacent
to the drain
As further increases VDS
this depletionregion grows toward the source
The channel-end voltage remainsessentially constant and equal to VDSAT
The pinch-off (depleted) section Absorbs most of the excess voltage drop,
VDS
-VDSAT
A high-field region forms between thechannel-end and the drain boundary
Accelerating electrons, usually reachingthe drift velocity limit
8/4/2019 Chapter 3 CMOS Class
20/48
20
MOSFET current-voltage characteristics-gradualchannel approximation (GCA)(1) Considering linear mode operation
VS=VB=0, the VGS and VDS are the external parameters controlling the draincurrent ID
VGS > VT0 (assume constant through the channel) to create a conducting inversion layer Defining
X-direction: perpendicular to the surface, pointing down into the substrate
Y-direction: parallel to the surface The y=0 is at the source end of the channel Channel voltage with respect to the source, Vc(y)
Assume the electric field Ey is dominantcompared with Ex
This assumption reduced
the current flow in the channel to the y-direction only Let QI(y) be the total mobile electron charge in the surface inversion layer
QI(y)=-Cox[VGS-Vc(y)-VT0]
8/4/2019 Chapter 3 CMOS Class
21/48
21
MOSFET current-voltage characteristics-gradualchannel approximation (GCA)(2)
L
Wkwhere kVVVV
kI
Cwhere kVVVVL
WkI
VVVVL
WCI
dVVVVCWLI
dVyQWdyI
dy(y)QW
I-dRIdV
yisdropalongdThevoltage
Q(y)QW
dydR
cesislincrementa
The
'
DSDSTGSD
oxn
'
DSDSTGSD
DSDSTGSoxn
D
V
CTCGSoxnD
V
CI
L
D
In
DDC
n
I
In
n
DS
DS
2
0
2
0
'
20
00
0n
0
22
22
22
)(
mobilityelectronbulktheofthatofhalf-oneabouttypicallyismagnitudeitsand
region,channeltheofionconcentratdopingon thedependentsmobilitysurfaceelectronThe
)chargelayerinversiontheofpolaritynegativethetodueissign(mimus
tanRe
mobilitysurfacrconstantahaslayerinversionin theelectronsmobileallthatAssumeing
8/4/2019 Chapter 3 CMOS Class
22/48
22
Example 4
8/4/2019 Chapter 3 CMOS Class
23/48
23
MOSFET current-voltage characteristics-gradualchannel approximation (GCA)-saturation region
For VDSVDSAT=VGS-VT0
The drain current becomes a function only of VGS, beyond the saturationboundary
20
2
000)(
2
2
2
TGSoxn
TGSTGSTGS
oxn
satD
VVL
WC
VVVVVV
L
WCI
8/4/2019 Chapter 3 CMOS Class
24/48
24
Channel length modulation
DSTGS
oxnD(sat)
DS
DS
DSATDS
TGS'
oxnD(sat)
TGS'
oxnD(sat)
I
'
I
TGSDSATDS
DSTGSoxI
TGSoxI
VVVL
WCI
, VLL
VVL
VVL
WC
L
LI
VVLWCI
Qw
L--L
L)(yQ
-VVV, V
V-VV-CL)(yQ
-VV-C)(yQ
12
1thatAssuming
tcoefficienmodulationlengthchannel11useWe
21
1
2
0thsegment wichanneltheoflengththeisLhere
lengthchanneleffectiveThe
0
smallverybecomeenddrainat thechargelayerinversionThe
saturationofedgeat thethatNote
ischanneltheofenddrainat thechargelayerinversiontheand
0
ischanneltheofendsourceat thechargelayerinversionThe
2
0
2
0
20
0
0
0
8/4/2019 Chapter 3 CMOS Class
25/48
25
Substrate bias effect
The discussion in the previous has been done under the assumption The substrate potential is equal to the source potential, i.e. VSB=0
On the other hand the source potential of an nMOS transistor can be larger than the substrate
potential, i.e. VSB>0
DSSBTGSoxn
satD
DSDSSBTGSoxn
linD
FSBFTSBT
VVVVL
WCI
VVVVVL
WCI
VVVV
1)(2
)(22
22)(
2
)(
2
)(
0
8/4/2019 Chapter 3 CMOS Class
26/48
26
Current-voltage equation of n-, p-channel MOSFET
TGSDS
TGSDSTGS
oxp
satD
TGSDS
TGSDSDSTGS
oxp
linD
TGSD
TGSDS
TGSDSTGS
oxn
satD
TGSDS
TGSDSDSTGSoxn
linD
TGSD
-VVV
VVVVVL
WCI
-VVV
VVVVVV
L
WCI
VVI
-VVV
VVVVVL
WCI
-VVV
VVVVVVL
WCI
VVI
and
for12
and
for2
2
for,0
MOSFETchannel-pFor
and
for12
and
for22
for,0
MOSFETchannel-nFor
2
)(
2
)(
2
)(
2
)(
8/4/2019 Chapter 3 CMOS Class
27/48
27
Measurement of parameters- kn, VT0, and The VSB is set at a constant value
The drain current is measured for different values of VGS
VDG=0 VDS>VGS-VT is always satisfied saturation mode
Neglecting the channel length modulation effect
Obtaining the parameters kn, VT0, and
0
2
0)(2
,2
TGS
n
DTGS
n
satDVV
kIVV
kI
FSBF
TSBT
V
VVV
22
)( 0
8/4/2019 Chapter 3 CMOS Class
28/48
28
Measurement of parameters- The voltage VGS is set to VT0+1
The voltage VDS is chosen sufficiently large (VDS>VGS-VT0) that the transistoroperates in the saturation mode, VDS1,VDS2 ID(sat)-(kn/2)(VGS-VT0)2(1+VDS)
Since VGS=VT0+1ID2/ID1=(1+VDS2)/ (1+VDS1) Which can be used to calculate the channel length modulation coefficient This is in fact equivalent to calculating the slope of the drain current versus drain
voltage curve in the saturation region The slope is kn/2
8/4/2019 Chapter 3 CMOS Class
29/48
29
Example 5
8/4/2019 Chapter 3 CMOS Class
30/48
30
MOSFET scaling and small-geometry effects
High density chip The sizes of the transistors are as small as possible
The operational characteristics of MOS transistor will change with the reduction of iys
dimensions There are two basic types of size-reduction strategies
Full scaling (constant-field scaling) Constant-voltage scaling
A new generation of manufacturing technology replaces the previous one about every two or three years
The down-scaling factor S about 1.2 to1.5
The scaling of all dimensions by a factor of S>1 leads to the reduction of the areaoccupied by the transistor by a factor of S2
8/4/2019 Chapter 3 CMOS Class
31/48
31
Full scaling (constant-field scaling)
sresistanceabdescapacitancparasiticvariousofreductionA
improveddown time-chargeandup,-chargetheoffactorabydownscaledis
unchangedvirtuallyremainingareaunitperThe
scalingfulloffeaturesattractivemosttheofoneisndissipatiopowertheofreductiontsignificanThe
1
ndissipatiopowerThe
1
22
currentdrainmodesaturationThe
21
2
22
currentdrainmodelinearThe
offactorabyscaledalsowilltheunchangedratioaspectThe
C
areaunitperecapacitancoxidegateThe
densitydopingscaledby theaffectedtlysignificannotismobilitysurfacetheAssuming
factorscalingsameby theally,proportiondownscaledbemustpotentialsallgoal,thisachieveTo
22
2
2
2
2
2
2
''ox
SC
itypower dens
S
PVI
S
VIP
S
IVV
S
kSVV
k(sat)I
S
I
VVVVS
kS
VVVVk
(lin)I
SkW/L
CSt
St
g
DSD
'
DS
'
D
'
D(sat)
TGSn'
T
'
GS
'
n'
D
D(lin)
DSDSTGS
n
'
DS
'
DS
'
T
'
GS
'
n'
D
n
ox
ox
ox
ox
ox
n
8/4/2019 Chapter 3 CMOS Class
32/48
32
Constant-voltage scaling
stress-overelectricalandbreakdown,oxiden,degradatiocarrierhotration,electromig
densitypowerdensity,currentincreasingDisadv.
s.constraintlevel-voltageexternaltheofbecause
casespracticalmamyinscalingfulloverpreferredbemayscalingvoltage-constant,summarizedTo
offactorabyincresaeddensitypowerThe
ndissipatiopowerThe
offactorabyincreaseddensitycurrentdrainThe
22
currentdrainmodesaturationThe
22
22
currentdrainmodelinearThe
byincreasedalsoisparameteructancetranscondThe
offactorabyincreasedisareaunitperecapacitancoxidegateThe
relationsfield-chargethepreserveorder toinoffactorabyincreasedbemustdensitiesdopingThe
unchanged.remainedvoltagesterminaltheandtagesupply volpowerThe
.offactorabyreducedMOSFETaretheofdimensionsAll
3
3
22
2
2
2
S
PSV)I(SVIP
S
(sat)ISVVkS
VVk
(sat)I
(lin)ISVVVVkS
VVVVk
(lin)I
S
SC
S
S
DSD'
DS'
D'
DTGSn'
T
'
GS
'
n'
D
DDSDSTGS
n
'
DS
'
DS
'
T
'
GS
'
n'
D
ox
8/4/2019 Chapter 3 CMOS Class
33/48
33
Short-channel effects
A MOS transistor is called a short-channel device If its channel length is on the same order of magnitude as the
depletion region thickness of the Sand Djunction The effective channel length LeffS, Djunction depth xj Two physical phenomena arise from short-channel effects
The limitations imposed on electron drift characteristics in thechannel
The lateral electric field Ey increased, vdreached saturation velocity
No longer a quadratic function of VGS, virtually independent of thechannel length
The carrier velocity in the channel also a function of Ex Influence the scattering of carriers in the surface
The modification of the threshold voltage due to the shorteningchannel length
DSAToxsatd
L
IsatdsatdsatD VCvWQvWdxxnqvWIeff
)(
0)()()( )(
TGSno
cGS
Siox
ox
nonon
VVyVVt
Ex
eff
1)(11
)(
8/4/2019 Chapter 3 CMOS Class
34/48
34
Short-channel effects-modification of VT The n+ drain and source diffusion regions in p-type substrate induce a
significant amount of depletion charge The long channel VT, overetimates the depletion charge support by the gate
voltage The bulk depletion region asymmetric trapezoidal shape
A significant portion of the total depletion region charge is due the S and D junctiondepletion
12
112
12
221
12
1
12
12
022
ln22
222
1
V-V
0
222
222
222
2000
0
T0T00
j
dS
j
dDj
FASi
ox
T
j
dS
jS
j
dDjdDjdDdmjjD
dDjdDdmDjD
DjdmdDj
i
ADDS
A
Si
dD
A
Si
dS
FASi
DS
B
T
x
x
x
x
L
xNq
CV
x
xxL
x
xxxxxxxxL
xxxxLxL
Lxxxx
n
NN
q
kT, VNq
, xNq
x
NqL
LLQ
nnel)(short chaV
8/4/2019 Chapter 3 CMOS Class
35/48
8/4/2019 Chapter 3 CMOS Class
36/48
36
Example 6 (1)
8/4/2019 Chapter 3 CMOS Class
37/48
37
Example 6 (2)
8/4/2019 Chapter 3 CMOS Class
38/48
38
Example 6 (3)
8/4/2019 Chapter 3 CMOS Class
39/48
39
Narrow-channel effect
Channel width W on the sameorder of magnitude as the
maximum depletion regionthickness xdm The actual threshold voltage of
such device is larger than thatpredicted by the conventionalthreshold voltage
Fringe depletion region underfield oxide
arcscircular-quarterbymodeledregiondepletionfor2
221
V
VVchannel)narrow(
T0
T0T00
W
xNq
C
V
dm
FASi
ox
T
8/4/2019 Chapter 3 CMOS Class
40/48
40
Other limitations imposed by small-device geometries
The current flow in the channel are controlled by two dimensional electric field vector Subthreshold conduction
Drain-induced barrier lowering (DIBL)
A nonzero drain current ID for VGS
8/4/2019 Chapter 3 CMOS Class
41/48
41
MOSFET capacitances
L=LM-2LD L: the actual channel length L
M
: the mask length of thegate
LD: the gate-drain, the gate-source overlap
On the order of 0.1m
8/4/2019 Chapter 3 CMOS Class
42/48
42
Oxide related capacitance(1)
The gate electrode overlapcapacitance
CGD(overlap)=CoxWLD CGS(overlap)=CoxWLD
With Cox=ox/tox
Both capacitance do not dependon the bias condition, they arevoltage-independent
The capacitances result from theinteraction between the gatevoltage and the channel charge
Cut-off mode
Cgs=Cgd=0
Cgb=CoxWL
Linear mode
Cgb=0
CgsCgd(1/2) CoxWL
Saturation mode
Cgb= Cgd =0
Cgs
(2/3) C
oxWL
8/4/2019 Chapter 3 CMOS Class
43/48
43
Oxide related capacitance(2)
The sum of all three voltage-dependent (distributed) gate oxidecapacitances (Cgb+Cgs+Cgd) A minimum value of 0.66CoxWL, in saturation mode
A maximum value of CoxWL, in cut off and linear modes For simple hand calculation
The three capacitances can be considered to be in parallel A constant worst-case value of CoxW(L+2LD) can be used for the sum of
MOSFET gate oxide capacitances
8/4/2019 Chapter 3 CMOS Class
44/48
44
Junction capacitance(1)
102012
0
0
0
1
0
2
2
00
1
0
1
1
0
2
2
00
1212
12
0
0
0
0
0
0
20
0
2
112
junctions-pnabruptofcasespecialFor the
111
1
asdefinedbecanecapacitancsignal-largeequivalentThe
1
2areaunitperecapacitancjunctionbiaszeroThe
tcoefficiengradingismparameterthe,
1
1
2ecapacitancjunctionThe
2chargeregiondepletionThe
lnpotentialin-builtThe
2cknessregion thidepletionThe
2
1
VVVV
K
KCAC
VV
VV
CAC
VVmVV
CA
(V)dVCVVVV
)(VQ)(VQ
V
QC
NN
NNqC
V
AC(V)C
VNN
NNqA
dV
dQC
VNN
NNqAx
NN
NNqAQ
n
NN
q
kT
VNN
NN
q
x
eq
eqjeq
j
eq
mm
j
V
Vj
jj
eq
DA
DASij
m
j
j
DA
DASij
j
DA
DASid
DA
DAj
i
DA
DA
DASid
8/4/2019 Chapter 3 CMOS Class
45/48
45
Example 7
8/4/2019 Chapter 3 CMOS Class
46/48
46
Junction capacitance(2)
eq(sw)jsweq(sw)
eq(sw)
swsw
sw
sweq
jswjjsw
swDA(sw)
DA(sw)Si
swj
A(sw)
A
KCPC
P
C
VVVV
K
xCC
NN
NNq
C
N
N
p
becan)(perimeterlengthofsidewalla
forecapacitancjunctionsignal-largeequivalentThe
2
factoreequivalencvoltagesidewallThe
1
2
asfoundbecanareaunitperecapacitancbias-zerothe
,bygivenisdensitydopingsidewalltheAssume
densitydopingsubstratethan the
densitydopinghigherawithimplant,stop-channelabysurroundedare
regiondiffusiondrainorsourceMOSFETtypicalaofsidewallsThe
102012
0
)(
0
00
8/4/2019 Chapter 3 CMOS Class
47/48
47
Example 8 (1)
8/4/2019 Chapter 3 CMOS Class
48/48
48
Example 8 (2)
Top Related