Computer System Architecture© Korea Univ. of Tech. & Edu.
Dept. of Info. & Comm.Chap. 12 Memory Organization
12-1Chap. 12 Memory Organization
12-1 Memory Hierarchy Memory hierarchy in a computer system : Fig. 12-1
Main Memory : memory unit that communicates directly with the CPU (RAM) Auxiliary Memory : device that provide backup storage (Disk Drives) Cache Memory : special very-high-speed memory to increase the processing
speed (Cache RAM)
Multiprogramming enable the CPU to process a number of independent program concurrently
Memory Management System : sec. 12-7 supervise the flow of information between auxiliary memory and main memory
Magnetictapes
Magneticdisks
I/O processor
CPU
Mainmemory
Cachememory
Auxiliary memory
Computer System Architecture© Korea Univ. of Tech. & Edu.
Dept. of Info. & Comm.Chap. 12 Memory Organization
12-2
12-2 Main Memory Bootstrap Loader
A program whose function is to start the computer software operating when power is turned on
RAM and ROM Chips Typical RAM chip : Fig. 12-2
» 128 X 8 RAM : 27 = 128 (7 bit address lines)
Typical ROM chip : Fig. 12-3» 512 X 8 ROM : 29 = 512 (9 bit address lines)
×
128×8RAM
CS1
AD7
WR
RD
CS2
Chip select 1
Chip select 2
Read
Write
7 bit address
8 bit data bus
(a) Block diagram
CS1 WRRDCS2 Memory function State of data bus
0
×
×
×
0
0 0
0 0
01 1
1
1
1
1
×
0
×
×
0
1
1
Inhibit
Inhibit
Inhibit
Write
Read
Inhibit
High-impedance
High-impedance
High-impedance
Input data to RAM
Output data from RAM
High-impedance
(b) Function table
512×8ROM
CS1
AD9
CS2
Chip select 1
Chip select 2
9 bit address
8 bit data bus
Power-ON
FFFF:0000(Reset Point)
POST
System Init.
INT 19
Load Bootstrap Record(Track 0, Sector 0)
Load Operating System(IO.SYS, MSDOS.SYS, COMMAND.COM)
Bootstrap LoaderBootstrap ROMBoot ROM
Computer System Architecture© Korea Univ. of Tech. & Edu.
Dept. of Info. & Comm.Chap. 12 Memory Organization
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Memory Address Map Memory Configuration :
» 512 bytes RAM + 512 bytes ROM
» 1 x 512 byte ROM + 4 x 128 bytes RAM
Memory Address Map : Tab. 12-1» Address line 9 8
RAM 1 0 0 : 0000 - 007F
RAM 2 0 1 : 0080 - 00FF
RAM 3 1 0 : 0100 - 017F
RAM 4 1 1 : 0180 - 01FF
» Address line 10 ROM 1 : 0200 - 03FF
Memory Connection to CPU : Fig. 12-4» 2 x 4 Decoder : RAM select (CS1)
» Address line 10 RAM select : CS2
ROM select : CS2 의 Invert
» 참고
RD : ROM 의 CS1은 보통
OE(Output Enable)로 사용
128×8RAM 1
CS1
AD7
WR
RD
CS2
128×8RAM 2
CS1
AD7
WR
RD
CS2
128×8RAM 4
CS1
AD7
WR
RD
CS2
128×8RAM 3
CS1
AD7
WR
RD
CS2
128×8ROM
CS1
CS2
AD9
Data
Data
Data
Data
Data
CPU
WRRD16 - 11 10 9 8 7 - 1
Address bus
Data bus
Decoder
3 2 1 0
1-7
8
9
Computer System Architecture© Korea Univ. of Tech. & Edu.
Dept. of Info. & Comm.Chap. 12 Memory Organization
12-4
12-3 Auxiliary Memory Magnetic Disk : Fig. 12-5, FDD, HDD
Magnetic Tape : Backup or Program 저장
Optical Disk : CDR, ODD, DVD
12-4 Associative Memory Content Addressable Memory (CAM)
A memory unit accessed by content
Block Diagram : Fig. 12-6
texttexttexttext
Secto
r
Read/Writehead
Tracks
A Register 101 111100K Register 111 000000
Word 1 100 111100 M = 0Word 2 101 000011 M = 1
Argument register (A)
Key register (K)
Associative memoryarray and logic
m words n bits per word
M
Matchregister
Input
Write
Read
Output
성명 학번
Argument
Key (Mask)
Match Logic
Memory 내용
M = 1 일때 출력
Computer System Architecture© Korea Univ. of Tech. & Edu.
Dept. of Info. & Comm.Chap. 12 Memory Organization
12-5
m word x n cells per word : Fig. 12-7
Match Logic One cell of associative memory : Fig. 12-8
» Input = 1 or 0 에 따라 Write 신호와 동시에 F/F에 저장
» A 와 K 에 의해 Match Logic 에서 M=1 이면 (M을 READ에 직접 연결 가능함)
» Read 신호에 따라 F/F에서 데이터를 읽는다
A1
C11
AnA j
K1 KnK j
C 1j C1n
C i1 C ij C in
Cm1 Cmj Cmn
M1
Mm
M i
Bit 1 Bit nBit j
Word 1
Word m
Word i
R S Matchlogic
Input
Read
Write
Output
To M i
K jA i
F ij
Computer System Architecture© Korea Univ. of Tech. & Edu.
Dept. of Info. & Comm.Chap. 12 Memory Organization
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Match Logic : Fig. 12-9» Aj = Argument, Fij = Cell ij 번째 bit
» j 번째 1 bit match 조건
xj = Aj Fij (1 AND 1)+ Aj’ Fij’ (0 AND 0)
» 1 - n 까지 n bits match 조건 Mi = x1x2…..xn
» Key bit Kj : xj + Kj’ Kj = 0 : Aj 와 Fij 는 no comparison ( Kj : xj + 1 = 1 )
Kj = 1 : Aj 와 Fij 는 comparison ( Kj : xj + 0 = xj )
» Match Logic for word I :
Mi = (x1 + K1’) (x2 + K2’)…. (xn + Kn’)
= (xj + Kj’)
= (Aj Fij + Aj’ Fij’ + Kj’)
n
j 1
n
j 1
F'i1 Fi1
A 1K1
F'i2 Fi2
A 2K 2
F'in Fin
A nKn
M i
Computer System Architecture© Korea Univ. of Tech. & Edu.
Dept. of Info. & Comm.Chap. 12 Memory Organization
12-7
12-5 Cache Memory Locality of Reference
the references to memory tend to be confined within a few localized areas in memory
Cache Memory : a fast small memory keeping the most frequently accessed instructions and data in the fast cache
memory
Cache 의 설계 요소 cache size : 보통 256 K byte (최대 512 K byte) mapping method : 1) associative, 2) direct, 3) set-associative replace algorithm : 1) LRU, 2) LFU, 3) FIFO write policy : 1) write-through, 2) write-back
Hit Ratio the ratio of the number of hits divided by the total CPU references (hits + misses)
to memory» hit : the CPU finds the word in the cache (보통 0.9 이상)» miss : the word is not found in cache (CPU must read main memory)
예제 : cache memory access time = 100 ns, main memory access time = 1000 ns, hit ratio = 0.9
» 1 회 miss : 1 x 1000 ns» 9 회 hit : 9 x 100 ns
총 10 회Memory 참조
1900 ns / 10 회 = 190 nsCache가 없으면 1000 ns,따라서 약 5 배 성능 향상
Computer System Architecture© Korea Univ. of Tech. & Edu.
Dept. of Info. & Comm.Chap. 12 Memory Organization
12-8
Mapping The transformation of data from main memory to cache memory
» 1) Associative mapping
» 2) Direct mapping
» 3) Set-associative mapping
Example of cache memory : Fig. 12-10
main memory : 32 K x 12 bit word (15 bit address lines)
cache memory : 512 x 12 bit word» CPU sends a 15-bit address to cache
Hit : CPU accepts the 12-bit data from cache
Miss : CPU reads the data from main memory (then data is written to cache)
Associative mapping : Fig. 12-11
Cache memory로 고가의 associative memory 사용
Address 와 Data 가 직접 Cache memory에 사용됨
Direct mapping : Fig. 12-12
Cache memory로 저가의 일반 memory 사용
Tag field (n - k) 와 Index field (k)를 사용
» 2k words cache memory + 2n words main memory Tag = 6 bit (15 - 9), Index = 9 bit
Cache Coherence (Sec. 13-5)
Main memory32K×12
CPUCache memory
512×12
Argument register
0 1 0 0 0
2 2 3 4 5
0 2 7 7 7
3 4 5 0
1 2 3 4
6 7 1 0
Address Data
CPU address(15 bits)
Computer System Architecture© Korea Univ. of Tech. & Edu.
Dept. of Info. & Comm.Chap. 12 Memory Organization
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Direct mapping cache organization : Fig. 12-13
» 예제 : 02000 번지를 읽는 경우
1) 우선 Index 000을 cache 에서 찾는다
2) 다음은 Tag를 cache에서 비교한다
3) 000 Index에 있는 cache tag는 00 이다
(02가 아니다)
4) 따라서 miss
5) 그러므로 main memory에서 data read
(address 02000 = 5670 read)
32K×12
Main memory
Address = 15 bitsData = 12 bits
Tag Index
6 bits 9 bits
HexAddress
00 000
3F 1FF
512×12Cache memory
Address = 9 bitsData = 12 bits
000
1FF
Octaladdress
1 2 2 0
2 3 4 0
3 4 5 0
4 5 6 0
5 6 7 0
6 7 1 0
Memory dataMemory address
000000
02777
02000
01777
01000
00777
00 1 2 2 0
02 6 7 1 0
Tag DataIndex
address
000
777
(a) Main memory
(b) Cache memory
Tag (6 bit)00 - 63
Index (9 bit)000 - 511
Computer System Architecture© Korea Univ. of Tech. & Edu.
Dept. of Info. & Comm.Chap. 12 Memory Organization
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Direct mapping cache with block size of 8 words : Fig. 12-14» 64 block x 8 word = 512 cache words size
8 word 를 1개의 block 단위로 update
Set-associative mapping : Fig. 12-15 (two-way) Direct mapping ( Fig. 12-13(b))에서 같은 Index에 다른 tag를 자주 읽으면 속도가
저하됨 ( 예제 02777, 01777 )
따라서 set의 개수를 증가시키면 속도가 향상된다.
000
007
010
017
0 1
0 1
770
777
0 2
0 2
3 4 5 0
6 5 7 8
6 7 1 0
Index Tag Data
Block 0
Block 1
Block 63
Tag Block Word
6 36
Index
0 1 3 4 5 0 0 2 5 6 7 0
0 2 6 7 1 0 0 0 2 3 4 0
000
777
Index Tag Data Tag Data
Computer System Architecture© Korea Univ. of Tech. & Edu.
Dept. of Info. & Comm.Chap. 12 Memory Organization
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Replacement Algorithm : cache miss or full 일때
1) LRU (Least Recently Used) : 최근에 가장 적게 사용된 block 교체
2) LFU (Least Frequently Used) : 사용 빈도가 가장 적은 block 교체
3) FIFO (First-In First-Out) : 가장 오래된 block 교체
Writing to Cache : Cache Coherence(Sec. 13-5) Cache에 있는 내용이 변경된(WRITE) 경우, Cache의 block이 교체되기 전에 main
memory에 내용도 update 해야 함
» 1) Write-through : Cache write 와 동시에 main memory도 항상 동시에 write 한다.
» 2) Write-back : Cache write 시에 내용이 변경되었다는 flag 만 set해 놓고 나중에block이 교체되기 전에 flag를 검사하여 변경된 부분만 나중에 write 한다.
따라서 Write-back 방식은 main memory가 무효한 상태에 빠져 있을 수 있다.
Cache Initialization Cache is initialized : 이때 cache 는 empty 상태이고 invalid data를 갖을 수 있다.
» 1) when power is applied to the computer
» 2) when main memory is loaded with a complete set of programs from auxiliary memory
valid bit» indicate whether or not the word contains valid data
Main memory 와 Cache memory의 내용이 동일해야 함 : 통일성(일관성) 유지
Cache READ는 문제 없음
Computer System Architecture© Korea Univ. of Tech. & Edu.
Dept. of Info. & Comm.Chap. 12 Memory Organization
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12-6 Virtual Memory Virtual Memory : Auxiliary memory Main memory
Translate program-generated (Aux. Memory) address into main memory location » Give programmers the illusion that they have a very large memory, even though the
computer actually has a relatively small main memory
예제 : Intel Pentium Processor» Physical Address Lines = A0 - A31 : 232 = 230 X 22 = 4 Giga
» Logical Address = 46 bits address : 246 = 240 X 26 = 64 Tera
Address Space & Memory Space Address Space : Virtual Address
» Address used by a programmer
Memory Space : Physical Address(Location)» Address in main memory
예제 : Fig. 12-16
address space (N) = 1024 K = 220
» Auxiliary Memory
memory space (M) = 32 K = 215
» main Memory
Program 1
Data 1,1
Data 1,2
Program 2
Data 2,1
Program 1
Data 1,1
Auxiliary memory
Main memory
Address space
N = 1024K =
Memory space
M = 32K = 215
220
Computer System Architecture© Korea Univ. of Tech. & Edu.
Dept. of Info. & Comm.Chap. 12 Memory Organization
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Memory table for mapping a virtual address : Fig. 12-17
Translate the 20 bits Virtual address into the 15 bits Physical address
Address Mapping Using Pages : Fig. 12-18
Address mapping 을 간단하게 하기 위하여 사용
» Address space와 memory space를 fixed size로
분할하여 사용함
Address space : 1 K page 로 분할
Memory space : 1 k block으로 분할
» Address space의 4 개 page가 memory space에
block에 들어 갈수 있다.
Virtualaddressregister(20 bits)
Memorymapingtable
Memory tablebuffer register
Main memoryaddressregister(15 bits)
Mainmemory
Main memory buffer register
Virtual address
Page 0
Page 7
Page 6
Page 5
Page 4
Page 3
Page 2
Page 1
Block 0
Block 3
Block 2
Block 1
Address space
N = 8K = 213
Memory space
M = 4K = 212
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Dept. of Info. & Comm.Chap. 12 Memory Organization
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Memory table in a paged system : Fig. 12-19 Virtual address → Memory address
1 0 1 0 1 0 1 0 1 0 0 1 1
0
00
11
10
01
1
0
1
10
1
1
10
01 1
000
111
110
101
100
011
010
001
Tableaddress
Presencebit
Page no.Line number
Virtual address
01 0101010011
Block 0
Block 1
Block 2
Block 3
MBR
Main memory address register
Memory page table
Main memory
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Dept. of Info. & Comm.Chap. 12 Memory Organization
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Associative memory page table : Fig. 12-20
Associative memory를 이용하여 block number(01)를 곧바로 찾는다
Page(Block) Replacement Page Fault : the page referenced by the CPU is not in main memory
» a new page should be transferred from auxiliary memory to main memory
Replacement algorithm : FIFO 와 LRU 주로 사용
1 0 1 Line number
1 1 1 0 0
0 0 1 1 1
1 1 0 1 0
1 0 1 0 1
0 1 0 0 0
Argument register
Key register
Associative memory
Page no.
Page no. Block no.
Virtual memory
Computer System Architecture© Korea Univ. of Tech. & Edu.
Dept. of Info. & Comm.Chap. 12 Memory Organization
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12-7 Memory Management Hardware Basic components of a Memory Management Unit
1) Address mapping
2) Common program sharing
3) Program protection
MMU : OS 에서 지원 해야 함
1) CPU에 내장된 형태, 2) 별도의 memory controller 형태
Segment : CS, DS, SS
A set of logically related instruction or data elements associated with a given name
View memory as a collection of variable-sized segments, and Eliminate internal fragmentation
예제 : a subroutine, an array of data, a table of symbol, user’s program, stack
Logical Address the address generated by a segmented program
similar to virtual address» Virtual Address : fixed-length page
» Logical Address : variable-length segment
segment
Base address
Length
Computer System Architecture© Korea Univ. of Tech. & Edu.
Dept. of Info. & Comm.Chap. 12 Memory Organization
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Paging vs. Segmentation
* Paging
No separate protection
No shared code
Fixed size
* Segmentation
Separate protection
Shared code
Variable size
Multi-segment Model
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Dept. of Info. & Comm.Chap. 12 Memory Organization
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Segmented-page MMU Pure segmentation or paging is not very popular and not being used in many of the
operating systems.
However, Segmentation can be combined with Paging to get the best features out of both the techniques.
» Segment is good logical unit of information : Sharing, Protection
» Page is good physical unit of information : Simple memory management
One way of specifying the length of a segment is by associating with it a number of equal-size pages.
Combining Segmentation and Paging : Segmented-page MMU
Logical address is partitioned into three fields : Segment, Page, Word Fig. 12-21(a)» Segment field specifies a segment number
» Page field specifies the page within the segment
» Word filed gives the specific word within the page12 bit block : 4096 blocks
Fig. 12-21(a) : 2 개의 table(segment, page)을 사용함
» 따라서 2 개의 table을 읽는데 많은 시간이 소모됨
Fig. 12-21(b) : Associative memory를 이용한 1 개의 table을 사용함
» 따라서 속도가 빠르다
» TLB (Translation Look-a-side Buffer) associative memory를 이용한 most recently reference table
Computer System Architecture© Korea Univ. of Tech. & Edu.
Dept. of Info. & Comm.Chap. 12 Memory Organization
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Numerical Example 예제 : Logical address & Physical address (Fig. 12-22)
» Logical Address : 4 bit segment : 16 segments
8 bit page : 256 pages
8 bit word : 256 address field
» Physical Address : 12 bit block : 4096 blocks
8 bit word : 256 address field
» The smallest possible segment
will have one page (256 words)
» The largest possible segment
will have 256 pages (256 x 256 =
64K)
Consider a program loaded into memory that requires 5 pages
The operating system may assign to this program segment 6 and pages 0 ~ 4 : Fig. 12-23(a) ( total logical address range for the program – 60000 to 604FF )
The operating system finds empty spaces (5 blocks in physical memory : 012, 000, 019, 053, A61) when the program is loaded into physical memory : Fig. 12-23(b)
(a) Logical address format : 16 segments of 256 pages each,each page has 256 words
× 32Physical memory
220
Block Word
12 8
(b) Physical address format : 4096 blocks of 256 word each,each word has 32 bits
Segment Page Word
4 8 8
Addressor Index
Fig. 12-22 An example of logical and physical address
Computer System Architecture© Korea Univ. of Tech. & Edu.
Dept. of Info. & Comm.Chap. 12 Memory Organization
12-20
Page 0
Page 4
Page 3
Page 2
Page 1
Page number
6 00 006 00 FF
Hexadecimaladdress
Segment Page Block
6
6
6
6
6
00
04
03
02
01
012
A61
053
019
000
(a) Logical address assignment (b) Segment-page versus memory block assignment
6 01 006 01 FF
6 02 006 02 FF
6 03 006 03 FF
6 04 006 04 FF
예제 : Logical [6027E] & Physical [0197E] address assignment (Fig. 12-23, 12-24)
Logical Address
Page Table
Block number 019 를 찾는다
Word
Segment
Page
Fig. 12-23 Example of logical and physical memory address assignment
Computer System Architecture© Korea Univ. of Tech. & Edu.
Dept. of Info. & Comm.Chap. 12 Memory Organization
12-21
35
A3
0
6
F
Segment table
012
A61
053
019
000
012
00
35
38
37
36
39
A3
Page table
Block 0
6 02 7E
Logical address (in haxadecimal)
Block 12
32 bit word
Physical memory
000 00
000 FF
012 00
012 FF
019 00
019 FF
019 7E
(a) Segment and page table mapping
6 02 019
6 04 A61
Segment Page Block
(b) Associative memory (TLB)
+
Fig. 12-21 Mapping in segmented-page memory management unit. Fig. 12-24 Logical to physical memory mapping example
+ Word+ Word = 7E
01234
0
Computer System Architecture© Korea Univ. of Tech. & Edu.
Dept. of Info. & Comm.Chap. 12 Memory Organization
12-22
Logical to Physical Memory Mapping Example : Fig. 12-24(a) 5 digits hexadecimal logical address : 6027E
The logical address refers to word number 7E of page 2 in segment 6
The base of segment 6 in the page table is at address 35
The segment 6 has associated with it 5 pages, as shown in the page table at address 35 ~ 39
The page 2 of segment 6 is at address 35 + 2 = 37
The physical memory block is found in the page table to be 019
The word 7E in block 19 gives the 20-bit physical address : 0197E
Memory Sharing : Fig. 12-24(a) Different segments can use the same block of memory if it is required to share
a program by many users
Block number 12 in physical memory can be assigned a second logical address F0000 ~ F00FF : the segment F(15) at page 0 = F 00
Block number 12 = Memory Shared
Computer System Architecture© Korea Univ. of Tech. & Edu.
Dept. of Info. & Comm.Chap. 12 Memory Organization
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Memory Protection Typical segment descriptor : Fig. 12-25
Intel segment descriptor format : DPL(Descriptor Privilege Level)
Access Rights : protecting the programs residing in memory» 1) Full read and write privileges : no protection
» 2) Read only : write protection
» 3) Execute only : program protection
» 4) System only : operating system protection
Base address Length Protection