Features and Benefits of Camera Link HS•Globallyavailable,off-the-shelfcomponentsareused.•Scaleablebandwidthsin300MB/sstepsfrom300to6000Mbytes/s,1xto20xconfigurations,whilemaintainingacommonandconsistentcontrolinterfaceandeaseofimplementation.•Camerasizeisminimized.•InterfacetechnologycanbeintegratedintoFPGAs•PoweroverCameraLinkHSispossible.•Protocolhandlesreal-timetriggering.Noneedforaseparatetriggercable.•Real-timetriggering-lowjitterof3.2nsmakesCameraLinkHSviableforlinescanapplications.•MaintainsthefeaturesofCameraLink,anindustryspecificconnectivitysolution,whileemployingbroadly-used,off-the-shelfcomponentswithdevelopmentroadmapsforincreasedperformance.Thisprotocolwillhavealongservicelife.•Lowercostdatatransmissionacrossallbandwidths.•Reliabledatatransmissionachievedthroughredundanttriggercodes,hardwareresendcapabilty,andproventechnology.HardwareresendenablesminimalbuffersizessuitableforinclusioninFPGAs,ie.noexternalmemoryrequired.•PlugandPlay-CamerasareGenICam™•GeneralPurposeI/Oareoptionalandsupportedonthecamera•Poweroptimizedasthenumberoflanesneededfordatatransmissionscalesasnecessary.Friendlytotheenvironment.•DataForwarding-Lowcostdistributedimageprocessingisaframegrabberdifferentiator.•Referencedesignsavailabletoreduceimplementationtimes.•Designedtoensurelongevityinthemarketplace.Expectedlifecycleis10-20years.•Directconversiontofiberoptic.•CameraLinkHSProtocol-exceeding95%videoefficiency.

Functional Block DiagramsTheCameraLinkHSIPCoretakesinCameraLinksignalsandprioritymanagestrigger,GPIOimagedataandconfigurationdataandsendsthisinformationtothePHY.TheIPcoreensuresguaranteeddatadeliveryandsimplifiesdesignimplementationinbothframegrabbersandcameras.Multi-vendorPHYsthatoperateon86/106,areavailablethatserializeandde-serializethedatatransmittedoverthecablemedium.Forlowbandwidthapplications(<300Mbytes/s),Infiniband(IBx1)orCoaxcablingoffersalowcostsolution.Forapplicationsupto2100Mbytes/s,asingleCX4cableisused,whichsignificantlyreducesthesizeandnumberofcablesrequiredcomparedtotoday’smachinevisionstandards,andstilldelivers15mtransmissiondistances.

Figure 1 – Functional Diagram of Camera Link HS from a Camera Perspective

Camera Link HS IP Core

Camera Link HS Overview

CameraFrontend

Camera LinkSignaling

Layer

Camera LinkHS IP Core SERDES

FVAL

LVAL

Image DATA

Serial

MediaControl

Data

CC

LocalIOs GPIO

StrobeTrigger

Interface

Ext. Trigger Handler

Error Handler

Packet Engine

Camera Link HSIP Core

Video Handler

GPIO, Ack/Nack Handler

K-Code Manager

Command

Priority Manager

128 256 512 1024 2048 4096 8192

60%

65%

70%

75%

80%

85%

90%

95%

100%

Video Packet Size

Protocol Efficiency

Increasingresolutionandfasterframerateshavecausedcamerasformachinevisionsystemstosteadilygrowintheirneedforbandwidth.ThepopularCameraLinkinterface,however,topsoutat850Mbytes/secondand10GEthernetinterfacecanonlymanage1.2Gbytes/second,evenasanincreasingnumberofcamerasbecomeavailablethatcansendmorethan1Gbyte/sectoaframegrabber.Toaddressthisshortfall,theAIAhasformedtheCameraLinkHScommitteetodevelopthenextgenerationmachinevisioncameratoframegrabberconnectionstandard.ThisdevelopmentwillreviewandimproveDALSA’sHSLINKproposalasitservesthefullrangeofcameratypesfrom300Mbytes/secondupto6Gbytes/secondwhilekeepingimplementationsimpleandcostsdown.

CameraLinkHSisdesignedspecificallytomeettheneedsofallmachinevisionapplicationsandthereforecarriesimagedata,configurationdataandlowjitter,realtimetriggeringsignalsoverasimplenetworktopologysupportingcameras,intermediatedevicesandframegrabbers.TheinterfacehastakenthekeystrengthsofCameraLink®,andaddednewfeaturesandfunctionstomeetthecustomerdemandsoftodayandtomorrow.CameraLinkHSisdesignedfromasystempointofview,ensuringtheabilitytocreatelowcostcamerasandframegrabbers,whilemeetingtheeaseofuse,flexibilityanddatareliabilitydemandedbyendcustomers.

TLK3131

Connector

FPGA

3.3

Sensor

1.5

Flash

c

c

osc

c c c

c

c c

c

3.3 2.5

1.2

Camera Link HS - not just for High SpeedCameraLinkHSisdesignedtosupportlowbandwidthcamerasaseasilyasitsupportshighbandwidthcameras.

ACameraLinkHS1xconfigurationsupportsonasinglecable:•Triggerswithmaximum3.2nsjitter•32highspeedcontrollineswithmaximum200nsjitterforframebyframewindowingortogglingofGeneralPurposeI/Olines•100MByte/scommandchanneltocamera•Poweronthecableisproposed•Videobandwidthabove300MByte/sec

Camera Link HS 1x (up to 300 MByte/s) ImplementationThediagrambelowshowsanimplementationblockdiagramfora1xconfigurationindicatingthatCameraLinkHScanbeintegratedentirelyintoanFPGAwithoutanyexternalICs.Thisensuressmallsizeandlowcostcanbeachieved.

CMOSSensor

FPGA withembeddedSERDES

FPGA withembeddedSERDES

PCIeConnector Connector

I/O(optional) I/O

Proposed CableHigh-flex low cost

AlteraLatticeXilinxothers...

equalizer(optional)

equalizer(optional)

Camera Link HS 1x (up to 300 MByte/s) Implementation

Camera Framegrabber

Key Features of Camera Link HS 1x

Lowest Cost Solution - off the shelf, multi vendor components

Flexible Cables

1

2

Reliable Data Delivery3

Industry Supported4

Direct Fibre Optic Conversion possible5

Jitter Cleaner(optional)

Power overCLHS

Power overCLHS

Contact NameIfyouhaveanyquestionsorfeedbackonCameraLinkHS,pleasecontact:Jeff Fryman, Director, Standards Development, JFryman@robotics.orgorMike Miethig (Camera Link HS Chair), mike.miethig@dalsa.com

Camera Link HS Committee Thecommitteeismadeofcamera,framegrabberandcablecompaniesandareworkingtowardsaspecificationreleasein2011.Currentlyparticipatinginthecommitteeare:3M Company, ANAFOCUS, Basler, Bitflow, Components Express, Dalsa, Great River Technology, Intercon 1, Matrox, Mikrotron, National Instruments, PCO, Silicon Software, Stemmer Imaging, Toshiba Teli

Key Features of Camera Link HS1. LowestCostSolution-offtheshelf,multi-vendorcomponents

2.FlexibleCables3.ReliableDataDelivery4.IndustrySupported5.DirectFibreOpticConversionpossible

Possible Implementation using discrete serdesThefigurebelowisanactualsizeimplementationofaCameraLinkHS1xcamerafeaturingsingleprintedcircuitboardconstruction.