Bi vit ny nhm hng dn cc bn vit mt testbench n gin, ng thi nu mt cu trc c bn ca testbench cc bn c th tham kho. Ch , cu trc testbench a ra khng phi l chun (standard) m ch l mt xut cc bn c th tham kho v thc hin. Vic xy dng mt mi trng kim tra v to ra cc testbench cng l mt cng vic cn nhiu sng to khng km ngi thit k. Mnh cng rt mong bn no c kinh nghim chuyn su cng trao i chia s mi ngi c th cng hc hi. Phn ln testbench cha cc thnh phn c bn sau: Mt DUT (Device/Design Under Test) chnh l thnh phn m testbench s phi kim tra hay chnh l thit k m bn cn kim tra. Mt tp cc kch thch ng vo ca DUT (DUT Stimulus) Mt b gim st bt hoc phn tch ng ra ca DUT Cc kt ni ng vo v ng ra ca DUT vi testbench

Cu trc c bn ca ca mt testbench Verilog c th cha cc thnh phn thng gp sau: 1. The timescale directive: Ch dn v t l thi gian m phng timescale 2. Preprocessor Directives: nh ngha cc ch dn tin x l 3. Include Statements: Cc thnh phn c bao gm 4. Parameter definitions: nh ngha cc tham s s dng ni b trong file testbench 5. DUT Input regs: Khai bo kiu reg cho cc ng vo ca DUT (Bt buc) 6. DUT Output wires: Khai bo kiu wire cho cc ng ra ca DUT (Bt buc) 7. DUT Instantiation: Gi DUT (Bt buc) 8. Initial Conditions: To cc iu kin, gi tr khi ng ban u khi bt u m phng 9. Generating Test Vectors: To cc vector test hay cc gi tr kch thch ng vo ca DUT (Bt buc) 10. Debug output: Gim st v debug ng ra ca DUT 11. Self checking: T ng phn tch, so snh v nh gi kt qu kim tra theo mt hoc nhiu tiu ch m testbench t ra. Mnh xin minh ha c th tng thnh phn trn qua mt v d c th. V d ny bn gp trong bi vit v Hiu c bn v cch thc hin kim tra/m phng (Verification/Simulation) mt thit k. Thit k cn c kim tra l mt b m ln 4 bit nh sau:

y chnh l DUT kim tra thit k ny mnh vit mt testbench n gin bao gm 11 thnh phn lit k trn y minh ha. Cc bn ch n cc comment trong file testbench bit on code no thuc v thnh phn no.

Sau y mnh xin gii thch tng thnh phn trong testbench ny. 1. The timescale directive Ch dn v t l thi gian M (verilog):

c t u ca mt file module nh ngha n v thi gian m phng v chnh xc ca thi gian. S u chnh l gi tr ca mt n v thi gian. Tt c cc gi tr thi gian s dng trong testbench s c hiu theo n v ny. S sau chnh l chnh xc c trnh m phng hiu v gi li. Gi tr ny quy nh s ch s l v thi gian sau du phy thp phn s c gi li sau khi gi tr khai bo nhn vi n v thi gian. Vi khai bo timescale trn chng ta xt cc v d sau: #9 a=1b1; //Trnh m phng s ch 9 ns trc khi gn a bng 1 #9.01 a=1b1; //Trnh m phng s ch 9.01 ns #9.001 a=1b1; //Trnh m phng s ch 9 ns v chnh xc ch xc nh n 10 ps tr ln cn s l y ch l 1 ps Mt v d khc, nu khai bo timescale l 10 ns/1 ps #9 a=1b1; //Trnh m phng s ch 90 ns trc khi gn a bng 1 #9.01 a=1b1; //Trnh m phng s ch 90.1 ns #9.001 a=1b1; //Trnh m phng s ch 90.01 ns #9.0001 a=1b1; //Trnh m phng s ch 90.001 ns2. Preprocessor Directives: nh ngha cc ch dn tin x l

Chnh l cc define c khai bo u file testbench v sau timescale. Nh trong testbench v d, ch no s dng bin DELAY s c thay bng gi tr thp phn 10.3. Include Statements: Cc thnh phn c bao gm

Pht biu gi (include) thnh phn file lin quan s dng cc thng s trong file ny cng ging nh trong ngn ng C. File c gi s tr thnh mt phn ca file hin ti. File c gi thng l file cha cc thng s s c s dng chung cho nhiu file khc, thng c hiu l cc hng s ton cc (global constant). Theo nh testbench v d th file c include l file counter_define.h. File ny ch mt thng s l

4. Parameter definitions: nh ngha cc tham s s dng ni b trong file testbench

Tng t define, cc tham s parameter nhm khai bo cc bin thay th cho cc gi tr s c s dng nhiu trong module d dng hiu chnh li khi cn. Thng thng cc gi tr ny l Chu k clock (clock cycle) Thi gian kt thc m phng (finish time) Cc t iu khin hay cc lnh (control word or command) rng ng d liu, ng a ch (data/address width) Nh testbench v d, ch no s dng ENDTIME s c thay th bng gi tr thp phn 400. C th dng sau:

tng t nh vit #400 v c hiu l to tr 400 ns (da trn timescale khai bo) Vy s khc nhau gia khai bo parameter v define (hay nh ngha cc ch dn tin x l - Preprocessor Directives) l g? Vi Preprocessor Directives nh ngha cc ch dn tin x l th Khai bo trc (ngoi) module Thng l bin ton cc (global) C th nh ngha li thng qua dng lnh ca trnh bin dch hay trnh m phng. V d nh trong testbech minh ha, DELAY c nh ngha l 10. Sau khi compile file testbench bng ModelSim, gi tr ny vn c th thay i c sau mi ln chy m phng m khng cn sa file testbench thng qua dng lnh sau

Dng lnh ny yu cu ModelSim compile li file tb_counter.v vi gi tr DELAY c gn bng s thp phn 50.

Vi parameter Khai bo trong module Thng dng cho bin cc b (local) Khng th thay i li thng qua dng lnh ca trnh bin dch hay m phng. Ngha l, mun thay i, bn phi sa gi tr trong file testbench

5. DUT Input regs: Khai bo kiu reg cho cc ng vo ca DUT Cc bin ng vo ca DUT v cc bin c s dng gn gi tr li tn hiu ni chung phi c khai bo kiu reg. V d nh trong testbench minh ha Cc ng vo ca DUT c khai bo l:

6. DUT Output wires: Khai bo kiu wire cho cc ng ra ca DUT Cc bin ng ra ca DUT c khai bo kiu wire. V d nh trong testbench minh ha

7. DUT Instantiation: Gi DUT Khi gi DUT, th t port (th t tn hiu) ca DUT c gi khng quan trng m cc port ch c nhn bit da trn tn (port name). Nhng, cc bn nn s dng cch gi r rng sau

8. Initial Conditions: To cc iu kin, gi tr khi ng ban u khi bt u m phng To iu kin u hay gi tr u cho cc tn hiu hoc trng thi m phng

9. Generating Test Vectors: To cc vector test hay cc gi tr kch thch ng vo ca DUT Li cc tn hiu hay nhm tn hiu theo nhng gi tr v iu kin mong mun thc hin ng mc ch test. li cc tn hiu th chng ta c th li ring, c lp tng tn hiu nh trong testbench v d

hoc chng ta c th gom cc tn hiu li thnh mt vector, sau li vector ny theo nhng gi tr mong mun. V d, hai tn hiu rst_n v enable trong testbench v d c gom li nh sau

10. Debug output: Gim st v debug ng ra ca DUT Ngoi vic m trc tip ca s waveform ca cc trnh m phng xem dng sng ng ra th trong testbench chng ta c th s dng (hay s dng) hai lnh $display, $monitor v $time gi st testbench chy v gi tr ca cc tn hiu. V dinitial begin $display("----------------------------------------------"); $display("----------- SIMULATION RESULT ----------------"); $display("----------------------------------------------"); `ifdef FULL_SIGNAL $monitor ("TIME = %d, clk = %b, rst_n = %b, enable = %b, count = %d,counter_full = %b",$time, clk, rst_n, enable, count, counter_full); `else $monitor("TIME = %d, clk = %b, rst_n = %b, enable = %b, count = %d",$time, clk, rst_n, enable, count); `endif End

Trong : "$time" s tr v gi tr nguyn 64-bit ca thi gian hin ti c tnh theo timescale. "$display" in ra mt chui no ch mt ln duy nht mi khi lnh c gi. "$ monitor" in ra cc chui hay gi tr c khai bo mi khi c s thay i ca mt trong cc tn hiu c lit k trong danh sch hm $monitor. Nh v d trn l clk, rst_n, enable, count v c hoc khng c counter_full (tn hiu ny c hoc khng ph thuc vo define ca bin FULL_SIGNAL).11. Self checking: T ng phn tch, so snh v nh gi kt qu kim tra theo mt hoc nhiu tiu ch m testbench t ra.

Cui cng, sau y l kt qu khi chy testbench m phng trn phn mm ModelSim (quan st ti ca s transcript)