Y = ~Xnot(Y,X)
Basic Gates
NOT
X Y
01
10
X
YZ
X Y
X Y
Z
AND
OR
X Y Z0 0 00 1 01 0 01 1 1
X Y Z0 0 00 1 11 0 11 1 1
Z = X & Yand(Z,X,Y)
Z = X | Yor(Z,X,Y)
Any logic circuit can be created using only these three gates
NOT Gate
X ~X ~~X = X
X ~X ~~X0 1 01 0 1
Behavior:The output of a NOT gate is the inverse (one’s complement) of the input
AND Gate
X[1]X[2]
X[n]
ZAND
Behavior:The output of an AND gate is HIGH only if all inputs are HIGH
assign Z = X[1] & X[2] & ... & X[n];assign Z = &X;and(Z,X[1],X[2],...,X[n]);
4-Input AND GateX[1]
X[2]
X[3]
X[4]
Z
X[1]
X[2]
X[4]
ZANDX[3]
X[1]
X[2]
X[3]
X[4]
Z
3-Level
2-Level
Behavior:Z = X[1];for(i=2; i<=4; i=i+1) Z = Z & X[i];
OR Gate
Behavior:The output of an OR gate is LOW only if all inputs are LOW
X[1]
X[2]
X[n]
ZOR
assign Z = X[1] | X[2] | ... | X[n];assign Z = |X;or(Z,X[1],X[2],...,X[n]);
4-Input OR Gate
X[1]
X[2]
X[4]
ZORX[3]
X[1]
X[2]
X[3]
X[4]
Z
3-Level
2-Level
Behavior:Z = X[1];for(i=2; i<=4; i=i+1) Z = Z | X[i];
X[1]
X[2]
X[3]
X[4]Z
Exclusive-OR (XOR) Gate
Behavior:The output of an XOR gate is HIGH only if the number of HIGH inputs is ODD
X[1]
X[2]
X[n]
ZXOR
assign Z = X[1] ^ X[2] ^ ... ^ X[n];assign Z = ^X;xor(Z,X[1],X[2],...,X[n]);
2-Input XOR Gate
XOR X Y Z0 0 00 1 11 0 11 1 0
Z = X ^ Yxor(Z,X,Y)
X Y
Z
Note: if Y = 0, Z = Xif Y = 1, Z = ~X
Therefore, an XOR gate can be used as a controlled inverter
4-Input XOR Gate
X[1]
X[2]
X[4]
ZXORX[3]
X[1]
X[2]
X[3]
X[4]
Z
3-Level
2-Level
X[1]
X[2]
X[3]
X[4]Z
Note: Z = 1 if the number of 1 inputs in ODD
Behavior:Z = X[1];for(i=2; i<=4; i=i+1) Z = Z ^ X[i];
Exclusive-NOR Gate XNOR (NOT – XOR)
Behavior:The output of an XNOR gate is HIGH only if the number of HIGH inputs is EVEN
X[1]
X[2]
X[n]
ZXNOR
assign Z = ~(X[1] ^ X[2] ^ ... ^ X[n]);assign Z = ~^X;xnor(Z,X[1],X[2],...,X[n]);
2-Input XNOR Gate
XNOR X Y Z0 0 10 1 01 0 01 1 1
Z = ~(X ^ Y)Z = X ~^ Yxnor(Z,X,Y)
Note: Z = 1 if X = Y
Therefore, an XNOR gate can be used as an equality detector
XY
Z
NAND Gate (NOT-AND)
Behavior:The output of an NAND gate is LOW only if all inputs are HIGH
X[1]
X[2]
X[n]
ZNAND
assign Z = ~(X[1] & X[2] & ... & X[n]);assign Z = ~&X;nand(Z,X[1],X[2],...,X[n]);
NOR Gate (NOT – OR)
Behavior:The output of an NOR gate is HIGH only if all inputs are LOW
X[1]
X[2]
X[n]
ZNOR
assign Z = ~(X[1] | X[2] | ... | X[n]);assign Z = ~|X;nor(Z,X[1],X[2],...,X[n]);
Gates2.vmodule gates2 ( A ,Z ,B );
input A ;wire A ;input B ;wire B ;
output [1:6] Z ;wire [1:6] Z ;
assign Z[1] = A & B;assign Z[2] = ~(A & B);assign Z[3] = A | B;assign Z[4] = ~(A | B);assign Z[5] = A ^ B;assign Z[6] = A ~^ B;
endmodule
module gates ( X ,Z, Y );
input [4:1] X ;wire [4:1] X ;
output [6:1] Z ;wire [6:1] Z ;output [6:1] Y ;wire [6:1] Y ;
and(Z[6],X[1],X[2],X[3],X[4]);nand(Z[5],X[1],X[2],X[3],X[4]);or(Z[4],X[1],X[2],X[3],X[4]);nor(Z[3],X[1],X[2],X[3],X[4]);xor(Z[2],X[1],X[2],X[3],X[4]);xnor(Z[1],X[1],X[2],X[3],X[4]);
assign Y[6] = &X; assign Y[5] = ~&X;assign Y[4] = |X;assign Y[3] = ~|X;assign Y[2] = ^X;assign Y[1] = ~^X;
endmodule
Gates4.v
Verilog gate level primitives
Verilog reduction operators
assign Y[6] = &X; assign Y[5] = ~&X;assign Y[4] = |X;assign Y[3] = ~|X;assign Y[2] = ^X;assign Y[1] = ~^X;
and(Z[6],X[1],...nand(Z[5],X[1], ...or(Z[4],X[1], ...nor(Z[3],X[1], ...xor(Z[2],X[1], ...xnor(Z[1],X[1], ...
NAND Gate
X
Y
X
Y
Z Z
Z = ~(X & Y) Z = ~X | ~Y
=
X Y W Z0 0 0 10 1 0 11 0 0 11 1 1 0
X Y ~X ~Y Z0 0 1 1 10 1 1 0 11 0 0 1 11 1 0 0 0
De Morgan’s Theorem-1
~(X & Y) = ~X | ~Y
• NOT all variables• Change & to | and | to &• NOT the result
NOR Gate
X
YZ
Z = ~(X | Y)
X Y Z0 0 10 1 01 0 01 1 0
X
YZ
Z = ~X & ~Y
X Y ~X ~Y Z0 0 1 1 10 1 1 0 01 0 0 1 01 1 0 0 0
De Morgan’s Theorem-2
~(X | Y) = ~X & ~Y
• NOT all variables• Change & to | and | to &• NOT the result
De Morgan’s Theorem
• NOT all variables
• Change & to | and | to &
• NOT the result
• --------------------------------------------• ~X | ~Y = ~(~~X & ~~Y) = ~(X & Y)• ~(X & Y) = ~~(~X | ~Y) = ~X | ~Y• ~X & ~Y = ~(~~X | ~~Y) = ~(X | Y)• ~(X | Y) = ~~(~X & ~Y) = ~X & ~Y
module gates ( X ,Z);
input [4:1] X ;wire [4:1] X ;
output [1:6] Z ;reg [1:6] Z ;integer i;
// 4-input and gatealways @(X)
begin Z[1] = X[1];for(i=2; i<=4; i=i+1)
Z[1] = Z[1] & X[i];end
X[1]
X[2]
X[3]
X[4]
Z
Behavior of multiple input gates
Behavior of multiple input gates
// 4-input nand gate -- DeMorgan's Theoremalways @(X)
begin Z[2] = ~X[1];for(i=2; i<=4; i=i+1)
Z[2] = Z[2] | ~X[i];end
~X[1]
~X[2]
~X[3]
~X[4]Z
X[1]
X[2]
X[n]
ZNAND =
// 4-input or gatealways @(X)
begin Z[3] = X[1];for(i=2; i<=4; i=i+1)
Z[3] = Z[3] | X[i];end
Behavior of multiple input gates
X[1]
X[2]
X[3]
X[4]Z
// 4-input nor gate// DeMorgan's theoremalways @(X)
begin Z[4] = ~X[1];for(i=2; i<=4; i=i+1)
Z[4] = Z[4] & ~X[i];end
~X[1]
~X[2]
~X[3]
~X[4]
Z
// 4-input xor gatealways @(X)
begin Z[5] = X[1];for(i=2; i<=4; i=i+1)
Z[5] = Z[5] ^ X[i];end
Behavior of multiple input gatesX[1]
X[2]
X[3]
X[4]Z
// 4-input xnor gatealways @(X)
begin Z[6] = X[1];for(i=2; i<=4; i=i+1)
Z[6] = Z[6] ~^ X[i];end
endmodule
X[1]
X[2]
X[3]
X[4]Z
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