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Design & Implementation of 128 bit AE
Crypto processor using FPGA
By
Atul D.Narkhede
Under the Guidance of
Prof. U.A.Rane
Department of Electronics & TelecommunicationEngineering
Shri Sant Gajanan Maharaj College of Engineering,
Shegaon 444 203 (M.S.)
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PROJECT OUTLINE
INTR!"CTIN
ENCR#$TIN
!ECR#$TIN
%&C' !IGRM
RES"&TS
CNC&"SINS
REERENCES
Department of Electronics & TelecommunicationEngineering
Shri Sant Gajanan Maharaj College of Engineering,
Shegaon 444 203 (M.S.)
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Department of Electronics & TelecommunicationEngineering
Shri Sant Gajanan Maharaj College of Engineering,
Shegaon 444 203 (M.S.)
The crypto processor is dedicated microprocessor for carrying
cryptographic operations using various secure crypto graphical
standards and efficient algorithms.
We are interested to design and implement128 bit crypto
processor using Advanced Encryption Standard (AES .The physical development !ill be done using "#$%&
hard!are description language.
Intro*+tion
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Department of Electronics & TelecommunicationEngineering
Shri Sant Gajanan Maharaj College of Engineering,
Shegaon 444 203 (M.S.)
AES is an algorithm for performing encryption and the reverse
decryption& !hich is a series of !ell'defined steps that can be
follo!ed as a procedure.
The original information is no!n as plainte)t& and the encrypted
form as cipher te)t.
AES is one of the most popular algorithms used in symmetric ey
cryptography.
Symmetric'ey cryptography refers to encryption methods in !hich
both the sender and receiver share the same ey or very less
commonly their eys are different& for this reason it counted in
symmetric ciphers.
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Department of Electronics & TelecommunicationEngineering
Shri Sant Gajanan Maharaj College of Engineering,
Shegaon 444 203 (M.S.)
ES Enr-tion
an* !er-tion
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Department of Electronics & TelecommunicationEngineering
Shri Sant Gajanan Maharaj College of Engineering,
Shegaon 444 203 (M.S.)
i*1
i*i+1
, -r
Add /ound0ey
yte Sub(State
Shift/o!(State
i)columns(State
Add round 0ey
yte Sub(State
Shift/o!(State
Add round 0ey
0
Ey
S
3
#
E
$
4
%E
Enr-tion
$roe//
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Department of Electronics & TelecommunicationEngineering
Shri Sant Gajanan Maharaj College of Engineering,
Shegaon 444 203 (M.S.)
!er-tion
$roe//
i*1
i*i+1
, - r
Add /ound0ey (State& ,nvroundey
,nvyte Sub(State
,nvShift/o!(State
i)columns(State
Add round 0ey(state&,nvroundey
,nvyte Sub(State
,nvShift/o!(State
Add round 0ey(state&,nvround ey
0
E
y
S
3
#
E
$4
%
E
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Department of Electronics & TelecommunicationEngineering
Shri Sant Gajanan Maharaj College of Engineering,
Shegaon 444 203 (M.S.)
#ard!are
53 !ith 6ilin) ,SE 7.1i
6ilin) Spartan ,,, $evelopment
oard 63S9::'9 5;2:83
5S
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=unctional$escription
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Department of Electronics & TelecommunicationEngineering
Shri Sant Gajanan Maharaj College of Engineering,
Shegaon 444 203 (M.S.)
Sub'System loc $iagram
AES CoreAES Core
Program
ControlLogic
PS2
KeyboardInterface
LCDInterfac
e
RAM
ROM
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Department of Electronics & TelecommunicationEngineering
Shri Sant Gajanan Maharaj College of Engineering,
Shegaon 444 203 (M.S.)
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Department of Electronics & TelecommunicationEngineering
Shri Sant Gajanan Maharaj College of Engineering,
Shegaon 444 203 (M.S.)
loc
$iagram
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Department of Electronics & TelecommunicationEngineering
Shri Sant Gajanan Maharaj College of Engineering,
Shegaon 444 203 (M.S.)
,mage 1
5ro>ect Setup
,mage 2
=5?A 0it (Spaten'
Re/+lt/
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Department of Electronics & TelecommunicationEngineering
Shri Sant Gajanan Maharaj College of Engineering,
Shegaon 444 203 (M.S.)
,mage' 9
AES in AS3,, ode
,mage
,nitial Start up
f l i & l i i
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Department of Electronics & TelecommunicationEngineering
Shri Sant Gajanan Maharaj College of Engineering,
Shegaon 444 203 (M.S.)
,mage '@
Encryption of $ata in #E6 ode
,mage'
,nsert 3haracter
D t t f El t i & T l i ti
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Department of Electronics & TelecommunicationEngineering
Shri Sant Gajanan Maharaj College of Engineering,
Shegaon 444 203 (M.S.)
,mage' 8
$ecrypted $ata in #E6 ode
,mage' 7
Encrypted $ata in AS3,, ode
D t t f El t i & T l i ti
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Department of Electronics & TelecommunicationEngineering
Shri Sant Gajanan Maharaj College of Engineering,
Shegaon 444 203 (M.S.)
,mage'1:
3omplete loo,mage B
Criginal $ata after $ecryption
D t t f El t i & T l i ti
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Department of Electronics & TelecommunicationEngineering
Shri Sant Gajanan Maharaj College of Engineering,
Shegaon 444 203 (M.S.)
,mage D 12
$ata ?iven in #E6 ode
,mage'11
0ey ?iven in #E6 ode
D t t f El t i & T l i ti
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Department of Electronics & TelecommunicationEngineering
Shri Sant Gajanan Maharaj College of Engineering,
Shegaon 444 203 (M.S.)
,mage D 19
Encrypted $ata as ,
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Department of Electronics & TelecommunicationEngineering
Shri Sant Gajanan Maharaj College of Engineering,
Shegaon 444 203 (M.S.)
,mage' 1
Criginal $ata after $ecryption
Department of Electronics & Telecommunication
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Department of Electronics & TelecommunicationEngineering
Shri Sant Gajanan Maharaj College of Engineering,
Shegaon 444 203 (M.S.)
y using AES algorithms net!or processor can encipher and decipher the te)t by
using cipher ey of sie 128& 1B2&or 2@ bits.
AES'128 implementation can be used in cryptographic accelerator 3ards&
!hich helps in real time encryption process of servers at the time of client
authentication and symmetric encryption process&
!hich reduces load of 354 usage.
Conl+/ion
Department of Electronics & Telecommunication
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Department of Electronics & TelecommunicationEngineering
Shri Sant Gajanan Maharaj College of Engineering,
Shegaon 444 203 (M.S.)
Secure 3ommunication
AT $"$ 3ontent Secure et!ors
Secure Storage
3onfidential 3orporate $ocuments ?overnment $ocuments =, =iles 5ersonal Storage $evices
5erson ,nformation 5rotection
Applications
Department of Electronics & Telecommunication
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Department of Electronics & TelecommunicationEngineering
Shri Sant Gajanan Maharaj College of Engineering,
Shegaon 444 203 (M.S.)
/eferences
F1G William Stallings H3ryptography and et!or Security 5rinciples and 5racticesI& =ourth
Edition&& ovember 1@& 2::
F2G #aiyong 6ie& %i Jhou& and %a)mi huyan HArchitectural Analysis of 3ryptographicApplications for et!or 5rocessorsI.
FG Spartan' ?eneration =5?As K' The 4ltimate %o!'3ost Applications 5latform.
F9G 0ris ?a> and 5a!el 3hodo!iec H#ard!are performance of the AES finalists ' survey
and analysis of resultsI& ?eorge ason 4niversity
FG !!!.en.!iipedia.org
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Department of Electronics & TelecommunicationEngineering
Shri Sant Gajanan Maharaj College of Engineering,
Shegaon 444 203 (M.S.)
/eferences
F7G L. $aemen and ". /i>men& HAES Proposal: /i>ndaelI& AES Algorithm Submission&
September & 1BBB
httpKndaelndaeldoc"2.ip
F8G AES page available via httpKFBG 3omputer Security Cb>ects /egister (3SC/K!!!.
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