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Chap. 8 Datapath Units
Prof. An-Yeu Wu
Undergraduate VLSI CourseUpdated: May 24, 2002
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Several Implementations of Adders
One-Bit Full Adder (Cell)
Carry-Ripple Adder
Transmission-Gate Adder
Carry lookahead Adder
Bit-Serial Adder
Carry-Select Adder
Conditional- Sum Adder Manchester Adder
Very wide Adder
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One-Bit Full Adder (Cell)
A and B are
the adder
inputs, C isthe carry input,
SUM is the
sum output,
and CARRY is
the carry
output.
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Boolean Function
CARRYCBAABC
BACABCBAABCSUM
BACABBCACABCARRY
CBA
BABACBAABC
CBACBACBAABCSUM
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Implementation
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Implementation (Cont.)
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Carry-Ripple Adder
Simple & Slow
One stage delay time Tc
n stages delay time nTc
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Bit-Parallel Adder
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Subtractor
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Bit-Serial Adder
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Use register tostore CARRY
Carry-Save Adder
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CPA
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Transmission-Gate Adder
Use T-G to Implement XOR Gate
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Transmission-Gate Adder (Cont.)
Total 24 Transistors
SUM and CARRY have the same delay time
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Reduced Tx numbers
Dont care speed
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Carry-Lookahead Adders
The linear growth of
adder carry-delay with
the size of the input
word for n-bit addermaybe improved by
calculation the
carries to each stage
in parallel.
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Carry of the ith stage ---
Ci=Gi + PiCi-1
Gi=AiBi generate signal
Pi=Ai + Bi propagate signal
Expanding
Ci= Gi + PiCi-1 + PiPi-1Gi-2 + .. + PiP1P0
For four stages, the appropriate term :
C0= G0 + P0CIC1= G1 + P1G0 + P1P0CI
C2= G2 + P2G1 + P2P1G0 + P2P1P0CI
C3= G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0CI
Carry-Lookahead Adders (Cont.)
Fig1. Generic carry-lookahead adder
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Carry-Lookahead Adders (Cont.)
The size and fan-in of the gates needed to
implement this carry-lookahead scheme can
clearly get out of hand the number of
stages of lookahead is usually limited to
about 4.
The circuit and layout are quite irregular.
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Dynamic Carry Gates
The worst-case delay path in this circuit has six n-
transistor in series.
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High-speed Carry Lookahead Logic
Use pseudo-nMos to achieve high-speed static operation.
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Manchester Adder Circuits
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Manchester Adder Circuits (Cont.)
Dynamic stage
When CLK is low, the output node is pre-charged by the p
pull-up transistor.
When CLK goes high, the pull-down transistor turns on. If carry generate G=AB is true the output node
discharges.
If carry propagate P=A+B is true a previous carry may
be coupled to the output node, conditionally discharging it.
Static stage This requires P to be generated as AB
The Manchester adder stage improves on the carry-
lookahead implementation.
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Manchester Adder Circuits (Cont.)
Fig6. Manchester adder with carry bypass: (a) simple (b) conflict free
The control signalsT1,T2,and T3 shown
in Fig6(b) are
generated by:
T1 = -(P0P1P2)P3
T2 = -P3
T3 = P0P1P2P3
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Manchester Adder Circuits (Cont.)
The worst case propagation time of a Manchester
adder can be improved by bypassing the four stages
if all carry-propagate signals are true.
Fig. 6(b) uses a conflict -free bypass circuit, whichimproves the speed by using a 3-input multiplexer
that prevents conflicts at the wired OR node in the
adder.
In Fig. 6(b), the inverter presented on the Cin signalhas been moved to the center of the carry chain to
improve speed.
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Carry-Select Adder
Fig7. Carry-select adder:(a) basic architecture (b) 32-bit carry-select adder example
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Conditional-Sum Adder
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Conditional-Sum Adder (Cont.)
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Very Wide Adders
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Very Wide Adders (Cont.)
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Very Wide Adders with Bypass
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Homework #5
- Conditional Sum Adder8-bit
- Draw the schematic diagram of your design.- Verify your idea first using C or Matlab
programs.
- Write down the Verilog code to verify your
design.Check your results with the C/Matlabresults.
- Due date: June 14, 2002
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