EE241
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UC Berkeley EE241 B. Nikolić
EE241 - Spring 2001Advanced Digital Integrated Circuits
Lecture 11Dynamic Logic
UC Berkeley EE241 B. Nikolić
Delayed Precharge
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UC Berkeley EE241 B. Nikolić
IBM’s 1GHz ProcessorSilberman et al, ISSCC’98JSSC 11/98
UC Berkeley EE241 B. Nikolić
Domino Properties� Logic evaluation propagates as falling dominoes� Evaluation period determines the logic depth� The nodes must be precharged during the precharge
period (can limit the minimum size of PMOS)� Inputs must be stable (or have only one rising
transition) during the evaluation� Gates are ratioless� Restorer is ratioed� All the gates are non-inverting� Only one transition to be optimized
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UC Berkeley EE241 B. Nikolić
Multiple-Output Domino (MODL)
Hwang, Fisher, ISSCC’88
F = F1F2
Common subexpressions
UC Berkeley EE241 B. Nikolić
Lookahead Adder
Multiple Output Domino (MODL)
Generate Propagate
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UC Berkeley EE241 B. Nikolić
Lookahead Adder
4-bit group generate 4-bit group propagate
UC Berkeley EE241 B. Nikolić
Compound Domino
Houston et al,U.S. Pat. 5,015,882May 1991.
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UC Berkeley EE241 B. Nikolić
Clock-Delayed Domino
UC Berkeley EE241 B. Nikolić
Clock-Delayed Domino
φ
DDV
Dφ
Possible implementation of delay block
No need for inversionUsed in IBM’s 1GHz integer processor (ISSCC’98)
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UC Berkeley EE241 B. Nikolić
NTP DominoNoise-tolerant precharge (NTP)
Yamada, ICCD’95
UC Berkeley EE241 B. Nikolić
Output-Prediction LogicInverting logic:
Output-prediction logic:
McMurchie, et al, ICCD’2000
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UC Berkeley EE241 B. Nikolić
Output-Prediction LogicNOR3:
Clocking:
McMurchie, et al, ICCD’2000
UC Berkeley EE241 B. Nikolić
Output-Prediction LogicNOR3 chain of 10:
Clock separation:
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UC Berkeley EE241 B. Nikolić
np-CMOS
Mp
Me
VDD
PDN
φ
In1In2In3
φ
Me
Mp
VDD
PUN
φ
In4
φOut1
Out2
Only 1→0 transitions allowed at inputs of PUNGoncavles, De Man JSSC 6/83Friedman, Liu, JSSC 4/84
UC Berkeley EE241 B. Nikolić
np-CMOS
One-bit adder
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UC Berkeley EE241 B. Nikolić
NORA Logic
Mp
Me
VDD
PDNIn1In2In3
Me
Mp
VDD
PUNIn4
Out1
Out2
To otherN-blocks To other
CLK
CLK
P-blocks
CLK
CLK
UC Berkeley EE241 B. Nikolić
NORA Logic
EE241
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UC Berkeley EE241 B. Nikolić
NORA Logic
UC Berkeley EE241 B. Nikolić
NORA Logic
φ
φ
VDDVDD
PDN
φ
In1In2In3φ
VDD
PUN
φ
φ
Out
φ
φ
VDD
Out
VDD
PDN
φ
In1In2In3φ
VDD
In4
In4
VDD
(a) φ-module
(b) φ-module
Combinational logic Latch
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UC Berkeley EE241 B. Nikolić
NORA Logic
UC Berkeley EE241 B. Nikolić
NORA Logic
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UC Berkeley EE241 B. Nikolić
NORA Logic
UC Berkeley EE241 B. Nikolić
NORA Logic
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UC Berkeley EE241 B. Nikolić
NORA Logic
UC Berkeley EE241 B. Nikolić
Zipper Logic
Lee, Szeto, Circuits and Devices 5/86
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UC Berkeley EE241 B. Nikolić
Zipper Logic
Type I:
Type II:
UC Berkeley EE241 B. Nikolić
Clock and Data Precharged Logic
Domino CDPD
Yuan, Svensson, Larson, Electronics Letters, 12/93
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UC Berkeley EE241 B. Nikolić
Clock and Data Precharged Logic
Logicchains
UC Berkeley EE241 B. Nikolić
Mp
Me
VDD
CLK
CLK
A
B
M1
M2
A B
Mp CLK
O = ABO = AB
VDD
Mf1 Mf2
Differential (Dual Rail) Domino
Dynamic CVSL (Clock CVSL) - Heller et al, ISSCC’84
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UC Berkeley EE241 B. Nikolić
Dual-Rail Domino
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