A walk in the NanoPark -Practical Paths to Molecular Computers
Paul D. Franzon, with many others (acknowledged within, especially
David Nackashi and Christian Amsink)
North Carolina State UniversityDepartment of Electrical and Computer Engineering
[email protected]/erl/moelec
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OutlineOutline> The End Of The Silicon Roadmap> The Nanotechnology Promise
u Nanotelectronics = Devices + Integration
> Molecular Circuit Elements > Integration Alternatives
u The Tour-Reed Nanocell
u The NRL Cow Pea virus
> Circuit Design > CAD tool perspectives
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The End of the Silicon RoadmapThe End of the Silicon Roadmap
> The 35nm Technology Nodeu Around 2014*, we are expected to reach the 35nm
Technology Node◊ Mainly gate oxide tunnelling limit◊ This Technology Node includes 20-22nm transistor gate
lengths
> Active and aggressive research beyond 35 nodeu Next ITRS includes planning for 9 nm gates
u Technology pieces demonstrated down to 6 nm
*Sources : ITRS, Proc. IEEE 3/2001
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The end of the roadmap…The end of the roadmap…
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The The Nanotechnology Nanotechnology PromisePromise
A set of electronic nanodevices…..1. Chemical Synthesis
SAcAcS
X
Y
SAc
SAc
AcS
AcS
NC
NC
NC
NCOMe
OMe
OMe
OMe
Relatively Easy
Difficult
Courtesy of J. C. Ellenbogen
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NanodevicesNanodevices….….
2. Single Electron Transistors
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NanodevicesNanodevices….….
3. Quantum Cellular Automota> Coupled Spin States and Pauli Exclusion Principle
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NanodevicesNanodevices….….
4. Quantum Computing
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NanodevicesNanodevices……
5. Carbon Nanotubes
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NanodevicesNanodevices……
6. Resonant Tunneling Transistors
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Nanointegration Nanointegration TechnologiesTechnologies
1. Random chemical self-assemblyInput terminals Output terminals
Self-assembling molecularswitches (two types)
Nanoparticle
Work originated by B. Van Zandt, J.M. Tour, Rice University.
Courtesy of David Allera and Philipp Harder, PSU
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NanointegrationNanointegration
2. Nano-structured biological Materialsu Viruses, DNA, etc.
314 Å
Cow Pea Mosaic Virus
31 nm
Courtesy : Shashidar and Ratner, NRL
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NanotechnologiesNanotechnologies……
3. Directed self-assemblyu E.g. Viral nanoblock
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NanointegrationNanointegration….….
4. Inorganic nanostructures
CD = 100 nm
Pitch = 360 nm
From: Sone et.al., “Nanofabrication toward sub-10nmand its application to novel nanodevices,” Nanotechnology v10 (1999).
From: Chen et.al., “Two-dimensional arrangement of octadecylamine-functionalized gold nanoparticles using the LB technique,” Nanotechnology v11 (2000).
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NanointegrationNanointegration
5. Carbon Nanotubesu Possibility as “nano” interconnect
6. AFM and STMCourtesy of Schönenberger and Forró
Courtesy of Shashidar and Ratner
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Molecular Circuit ElementsMolecular Circuit Elements
> Two Terminal Devicesu Rectifying diodes
u Diodes exhibiting Negative Differential Resistance (NDR)
uWires
u Resistors
u Settable / Re-settable Devices
> Three terminal devicesu Chemical synthesis possible
u Electrical testing is quite difficult
Courtesy of Veena Misra
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0.0 0.5 1.0 1.5 2.0 2.5
0.0
400.0p
800.0p
1.2n
Ivalley= 1 pA
Ipeak= 1.03 nA
T= 60 K
I (A
)
V
J = 53 A/cm2
NDR = -380 µΩ-cm2
J ~ 50 A/cmJ ~ 50 A/cm22
NDR ~ NDR ~ --380380 µΩµΩµΩµΩ--cmcm22
0 1 2 3 40
250p
500p
750p
1n
Cur
rent
(A
)
Voltage (V)
Temperature 180 220 295 RT
1997
Summer 1999
Fall 1999
Mol DevicesMol Devices> Origins:
u Basic molecular device & self-assembly concepts (US05475341 (‘95), US05589692 (‘96))
u Single molecule transport (‘96)
u First molecular devices (‘97)
Courtesy : Mark Reed
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-0.75 -0.50 -0.25 0.00 0.25 0.50 0.75 1.00
-600.0µ
-400.0µ
-200.0µ
0.0
200.0µ
400.0µ
600.0µ
800.0µ
Cur
rent
(A
)
Voltage (V)
0.00 0.25 0.50 0.75 1.00-100.0µ
0.0
100.0µ
200.0µ
300.0µ
400.0µ
500.0µ
600.0µ
700.0µ
800.0µ
T = 300K first trace second trace
Cur
rent
(A
)
Voltage (V)
Winter 2000
Planar devices, ambient NDR & memoryPlanar devices, ambient NDR & memory
Courtesy : Mark Reed
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The ChallengesThe Challenges
> Have some switches……but……also need
> Integration Technology u Orderable Interconnect
◊ To create custom logic
◊ To create regular arrays (memory)
u Low-resistance interconnect
> Robustnessu Signal Integrity
u Restoring Logic Circuit Structures
u Input/Output Isolation
u Parasitic Control
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IntegrationIntegration--Scale IssuesScale Issues
> Must avoidu Using regular lithography
u Using MOSFET gates
SAcAcS
X
Y
Chip level
Cell level
Small array
Cluster of transistorsSingle transistor
Gate width is 0.18µm (180nm)
2.2nm
(Only M1 and M2 shown)
(Only M1 and M2 shown)
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…Scale Issues @ end of roadmap…Scale Issues @ end of roadmap
22 nm
2.2 nm
120 nm
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Role as Circuit Designer Role as Circuit Designer
> The “middleman”
Physical Circuit TopologiesArchitectures
LogicalArchitectures
Molecular Spice ModelingDevices
S
Au
Au
N O2
(2)(2)
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Circuit Design Issues Circuit Design Issues
> Current Device Models pooru Leading own characterization efforts
> Digital circuit abstractionu Restoring logic
u Support fan-out (impedance isolation)
u Robust in presence of process variations
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NDR Device ModelNDR Device Model> I-V data points provided by Jia Chen / Mark Reed - Yale
University
> Model was created using a piecewise linear (PWL) function in HSPICE (G element)
> Transient responses not included in this model
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Bistable Device DesignBistable Device Design
Strategy
> Utilize the negative resistance to locate two stable points of operation
> Results in Memory Element
Design
> Load the molecular diode with a voltage source and current-limiting resistor (R0, D0)
Adapted from J.Huber et al., IEEE Trans. Electron. Devices 44, 2149 (1997)
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NAND Gate DesignNAND Gate Design
> 2-Input Current-mode NAND gate
> Gate is first reset to place the NDR diodes in the low impedance state
u At this state, Iout is 500pA and Ibridge is 0pA
> If both input currents reach threshold, the output transitions from a low impedance state to a high impedance state
u At this state, Iout is 1-2 pA
> Output capacitance/resistance are used to simulate loading conditions
A B F
0 0 1
0 1 1
1 0 1
1 1 0
NAND truth table
* Circuit adapted from Chow, Principles of Tunnel Diode Circuits, (1964)
Rectifying diode from C.Zhou, M.R.Deshpande, M.A.Reed, J.M.Tour,” Nanoscale metal/self-assembled monolayer/metal heterostructures,” Appl. Phys. Lett., vol.71,pp.611-613,1997.
Iout
Ibridge
Rectifying diode for isolation *
Output Load
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NAND Gate DesignNAND Gate Design
> Gate is reset before each evaluation period
> An input/output “1” is equivalent to a 500pA current
> An input/output “0” is equivalent to a 1-2pA current
> The gate evaluates the currents at both inputs. If both inputs are at or beyond threshold at any time, a transition is made to the low current state.
> These waveforms were extracted through simulation without rectifying diodes
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NOR Gate DesignNOR Gate Design
> Transition from high to low occurs abruptly at an input current of 300pA
> Even as input current ramps up, the output current does not appreciatively increase
> Helps to minimize noise from propagating through the gate
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Memory ArraysMemory ArraysMemory Cell
> A memory cell is constructed from a bistable latch
> State “0” : Low Voltage/ High Current
> State “1” : High Voltage / Low Current
> Data to be written is placed on horizontal write lines (W0, W1)
> Data read is taken from the lower read lines (RD0,RD1)
> Cells are written in multi-bit words using the vertical readwrite lines (RW0,RW1)
Adapted from Chang, Parametric and Tunnel Diodes, (1964)
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Memory ArraysMemory Arrays> A “reset” signal is sent
by lowering the RW line to 2.0V
> A “write” signal is sent by raising the RW line to 2.6V
> Data words to be written into memory are placed on the RW bus
> The internal nodes of the bistable latch hold the values
> Data is read by lowering the RW line to 2.2V and reading the RD bus
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Suggested ArchitectureSuggested Architecture
Au- plate contacts all top faces’ gold balls
Wires intersect on 2 different “heights”
Whole circuit element chemically synthesized
Bonus: 4 memory elements per logical cell - fault tolerance
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Circuits DiscussionCircuits Discussion
> Have simulated fan-out; oscillation-free
> Tight marginsu < 5%
uWiring resistance could easily dominate
u Unclear if these resistors are buildable
> Difficult CMOS interface
> Margins improved byu Bistable devices (e.g DiNitro)
◊ Margin approaches Bistability Spread
u Increased current density (e.g. DiNitro)
u More device types with isolation◊ E.g. Gain devices
> C.f. CMOS end game : ~ 50 transistors/µµm22
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Memory DiscussionMemory Discussion
> Silicon DRAM densityu Today : 8 bits / µm2
u >200 bits / µm2 at end of road map
> SRAM built using Cow Pea Virusu >4,000 bits / µm2 / layer
> Integration Problemu Requires interface wires at < 10 nm pitch
u 30 nm pitch wires still gives 1,000 bits / µm2
u Common problem across many proposed structures
Nano Lithographic
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Memory (2)Memory (2)
> Signal Integrity Issuesu 0.1 V noise margin in structure above
u Improved to 1.6 V with bistable diNitro circuit
> Scaling LimitsuWiring resistance : device resistance
u On : off ratio for bistable devices
u Exploring ways around these limits
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CAD Tool IssuesCAD Tool Issues
> Frankly, mainly in TCADu Device modeling and prediction
> Higher level design issuesu Coping with a high degree of randomness
uWhile preserving traditional abstractions
◊ Circuit – logic – microarchitecture - ISA
u E.g. Nanocell……
◊ Difficult optimization problem
◊ Literally finding a “needle in a haystack”
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ConclusionsConclusions
> Molecular Electronics most promising of “beyond the end of the roadmap” device technologiesu True isolation, Room temperature, etc.
u Might be more suited as a memory material in short term
> Many challengesu Quality circuit elements
u Integration technologies
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