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IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 49, NO. 3, MAY/JUNE 2013 1383

A Gallium Nitride Switched-Capacitor Circuit UsingSynchronous Rectification

Mark J. Scott, Student Member, IEEE, Ke Zou, Jin Wang, Member, IEEE, Chingchi Chen, Ming Su, and Lihua Chen

Abstract—The physical characteristics of gallium nitride (GaN)make it theoretically superior to silicon (Si) in such aspects asthe temperature of operation, switching speed, breakdown voltage,and efficiency. While much research has been conducted on GaNdevices, the discussion of third-quadrant operation is limited.Furthermore, the merits of GaN transistors, particularly their fastswitching speed and low on-resistance, make them suitable forswitched-capacitor circuits. This paper demonstrates the abilityof a GaN transistor to function as a synchronous rectifier in aswitched-capacitor circuit. A 500 W GaN-based voltage doublercapable of achieving zero-current switching is presented withsupporting experimental results. This circuit achieves peak effi-ciencies of 97.6% and 96.6% while switching at frequencies of 382and 893 kHz, respectively.

Index Terms—DC–DC converter, gallium nitride (GaN),HEMTs, resonant power conversion, switched-capacitor circuit,zero-current switching (ZCS).

I. INTRODUCTION

POWER SWITCHING devices created from wide bandgap(WBG) devices are actively being researched to realize

the next generation of power conversion hardware [1]–[14]. Inparticular, gallium nitride (GaN) and silicon carbide (SiC) haveseveral properties that offer advantages over existing silicon(Si) technology. For instance, the bandgaps (Eg) of both GaN(3.44 eV) and SiC (3.26 eV) are about three times higher thanthat of Si (1.12 eV). This enables WBG devices to operateat higher temperatures when compared to their Si counter-parts [1]–[5]. Furthermore, the critical electric fields of GaN(3.0 MV/cm) and SiC (3.26 MV/cm) are an order of magni-tude greater than that of Si (0.3 MV/cm), and this translatesinto higher breakdown voltages for similar drift region spac-ing (i.e., gate-to-drain spacing) or lower specific on-resistance

Manuscript received February 13, 2012; revised May 13, 2012; acceptedJuly 7, 2012. Date of publication March 27, 2013; date of current versionMay 15, 2013. Paper 2012-IPCC-052.R1, presented at the 2011 IEEE EnergyConversion Congress and Exposition, Phoenix, AZ, USA, September 17–22,and approved for publication in the IEEE TRANSACTIONS ON INDUSTRY

APPLICATIONS by the Industrial Power Converter Committee of the IEEEIndustry Applications Society. This work was supported by the NationalScience Foundation through Project 1054479.

M. J. Scott and J. Wang are with the Department of Electrical and ComputerEngineering, The Ohio State University, Columbus, OH 43210 USA (e-mail:[email protected]; [email protected]).

K. Zou was with the Department of Electrical and Computer Engineering,The Ohio State University, Columbus, OH 43210 USA. He is now with FordMotor Company, Dearborn, MI 48126-2798 USA (e-mail: [email protected]).

C. Chen, M. Su, and L. Chen are with Ford Motor Company, Dearborn,MI 48126-2798 USA (e-mail: [email protected]; [email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TIA.2013.2255252

for devices of comparable voltage rating [1]–[5]. Both GaN(2.0× 107 cm/s) and SiC (2.5× 107 cm/s) also have a highersaturation velocity when compared to Si (1.0× 107 cm/s) andshould therefore be able to reach higher switching speeds [2].

Given these considerations, WBG devices should enablethe design of power conversion hardware that achieves higherpower densities and better efficiencies over those createdwith Si. Two separate demonstrations of conversion hardwarebased on GaN devices have been able to achieve efficien-cies exceeding 99%: a 760 W boost converter [6] and a900 W three phase inverter [7]. In addition, a 5 kW SiCphotovoltaic inverter has been demonstrated that realizes upto four times greater power density over similar rated Siimplementations [8].

An emerging application for these materials is in renewableenergy systems where aims to improve the efficiency are beingheavily pursued [9]. Photovoltaic (PV) panels and fuel cells,which are ubiquitous in these systems, operate at voltage levelsin the range of 20–45 V, which is more favorable to currentlyavailable GaN devices. Additionally, volume is a premium inhardware such as microinverters; the smaller footprint of theEfficient Power Conversion’s (EPC) device has an advantageto that of other commercially available WBG devices. Whatis more, the EPC-1010, which has the highest voltage ratingamong currently available EPC devices, has a typical on-resistance of 18 mΩ [10], and this is four times lower than thatof available SiC devices [11]. For these reasons, GaN devicesare being investigated. Already, EPC’s devices are being evalu-ated in PV applications designed for microconverters [12] andmicroinverters [13], [14].

One of the challenges presented in grid-tie applications is theneed for high-boost-ratio converters to interface low-voltagedc sources, such as PVs and fuel cells, with inverters usedin these systems [15]. An approach to achieving this highboost ratio is to cascade a voltage multiplier with a boostconverter to improve efficiency [16]. In addition, switched-capacitor multipliers have been used to generate the dc link forrenewable energy applications [14]. This paper presents a high-frequency GaN-based switched-capacitor voltage doubler to beused in these types of circuits.

Switched-capacitor circuits using GaN devices are one areain need of investigation. In high-speed circuits, magnetic com-ponents are becoming the major road block. While new GaNdevices can switch at 1 MHz and above with reduced switchingloss, it is difficult to find suitable magnetic cores, particularlyfor high-power applications. Thus, switched-capacitor circuitsare an attractive application for WBG devices [17], [18].While there are many efforts in new topologies and controls

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1384 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 49, NO. 3, MAY/JUNE 2013

TABLE IDEVICE PARAMETERS FOR TECHNOLOGY EVALUATION

for switched-capacitor circuits, adapting GaN devices in thesecircuits has not yet been widely studied.

The third-quadrant operation of GaN transistors and theirapplication in synchronous rectification (SR) are another areain need of further research. In [7], third-quadrant operation(i.e., SR) was demonstrated for the commutation current ina GaN-based three-phase inverter circuit, but the discussionof this mode of operation was limited. The doubler presentedin this paper relies on the third-quadrant capabilities of theGaN device to improve the efficiency of the circuit. Thus, thismechanism should be better understood.

The structure of this paper is as follows. Section II comparesthe merits of GaN against those of Si. Section III provides anoverview of the third-quadrant operation and presents the I–Vcurves for reverse current flow. In Section IV, the analysis ofa soft-switching modular switch-capacitor voltage doubler isdiscussed. The design of a GaN switched-capacitor circuit andits performance are shown in Section V. An eGaN FET fromEPC (EPC-1010 [10]) is used in this research.

II. GALLIUM NITRIDE COMPARISON

A. Device Model

Several models have been proposed to evaluate GaN tran-sistors in various applications [2], [19], [20]. From a circuitdesigner’s perspective, a normally off GaN transistor is quitesimilar to a Si MOSFET [2]. Both are voltage control de-vices that inherently have parasitic capacitances between theterminals. Each device is able to conduct third-quadrant cur-rent; however, the mechanism is different as is explained inSection III. In addition, the on-resistance in both devices hasa positive temperature coefficient. These similarities enable theuse of many of the same equations used when evaluating SiMOSFETs.

B. Comparison Among Competing Technologies

Table I compares the EPC-1010 against Si MOSFETs fromInternational Rectifier and Infineon to evaluate the theoreticaladvantages of using GaN devices in a high-power switched-capacitor application. The basis for this comparison was thatthe device be rated for 200 V. From there, a device with eithersimilar current rating (IRFU13N20D [21]), comparable sizepackage (BSZ12DN20NS3 [22]), and/or better on-resistance(RDS_ON) (IPB107NA [23]) was selected.

Table I summarizes the parameters that are relevant to theproposed topology [18]. Several of the values were not given

TABLE IIPOWER LOSS BREAKDOWN

directly in the data sheet. For example, the output capacitanceand forward voltage are estimated from the figures in the datasheet. Reverse recovery charge is calculated based on the linearinterpolation of the data provided. The switching speeds arecalculated from the switching times given in the data sheet andthe voltage level at which the test was performed. EPC does notdirectly publish switching speeds for the EPC-1010. Therefore,the value in [24] was used for this comparison.

A breakdown of the different loss mechanisms is given inTable II. The conduction losses are determined by multiplyingthe RDS_ON by the rms current. Both the output capacitance(COSS) and the gate charge (QG) are used to evaluate theswitching losses. Third-quadrant operation is evaluated byconsidering the forward voltage (VF ) and reverse recoverycharge (QRR). For the following analysis, it is assumed thatthe operating voltage is 55 V, the switching frequency is400 kHz, and the rms current is 6 A.

The fact that the EPC device does not have a QRR associatedwith it is apparent. This ends up being the dominant formof loss for each of the Si devices. Even if these losses areignored, the EPC device still operates more efficiently underthese conditions.

III. THIRD-QUADRANT OPERATION

A. Background

Third-quadrant current has two different paths to flowthrough in a Si MOSFET. When the gate-to-source voltage(VGS) is below the threshold voltage (VTH), current flowsthrough the p-n junction (i.e., body diode) created by p-base andn-drift regions that form the parasitic bipolar junction transistorfound in power MOSFETs [9]. During this time, the voltagedrop across the source to drain (VSD) can be as high as 1.6 V[25]. However, if VGS is much greater than VTH, the current canflow through the channel of the device. In this case, VSD will bedetermined by

VSD = ISD · RDS_ON. (1)

SCOTT et al.: GALLIUM NITRIDE SWITCHED-CAPACITOR CIRCUIT USING SYNCHRONOUS RECTIFICATION 1385

Fig. 1. EPC-1010 third-quadrant I–V characteristics (T = 23.7 ◦C).

Current flow across the p-n junction of the body diodeinvolves minority carriers, so the QRR is needed to return thedevice to a blocking state. Even with SR, this charge cannotbe eliminated because deadtime between switching cycles isrequired in most power converters.

Third-quadrant current moves through EPC’s eGaN FETdifferently than the Si MOSFET. As the drain voltage dropsbelow the gate voltage, electrons begin to gather under the gate.Once the gate-to-drain voltage exceeds the threshold voltage(VGD > 1.5 V), the channel will be activated, and current willbe able to move through the device [2].

All conduction, aside from leakage currents, flows within the2-D electron gas, regardless of the direction. With no minoritycarriers involved in this process, there is no associated QRR

with EPC devices [2]. This is particularly relevant becausethe rapid di/dt experienced during the reverse recovery periodcan cause oscillation among the parasitic components in acircuit, which can lead to electromagnetic interference (EMI)and additional power loss.

One disadvantage to the lateral GaN device, when comparedto a Si MOSFET, is the higher VF that is seen across thechannel. Since it is the VTH that induces the formation of thechannel, the VF of an eGaN FET is 1.8 V at 0.5 A and willincrease with higher levels of current [10].

B. Third-Quadrant Characteristics of the EPC-1010

The third-quadrant characteristics of the EPC-1010 weremeasured using an Agilent B1505A curve tracer along withthe associated N1259A test fixture. Tests were conducted witha gate bias from 0 to 5 V. The maximum drain current waslimited to 6 A. Fig. 1 shows the results from this testing atroom temperature (T = 23.7 ◦C). As the VGS increases, theVSD corresponding to a given ISD decreases; thus, one is ableto lower the voltage drop across the source-to-drain connectionby applying a gate bias during reverse current flow.

The RDS_ON for this test is obtained by calculating theinverse of the slope for the data corresponding to the 5-V gatebias. For the room temperature test, RDS_ON is equal to 15 mΩ,which is the same value given for the first quadrant operationat VGS = 5.0 V [21]. This test was also performed at 50 ◦C,

Fig. 2. DC–DC voltage doubler based on two half cells.

and it was found that the voltage drop across the GaN deviceincreased at the higher temperature. The RDS_ON for thiscase was 16.2 mΩ. The normalized RDS_ON provided at thistemperature is approximately 1.1 [10], which is in agreementwith the results. This is a modest increase when compared to Sidevices. As pointed out in [2], Si devices have a significantlyhigher positive temperature coefficient.

IV. SWITCHED-CAPACITOR CIRCUIT

A. Circuit Overview

Fig. 2 shows the topology of the dc–dc voltage doubler thatenjoys the benefits of minimized output capacitance and soft-switching capability [18]. It is created from the interconnec-tion of two half switching cells, also called Marx cells [26].The stray inductance from the associated printed circuit board(PCB) traces (LSX) is utilized to achieve zero-current switching(ZCS). In this topology, the location of the dc source and thatof the load can be interchanged to achieve different types offunctionality. For this application, the dc source is placed in themiddle, so the switches in the two cells experience the samecharging current stress.

Figs. 3 and 4 show the two switching states and their asso-ciated current waveforms for this converter. During State I, thecapacitor C1 is charged by the dc source through S1 and S2,while in the right cell, S6 connects capacitor C2 in series withthe dc source, which effectively doubles the output voltage. InState II, S3 is turned on in the left cell, and C1 is connectedin series with the dc source to achieve the voltage doublingfunction. S4 and S5 are on in the right cell, and C2 is chargedby the dc source.

A single control signal and its compliment are required tooperate this circuit. The duty ratio is fixed by the circuit pa-rameters, C1, C2, LS1, LS2, LS4, and LS5. With a symmetricallayout and C1 equal to C2, a 50% duty cycle can be used tocontrol this circuit.

Switches S2 and S4 operate in the third quadrant, while thetwo other eGaN FETs in the capacitor charging loop (S1 and S5)operate in the first quadrant. It can be seen in Figs. 4(b) and 5(b)that S1 and S5 carry just the capacitor charging current (IC),while the two third-quadrant-operated switches (S2 and S4)need to carry both IC and the load current (IOUT). The shape ofIC results from the stray inductance of the capacitor charging


Fig. 3. (a) Equivalent circuit for State I and (b) associated current waveforms.

loop oscillating with either C1 or C2 during each capacitor’srespective charging cycle, which will generate a sinusoidalshaped current. Soft switching is achieved by selecting theswitching frequency that results in the switches turning off atthe zero crossing of the charging current IC . Thus, S1 and S5are able to achieve ZCS. For S2 and S4, the remaining load cur-rent freewheels through the “body diodes” of the eGaN FETsduring the deadtime between switching transitions. Therefore,they turn off under a minimized voltage condition and realizezero-voltage switching (ZVS).

B. Efficiency Estimation

In the following section, the efficiency of the circuit will beanalyzed by considering the conduction losses, the switchinglosses, and the control circuit losses for each switch in theMarx cell. The total loss will be calculated as a function of loadcurrent. The following analysis assumes that the half cells aresymmetrical and a 50% duty cycle is implemented.

1) Conduction Losses on the Switches: Due to the existenceof the loop resistance, the shape of the capacitor charging cur-rent is not purely sinusoidal. In this analysis, it is assumed thatRS and LS represent the loop resistance and stray inductance,respectively, and C represents the capacitance of C1 or C2.Then, the equations of IS1 and IS2 can be written as

IS1(t) =Ae−α1t sinωd1t (2)

IS2(t) =Ae−α1t sinωd1t+ Iout. (3)

In the above equations, the term Asin(ωd1t) reflects theLC oscillation of the capacitor charging loop, in which A and

Fig. 4. (a) Equivalent circuit for State II and (b) associated current waveforms.

ωd1 represent the amplitude and frequency of the oscillation.The term e−α1t reflects the attenuation of the LC oscillationdue to the loop resistance RS . The attenuation factor is equalto α1 = RS/2LS . The damping factor is defined as ς1 =RS/2

√C/LS .

To derive the variable A in (2) and (3), it is recognized thatthe charge supplied to the capacitor C1 during charging equalsthe charge consumed by the load when C1 discharges

T2∫

0

e−α1tA sin(ωd1t)dt =T

2× Iout. (4)

Then, A is solved to be

A =1 + ς21

1 + e−ς1ππIout. (5)

The conduction losses of S1 and S2 are calculated as

P1,CON =1 − e−2ς1π

2π× A2RS1_ON

4(6)

P2,CON =

(1 − e−2ς1π

2π× A2

4

+1 + e−ς1π

1 + ς21

AIoutπ

+I2out

2

)RS2_ON. (7)

For S3, it carries the load current when it is conducting. Theconduction loss is calculated as

P3,CON =I2outRS3_CON

2. (8)


2) Conduction Losses on the Capacitors: There are threetypes of capacitors in the circuit: the input capacitor, the outputcapacitor, and the energy-transferring capacitors (C1 and C2).The output capacitor is for the purpose of smoothing the voltagesag during deadtime and has a much smaller loss than the othercapacitors. As a result, the power loss on the output capacitor isneglected here.

For the energy-transferring capacitor C1, when it is beingcharged, it has the same current as S1. When it is in thedischarging state, it carries the load current Iout. The capacitorlosses on C1 during the charging and the discharging state arecalculated as

Pch,ESR =1 − e−2ς1π

2π× A2RESR

4(9)

Pdis,ESR =I2outRESR

2. (10)

For the input capacitor, it needs to provide the sinusoidal-likecharging current for both the capacitors C1 and C2. At the sametime, it receives dc input current, which equals half the loadcurrent, from the input voltage source. Therefore, the current ofthe input capacitor in half a switching cycle can be expressed as

ICin(t) =

Iout2

−Ae−α1t sinωd1t. (11)

The power loss on the input capacitor can be expressed as

PCin,CON

=

(1 − e−2ςπ

2πA2

4− 1 + e−ςπ

1 + ς2AIoutπ

+I2out

2

)RESR_in. (12)

3) Switching Losses on the Switches: Each switch in theMarx cell operates under a different type of switching condi-tion. For S1, ZCS is achieved by switching at the moment whenIS1 drops to zero.

For S2, it has a residual current equal to the load current whenit is turned off. However, since it operates in the third quadrant,the current can freewheel during the deadtime, which meansthat ZVS can be achieved. Therefore, the switching power lossis calculated as

P2,SW = IoutVF (Iout)fs(2 · tdeadtime) (13)

where fs is the switching frequency and VF is the forwardvoltage dropped across the device.

For the diagonal switch S3, it is subjected to the highestswitching loss due to fact that it is operated under hard switch-ing. The equation used to calculate the switching loss of S3 isshown as follows:

P3,SW =12IoutVin(ton + toff )fs. (14)

4) Switching Losses on the Output Capacitors of MOSFETs:Since the proposed GaN switched-capacitor voltage doubleroperates at a high switching frequency, the switching loss due tothe charging and discharging of the output capacitance (COSS)of the MOSFETs cannot be neglected.

The energy to charge COSS is

ECOSS=

VDS_PEAK∫0

VDSCOSS(VDS)dVDS (15)

and the power loss is calculated as

PCOSS= ECOSS

fs. (16)

5) Loss Due to the Oscillation Between the Output Capaci-tor of the MOSFET and the Loop Inductor: Since the capacitorcharging loop requires a large stray inductance to achieve softswitching, a large oscillation may be induced by the chargingactivity of output capacitance of the MOSFETs. Power is lostto the nonzero MOSFET current and voltage. A simple LCRequivalent circuit can be used to calculate the power loss due tothis oscillation.

The current and voltage of MOSFET S1 during this oscilla-tion can be expressed as

iS1(t) =Vin

ωd2LSe−α2t sinωd2t (17)

VS1(t) =Vin(1 − e−α2t cosωd2t) (18)

where ωd2 and α2 represent the angular oscillation frequencyand attenuation factor of this oscillation.

The energy loss during half an oscillation cycle can becalculated as

ES1,osc =

TOSC/2∫0

iS1(t)VS1(t)dt =V 2in

ω2L

(1 + e−ς2π

1 + ς22

).

(19)There are multiple oscillations, and the oscillation energy

decreases cycle by cycle with a factor of e−4πς2 , where ς2 isthe damping factor of this oscillation. The total power loss canbe calculated as

PS1,osc =1

1 − e−4πς2ES1,oscfs. (20)

This loss only depends on the input voltage and frequency.It is a constant value under different load conditions with fixedvoltage and frequency, so it represents a large portion of thetotal loss at low-power operation conditions.

6) Gate Drive Losses: Additional power will be requiredfrom the control circuitry to turn the devices on and off. Thepower loss becomes relevant as the switching frequency of thepower converter is increased. This loss can be calculated as

PCOSS= VGSON

QGfs. (21)

V. EXPERIMENTAL RESULTS

A. Circuit Implementation

Fig. 5 shows the initial prototype of the eGaN FETswitched-capacitor voltage doubler, which was realized with sixEPC-1010 devices. The dimensions for this prototype are 4 in


Fig. 5. eGaN FET switched-capacitor prototype.

× 3.125 in × 2 in. Two PCBs were constructed, one for thevoltage doubler topology along with its gate drive circuitry andanother for the housekeeping power supplies and control logic.In Fig. 5, the control board is the one mounted on the top.The no-load power consumption of this board is approximately1.16 W when the GaN devices are not switching.

Driving a normally off eGaN FET is similar to drivinga Si MOSFET in most respects. Both are voltage-controlleddevices, and with the application of a positive gate bias, theyturn on. The differences between driving EPC’s devices anddriving typically Si devices, as well as detailed considerationson layout and gate drive circuitry, are provided in [2], [27],and [28].

In this topology, the GaN device was control by EL-7158pin drivers [29]. The applied gate bias was limited to 4.6 Vvia individually isolated housekeeping power supplies. A gateresistor of 10 Ω was used to minimize the overshoot duringturn-on. Lower power experiments were also conducted with4.7 and 2.7 Ω; however, the overshoot on the Vgs due to strayinductance in the gate drive loop was much more pronounced.Since this was the first version of this board, a second revisionof the PCB would solve this problem by optimizing the gatedrive layout.

The input voltage for this prototype is 55 V, and a nominal110 V is created at the output. Two different experiments wereperformed with this module: one at a frequency of 382 kHzand another at 893 kHz, each exceeding 500 W of input power.The frequencies were selected corresponding to the resonantfrequency created by the energy storage capacitors and the strayinductance. The board had to be altered to produce the differentresonant frequencies for each test. For the 382 kHz test, anadditional wire was inserted into each of the charging loopsto increase LS1 and LS5. During both tests, a 10-μF ceramiccapacitor was connected in parallel with the output to sustainthe load during the deadtime.

The test setup for this experiment is shown in Fig 6. Effi-ciency measurements were made using a Yokogawa WT-3000with a LEM IST UltraSTAB amplifier and two IL700-Scurrent transducers. A Tektronix MSO 4054 was used torecord the switching waveforms with the aid of two differen-

Fig. 6. Setup used to test the eGaN FET switched-capacitor doubler.

Fig. 7. Switching waveforms for 382 kHz operation.

tial voltage probes and two current probes. A Tektronix TPS2024 was used to monitor both the drain-to-source voltageand gate-to-source voltage prior to performing the efficiencymeasurements.

B. Low-Frequency Test (382 kHz)

The first set of tests was performed at a switching frequencyof 382 kHz (see Fig. 7). The input voltage was fixed at55 V. Several different tests were conducted to determine theoptimum deadtime. The value was varied from 25 to 100 ns,and the peak efficiency was achieved using a deadtime of50 ns. The switching waveforms for the full-load test (516 W)are shown in Fig. 7. It can be seen that the devices turnedoff as the charging currents (IC1 and IC2) reach zero, therebyachieving soft switching at full-load conditions.

Fig. 8 shows the results for the efficiency testing. The con-verter achieved a peak efficiency of 97.6% at 209 W. Theefficiency at 516 W was 96.4%. The difference in the estimatedand the measured power loss at higher power levels is due to thefact that 25 ◦C was used in the estimate. However, during thetest, the temperature of the GaN devices was higher than this.


Fig. 8. Converter efficiency operating at 382 kHz.

Fig. 9. Switching waveforms for 893 kHz operation.

C. High-Frequency Test (893 kHz)

A second test was conducted at a frequency of 893 kHz.The load was varied from 60 to 480 W. The input voltagewas 55 V, and the output was measured at 103 V. The dropin output voltage is due both to the converter losses as wellas the deadtime being significant with respect to the switchingfrequency. The switching waveforms for the 480-W test areshown in Fig. 9. The peak efficiency was 96.6% at a 145-Woutput power, and the efficiency at 480 W was 94.4%.

D. System Efficiency

As was mentioned earlier, each of the three switches issubjected to a different type of stress. The two switches in thecharging loop suffer mainly conduction losses, and the switchthat conducts only the load current is subjected primarily toswitching loss.

In Fig. 2, there are four numbers denoting the critical pointsin a half cell. In the PCB layout, the traces between points 1 and4 and the traces between points 2 and 3 have similar size andlength. As a result, the resistance associated with these tracesis assumed to be identical. With this assumption, the RDS_ON

Fig. 10. Power loss breakdown for converter under 382-kHz operation.

of the switches can be combined together with the equivalentseries resistance (ESR) of C1 and C2 to simplify the estimation.For example, by knowing the charging-loop resistance, thetotal resistance of the equivalent series resistance (ESR) of C1

and the RDS_ON of S1 can be represented by half the loopresistance. And since C1 and S1 have the same conduction lossequation during the time when C1 is in the charging state, theirassociated conduction loss can be calculated together, withoutknowing their respective resistance.

At different switching frequencies, the PCB trace resistancechanges following the rules of skin effect. In order to accuratelyestimate the power loss, the loop resistance is measured fordifferent frequency conditions. The measurement took placeat an input voltage of 5 V, where the capacitance of theceramic capacitors is close to their rated value. The chargingcurrent data were recorded at a sampling frequency of 2.5 GHz.From the equation of the charging current (2), the followingrelationship exists between the sampling current at time t andt+ T0:

IS1(t+ T0)

IS1(t)= e−α1T0

sinωd1(t+ T0)

sin(ωd1t). (22)

By knowing T0 and ωd1, α1 can be solved for, and thedamping factor can be found. The loop resistance can then becalculated by knowing ωd1, the capacitance, and the dampingfactor.

The measurement result is that both charging loops of S1 andS5 have a loop resistance of 110 mΩ at 382 kHz. The dampingfactor associated with the charging loop is 0.35.

Fig. 8 shows the estimated power loss together with the mea-sured power loss for 382 kHz operation under a load of 400 W.It can be seen that the efficiency is higher than 96% for most testpoints. Fig. 10 shows the detailed breakdown of the power loss.It can be seen that the conduction losses on the switches andcapacitors are the dominant factors in the power loss. With aSi MOSFET which has much higher on-resistance, the powerloss would be significantly increased.


VI. CONCLUSION

The emergence of WBG power devices will continue to openup new fields of research for the power electronics designer. SRis one area where the GaN devices could be heavily utilized.This paper examined the third-quadrant capabilities of theEPC-1010 and demonstrated that the application of a gate biaswill lower the voltage drop across the source-to-drain terminalsduring reverse current flow.

This knowledge was applied in the application of an eGaNFET switched-capacitor prototype. The unit successfully dou-bled an input voltage of 55 V while carrying a load exceeding500 W. In addition, high-frequency power conversion wasdemonstrated by converting the 480 W at a switching frequencyof 893 kHz. The prototype further demonstrates that eGaNFETs can be used as synchronous rectifiers at low-power levels.

ACKNOWLEDGMENT

The authors would like to thank the manufacturing and engi-neering staff at Vanner Inc. for their assistance in fabricating theprinted circuit boards for this project. In particular, the authorswould like to thank A. Cook, B. Porter, and B. Whittington forthe help provided. The authors would also like to thank Effi-cient Power Conversion for the technical support, specificallyA. Lidow, S. Colino, and B. Nair. In addition, the authors wouldlike to thank their labmates L. Fu, J. Li, Y. Shao, and X. Fangfor the help provided.

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Mark J. Scott (S’09) received the B.S. degree inelectrical and computer engineering in 2005 fromThe Ohio State University, Columbus, OH, USA,where he is currently working toward the Ph.D.degree in electrical and computer engineering.

He has worked as a Field Engineer installing largeindustrial automated systems and as a Test Engineervalidating power electronics for automotive appli-cations. His research is focused on utilizing widebandgap devices in new and existing power elec-tronic topologies for renewable energy applications.

Mr. Scott is a founding member of the IEEE Graduate Student Body at TheOhio State University and a member of Tau Beta Pi.


Ke Zou received the B.S. and M.S. degrees fromXi’an Jiaotong University, Xi’an, China, in 2005and 2008, respectively, and the Ph.D. degree fromThe Ohio State University, Columbus, OH, USA,in 2012.

He is currently with Ford Motor Company,Dearborn, MI, USA. His research topics includeswitched-capacitor dc/dc converters and dc/ac mul-tilevel inverters, battery models in high-frequencyapplications, and wide bandgap devices.

Jin Wang (S’02–M’05) received the B.S. degree inelectrical engineering from Xi’an Jiaotong Univer-sity, Xi’an, China, in 1998, the M.S. degree in elec-trical engineering from Wuhan University, Wuhan,China, in 2001, and the Ph.D. degree in electricalengineering from Michigan State University, EastLansing, MI, USA, in 2005.

From September 2005 to August 2007, he waswith Ford Motor Company as a Core Power Elec-tronics Engineer and contributed to the traction drivedesign of the Ford Fusion Hybrid. Since September

2007, he has been an Assistant Professor with the Department of Electrical andComputer Engineering, The Ohio State University, Columbus, OH, USA. Histeaching position is cosponsored by American Electric Power, Duke/Synergy,and FirstEnergy. His research interests include high-voltage and high-powerconverters/inverters, integration of renewable energy sources, and electrifica-tion of transportation. He has over 50 peer-reviewed journal and conferencepublications and is the holder of two patents.

Dr. Wang was the recipient of multiple teaching and research awards,including the Ralph L. Boyer Award for Excellence in Undergraduate TeachingInnovation from the College of Engineering of The Ohio State University in2012, the IEEE Power Electronics Society Richard M. Bass Young EngineerAward in 2011, and the National Science Foundation CAREER Award in 2011.He has been an Associate Editor for the IEEE TRANSACTIONS ON INDUSTRY

APPLICATION since March 2008.

Chingchi Chen received the Ph.D. degree in elec-trical engineering from the University of Wisconsin,Madison, WI, USA, in 1994.

Since then, he has been with the Ford Re-search Laboratories, Dearborn, MI, USA, leadingpower electronics research for on-vehicle applica-tions. He has been working in various areas ofpower electronics for automotive applications, in-cluding topology evaluation, dynamic analysis, re-liability assessment, and package design. Recently,his focus has been on electromagnetic compatibil-

ity (EMC) of on-vehicle power electronic systems, developing models forEMC characteristics prediction, and methodologies for early EMC problemdiagnosis.

Ming Su received the B.E. degree in electronic en-gineering from Tsinghua University, Beijing, China,in 2002, and the M.S. and Ph.D. degrees in elec-trical engineering from Rutgers University, NewBrunswick, NJ, USA, in 2006 and 2010, respectively.

Since 2010, he has been with Research andAdvanced Engineering, Ford Motor Company,Dearborn, MI, USA, where he is a Research Engi-neer for hybrid electric vehicle (HEV) drive systems.His current research interests include device physics,manufacturing technologies, and application criteria

of silicon and wide-bandgap power semiconductor devices for the HEV tractioninverter system.

Lihua Chen received the B.S.E.E. and M.S.E.E.degrees from Changchun University of Science andTechnology, Changchun, China, in 1993 and 1996,respectively, and the Ph.D. degree from MichiganState University, East Lansing, MI, USA, in 2008.

Currently, he is with Ford Motor Company,Dearborn, MI, USA, as a Technical Expert respon-sible for HEV traction inverter design. From 1999 to2002, he was with Argonne National Laboratory asa Visiting Researcher, and before that, he was withChangchun University of Science and Technology as

an Assistant Professor for three years.