F
IGURES
FOR
C
HAPTER
10
Figure 10-1
Basic oscillator configuration.
+Vin Vout
Vf
HA( )ω
HF( )ω
Vin
V1 V2 = VoutHA( )ω
HF( )ω
(a) Closed-loop circuit model (b) Network representation
Figure 10-2
Output voltage versus gain characteristic.
| |VoutVQ
HQ
HA0
Negative slope(negative resistance)
Figure 10-3
Series resonance circuit with voltage-controlled source term.
R L C
v i( )+−
i t( )
Figure 10-4
Tunnel diode oscillator circuit and its small-signal model.
R L
+
R L
–g CT
LS
RS
Tunneldiode
VCC
(a) Tunnel diode oscillator circuit (b) Small-signal equivalent circuit
Figure 10-5
Feedback circuits with Pi- and T-type feedback loops.
HA( )ω
Z1 Z2Z3
HA( )ω
Z1 Z2Z3
Vout VoutV1V1
(a) Pi-type feedback (b) T-type feedback
Figure 10-6
Feedback oscillator with FET electric circuit model.
Z3
Z1 Z2– µVV1
RB
IB
V1 V2
+
−
Table 10-1
Various feedback configurations for oscillator designs based on Figure 10-5(a)
Hartley
X1 X2,
X3
Z1 Z2Z3
L1 L2
C3 C1 C2L3
C1 C2L3C3
Colpitts
Clapp
Figure 10-7
Hartley and Colpitts oscillators.
L2 C3L1
GS
DCB
CB
RDRA
VDD
RS CSRB
GS
DCB
CB
RDRA
VDD
RS CSRB
C2 L3C1
(a) Hartley oscillator (b) Colpitts oscillator
Figure 10-8
Common gate, source, and drain configurations.
S
G
D
Z1
Z3
Z2
S
GD
Z1
Z3
Z2 S
GD
Z1
Z3
Z2
(a) Common gate (b) Common source (c) Common drain
Figure 10-9
Colpitts oscillator design.
B C
E E
V1 V2
h11 h22–1
V h2 12 I1h21/h22
C1 C2
L3
I3
I1 I2
+−
Figure 10-10
Quartz-resonator equivalent electric circuit representation.
Cq
C0
Lq Rq
Figure 10-11
Susceptance response of a quartz element.
10-4
10-3
10-5
10-6
10-7
10-8
10-9
10-10
10-2
10-1
0.9 0.94 0.98 1.02 1.06 1.1Frequency , MHzf
Sus
cept
ance
||,
BΩ
Seriesresonance
Parallelresonance
Figure 10-12
Sourced and loaded transistor and its flow chart model.
BJT
11
(FET) Load
ΓS Γout
Γin ΓL
bS
S 21
S 12
S11
VS
ZS
S22ΓSΓL
(b) Equivalent signal flow graph
(a) Sourced and loaded transistor
Figure 10-13
Network representation of the BJT with base inductance.
LPositivefeedbackloop
Figure 10-14
Rollett stability factor (
k
) as a function of feedback inductance in common-base configuration.
–0.5
–0.6
–0.7
–0.8
–0.9
–1.00 0.4 0.8 1.2 1.6 2.0
Rol
lett
sta
bili
ty f
acto
rk
Feed-back inductance , nHL
Figure 10-15
Input stability circle for the oscillator design.
Cinr in
Unstable region
Figure 10-16
Series-feedback BJT oscillator circuit.
RFC RFC
VEE VCC
BFQ65
CB 0.48 nH13 Ω 50 Ω
4.3 pF
ΓS ΓL
Γout
Figure 10-17
GaAs FET oscillator implementation with microstrip lines.
RFC RFC
VDD = 3 VVSS = 0.65 V
CB
50 Ω
CB
TL1
TL2
TL3A TL3B
TL4
TL5
ATF13100
TL6
Figure 10-18
Stability factor for FET in common-gate mode as a function of gate inductance.
0 0.4 0.8 1.2 1.6 2.0
Rol
lett
sta
bili
ty f
acto
rk
Feedback inductance , nHL
0.8
0.4
0
0.6
0.2
–0.2
–0.4
–0.6
–0.8
–1
Table 10-2
Dimensions of the transmission lines in the FET oscillator
Transmission line Electrical length, deg. Width, mil Length, mil
TL1 80 74 141
TL2 48.5 74 86
TL3 67 74 118
TL4 66 74 116
Figure 10-19
Dielectric resonator (DR) placed in proximity to a microstrip line.
Enclosure
Field coupling region
Microstrip line
Tuningscrew
DR
Substrate
d
Figure 10-20
Placement of DR along a transmission line and equivalent circuit representation for
S
-parameter computation.
θ1
d
θ2
50 Ω
50 ΩZ = 50 0 Ω Z0 Z0
R
L
C
(a) Terminated microstrip line with DR (b) Transmission line model
Figure 10-21
Input stability circle of the FET in the DRO design example.
Stable region
Figure 10-22
DR-based input matching network of the FET oscillator.
Z0 Z0R
L
C
Dielectric resonator
Θ = 85° Θ = 85°
R = 50T Ω
CB
Figure 10-23
Frequency response of the output reflection coefficient for an oscillator design with and without DR.
Frequency ,f GHz
Out
put r
efle
ctio
n co
effi
cien
t, |
|Γ o
ut
7.98 7.985 7.99 7.995 8 8.005 8.01 8.015 8.02 8.025
14
12
10
8
6
4
2
0
Frequency ,f GHz
Out
put r
efle
ctio
n co
effi
cien
t, |
|Γ o
ut
14
13
12
11
10
9
8
7
6
55.5 6 6.5 7 7.5 8 8.5 9 9.5 10 10.5
(a) Oscillator design with DR
(b) Conventional oscillator without DR
Figure 10-24
Oscillator design based on a YIG tuning element.
RLYIGMatchingnetwork
Figure 10-25
Varactor diode oscillator.
C1
L3C2
C3
RL
CB
RFC
C1
L3
C2
C3
RL
(a) Pi-type feedback loop (b) Redrawn circuit with DC isolation
Figure 10-26
Circuit analysis of varactor diode oscillator.
C1
L3 C2
C3
RL
h11
βiB
ZT
ZIN
C1
L3 Z0
C2
C3
RLVIN
iBiIN
Figure 10-27
Gunn element and current versus voltage response.
Goldencontact
n
n+
Metal Anode
Cathode
active layer(10 . . . 20 µm)
V0
Imax
V
I
(a) Gunn element structure (b) Current vs. applied voltage response
Figure 10-28
Gunn element oscillator circuit with dielectric resonator (DR).
VB
biasvoltage
CB
CBRFC
DR
λ/4
Gunnelement
Figure 10-29
Heterodyne receiver system incorporating a mixer.
LNA Combiner Detector
Mixer
fLO
fIF
fRF
fLO fRF ± fLOfRF
LP Filter
Figure 10-30
Basic mixer concept: two input frequencies are used to create new frequencies at the output of the system.
VIN
VRF
VLO
VOUT ZL
Figure 10-31
Spectral representation of mixing process.
V ( )LO ω
ωωLO
(b) LO signal
V ( )RF ω
ωω ωRF W–
ωRF ω ωRF W+
(a) RF signal
V ( )out ω
ωω ωRF LO– ω ωRF LO+
(c) Down- and upconverted spectral products
Figure 10-32
Problem of image frequency mapping.
VRF
ω
VLO
ω
ωRF
ωLO
ωIF ωIF
ωIM
Undesiredimage signal
VIF
ωωIF
Figure 10-33 Two single-ended mixer types.
VRF (t)
VLO (t)
+VQ
CL fIF
(a) Diode mixer
VRF (t)
VLO (t)
fIF
(b) FET mixer
Figure 10-34 Conversion compression and intermodulation product of a mixer.
Pout (dBm)
1 dB
POIP3
P1 dB
PIIP3Pin (dBm)
Third order intercept point
Real vs. curveP Pout in
Ideal vs. curveP Pout in
1 dB compression point
0 dBm
Small-signalgain in dB
Third harmonic
Figure 10-35 General single-ended mixer design approach.
fRF
fLO
Inputmatchingnetwork
Activedevice
DC biasingnetwork
Outputmatchingnetwork fIF
Short circuitfor IF
Short circuitfor RF
Figure 10-36 DC-biasing network for BJT mixer design.
RFC1 RFC2
CB
CB
R1
R2
IB IC
VCC = 4 V
VCE = 3 V
Z fin RF( )=(77.9 – j130.6)Ω Z fout IF( ) = (677.7 – j2324)Ω
VBE = 0.89 V
IC = 2.2 mAIB = 30 µΑ
Figure 10-37 Connection of RF and LO sources to the BJT.
RFC1 RFC2
CB
CB
R1
R2 = 448 Ω
VCC
70.3 kΩ
fRF
fIFZRF = 50 Ω
ZLO = 50 Ω
fLO
CLO
ΓLO
ZL = 50 Ω
Figure 10-38 Input matching network for a single-ended BJT mixer.
RFC1 RFC2
CB
R1
R2 = 448 Ω
VCC
70.3 kΩ
fRF
fIF
ZLO
CLO
C1
L1
CB1
Input matchingnetwork
Figure 10-39 Modified input matching network.
RFC2
CB
R1
R2
VCC
fRF
fIF
ZLO
CLO
C1
L1
CB1
Input matchingnetwork
Figure 10-40 Complete electrical circuit of the low-side injection, single-ended BJT mixer with fRF = 1900 MHz and fIF = 200 MHz.
R1
R2
VCC
fRF
fIF
CLO
C1
L 1
CB1
Input matchingnetwork
fLO
CB2
L 2
C1
C3
Output matchingnetwork
fRF blockingcapacitor
Figure 10-41 Balanced mixer involving a hybrid coupler.
fRF
fLO
fIF
90° branch linecoupler
Figure 10-42 Single-balanced MESFET mixer with coupler and power combiner.
fRF
fLO
fIF
90° branchline coupler
Inputmatchingnetwork
Inputmatchingnetwork
Wilkinsonpower
combiner
Outputmatchingnetwork
Outputmatchingnetwork
180°phaseshift
Figure 10-43 Double-balanced mixer design.
fIF
fRFfLO
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