© Keysight Technologies 2018. All rights reserved. 5992-3405EN. October 11, 2018

400GE FEC Encode/Decode ProcessingThe IEEE 802.3bs Task Group defines specifications for 400 Gigabit per second (Gb/s) Ethernet, where forward error correction (FEC) is mandatory. See how a 400GBASE-R Reed-Solomon RS-544 (KP4 FEC) encode/decode works in operation. Note that FEC encoding/decoding takes place at the binary level before the physical layer.

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TRANSMIT PATH

RECEIVE PATH

Transmit Transcoder

Reduces line encoding overhead

Gearboxing facilitates FEC symbol boundaries

IEEE 802.3bs specifies 16 PCSlanes across both 400GAUI-16

& 400GAUI-8 electrical interfaces

256b/257b scrambled 256b/257b

Pre-FECSymbol Distributor

Symbol = 10 bits

PCS Lane

TransmitMAC

Scrambler

Self-synchronizes, ensures no long runs of 1s & 0s

Different markers are created for eachof the 16 PCS lanes

64/66

64/66

64/66

64/66

64/66 bit Codewords...

Alignment Marker Group Insertion

......

...

257

320 FEC a

KP4 FEC Encoding

30 check symbols are calculated & inserted

per FEC codeword

FEC CodewordInterleaving

& Distribution

FEC b

012

...

14

13

12.........

...

...

...

3...

15...

Gray Encoder

0

1

7

8

8 PAM4 Lanesat 53 Gb/s

to PHY Transmitter

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0

1

7

8

Receive Transcoder

Expands bit stream to original

64/66b format

Self-synchronizing, reconstitutes

original bit stream

Descrambler

256b/257bscrambled 256b/257b

012...

151413

PCS Lane

...

...

...

...

...

... 64/66 bit Codewords

Alignment Marker Group Removal

Corrects up to 15symbol errors per FEC

codeword

KP4 FEC Decoding

PCS Alignment

Marker Lock, Deskew, and Reorder process

...

257

320

FEC De-interleaving

Corrected FEC

Codeword Interleaving

FEC a

FEC b

AlignmentLock StateMachine

DeskewFIFO

AlignmentLock StateMachine

ReorderMUX

ReceiveMAC

DeskewFIFO

012

...

14

13

12.........

...

...

3...

15...

InverseGray Encoder

8 PAM4 Lanesat 53 Gb/s

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PHYReceiver