Taking semiconductors
to the next level
TIERLOGIC
3D FPGA & 3D ASICWorlds first unified 3D IC design platform
Hot Chips, August 2010 ©2010 Tier Logic - Public
Raminda Madurawe
2D FPGA dilemma
• Large programming overhead
Longer wires = degradation
Removing overhead = 2nd design
Hot Chips 2010 2
0.0
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20406080100120140160180200
AR
EA
(µ
2)
C/S
RA
M R
AT
IO
CRAM & SRAM scaling
CRAM
SRAM
RATIO
• 20 years of SRAM scaling
CRAM > memory SRAM
Stability / disturb at 28nm?
CRAM = configuration SRAM
©Tier Logic - Public
25µ
65µ
MUX
C-RAM
Xilinx XC2VP7 photo
25µ
65µ
MUX
C-RAM
25µ
65µ65µ
MUX
C-RAM
Xilinx XC2VP7 photo
Buffer
2D FPGA
3D Product concepts
2D FPGA
User Logic
Circuit
Configuration
SRAMConfiguration
SRAM
TierFPGA™
User Logic
Metal layer
TierASIC ™
Hot Chips 2010 3©Tier Logic - Public
• 2D FPGA – poor area, cost, power, speed
• 3D FPGA – better area, power, cost, speed
– Same placement / wires / base die 3D ASIC™
– One design – one timing closure – FPGA/ASIC options
Hot Chips 2010 4
Static Control
Vd
d
Vss
TierFPGA• TFT SRAM
TierASIC• Metal ROM
MultiASIC™• TFT MUX
0 1
©Tier Logic - Public
Base dieDynamic
Signals
One bitstream
= identical timing
= deterministic
“Bitstream” timing closure
Monolithic process
• Metal ROM over CMOS
– FPGA fabric / FPGA tools
– “Bitstream” custom M9
Hot Chips 2010 5
• TFT SRAM/MUX over CMOS
– FPGA fabric / FPGA tools
– Temperature < 400 ⁰C
©Tier Logic - Public
Thin-film-transistors (TFT)
Hot Chips 2010 6
Silicided Gate
Silicided S/D
Gate TEOSGate Spacer
a-Si Channel
• 9-TFT SRAM cell
– < 10µW static / 106 bits
– ION / IOFF stable & durable
• N/P thin-film transistors
– Majority carrier
– Accumulation mode
©Tier Logic - Public
TFT SRAM latches
Hot Chips 2010 7
• Static circuits
• VT not critical
• Low power
©Tier Logic - Public
E-field scalable
Hot Chips 2010 8
1.E-13
1.E-11
1.E-09
1.E-07
0 20 40 60
Lateral E-Field (V/µ)
NTFT OFF CURRENT
AM
PS
1.E-10
1.E-09
1.E-08
1.E-07
1 10 100
Lateral E-Field (V/µ)
NORMALIZED NTFT ON CURRENT
AM
PS
• 90nm CMOS – TFTs operate at 3.3V
• 45nm CMOS – TFTs operate at 1.8V
• Scale with CMOS
©Tier Logic - Public
Improving gate density
2D FPGA
3D FPGA
FPGA
Low ROI IC’s
Tru3D
FPGA
ASSP / ASIC
Competition 2010 2012 ?
• Approach ASIC gate density
• Improved mobility switch fabric –
laser crystallization
Configuration
Switches
User Logic
Hot Chips 2010 9©Tier Logic - Public
Competitive evolution
• Multi-faceted
technology evolution
3.5x 3D FPGA
7x Tru3D
• Programmability – as
needed – iterative
• Fixed function – when
satisfied
• All future ICs will need
programmability
• 56 issued patents
UN
IT C
OS
T
Hot Chips 2010 10©Tier Logic - Public
4LUT gate density2D FPGA 4LUT
density: follow
Moore’s Law
• 180nm = 110/mm2
(FY2000)
• 20nm ~ 4500/mm2
(FY2013)
• 6 nodes ~ 40x
3D gives higher
4LUTs
• 28 nm = 16k /mm2
(FY2013)
Hot Chips 2010 11©Tier Logic - Public
Tier Logic
90
nm
_3
D
45
nm
_3
D
45
nm
_T
3D
28
nm
_T
3D
Routing architecture
Hot Chips 2010 12
Area:
CR = CRAM
LO = Logic
RO = Routing
©Tier Logic - Public
ARCHITECTURE 2D FPGA ASIC2D FPGA
(No CR)
3D FPGA
(3D CR)
Logic cell area 1 e = 0.208 f = 0.313 g = 1
Wires / area N N N N
RO per wire 0.6 / N 0.4 / N 0.6 / N 0.665 / N
LO area 0.125 0.125 0.125 0.335
RO area RO1 = 0.6 RO2 = 0.4*e RO3 = 0.6*f RO4 = 0.665
Area (RO+LO+CR) 1=CR+LO+RO1 e=LO+RO2 f=LO+RO3 g=LO+RO4
LO ratio to 2D 1.0 4.8 3.2 2.7
LO Efficiency 1 6 1 1.4
User LO / area 1 28.8 3.2 3.8
LO =
0.335
RO4 = 0.665
LO =
0.125
RO3 = 0.60*f
LO =
0.125
RO2 = 0.4*e
LO =
0.125
CR = 0.275
RO1 = 0.600
area=1 area=e area=f area=1
Unified tools
Existing FPGA Viciciv RTL Designs Device
Existing FPGA → Tier LogicRTL Designs Device
Hot Chips 2010 13©Tier Logic - Public
• FPGA RTL design entry
Mentor “Precision” synthesis
Tier Logic “Mobius” P&R
• One tool – one placement
“Bitstream” for FPGA
“M9 mask” for ASIC
• Excellent quality of results
• Combining tools, design &
process
FPGA design for ASICs
14
FPGA RTL
T0
Synthesis
~ 1 day
Timing ?
~ 2 days
Fabrication
~ 4 weeks
Samples
T ~ T0 + 6W
• FPGA verified RTL
• Standard front end tools
– No re-design
– TierFPGA to re-verify (if necessary)
– Pin compatible TierASICs (6 weeks + $50k)
Hot Chips 2010 ©Tier Logic - Public
Hot Chips 2010 15
Die stack vs. monolithic
Reference: 3rd Stanford and Tohoku Universities joint Open Workshop on 3D
Transistors and its Applications December 2009
• FPGA’s need > 90% area
for wires
• 40nm 2D CRAM bit
density ~ 90M /cm2
Requirement for Via
> 1B /cm2
©Tier Logic - Public
Hot Chips 2010 16
Summary
• Unified IC design for FPGA & ASIC
– Beyond process scaling
– “Bitstream” concept to IC design
• Worlds first monolithic 3D FPGA
– Same “netlist / placement / base-die” → 3D ASIC – Fine grain for logic & course grain for routing
• Augment programmability to ASIC density
– High mobility 3D nTFT switches
taking semiconductors to the next level
©Tier Logic - Public
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