2006.10.25. A. Matsuzawa, Tokyo Tech. 1
Nano-scale CMOS and Low Voltage Analog to Digital Converter
Design Challenges
Akira Matsuzawa
Tokyo Institute of Technology
2006.10.25.
A. Matsuzawa, Tokyo Tech. 2
Contents
1. Introduction
2. Effect of technology scaling on analog performance
--- Performance analysis of pipeline ADC ---
3. Design challenges for ADC in nano-scale era
--- No use of Operational amplifier --
- Comparator controlled current source - Successive approximation ADC - Sub-ranging ADC
4. Summary
2006.10.25.
A. Matsuzawa, Tokyo Tech. 3
Performance and applications
6 8 10 12 14 16
Resolution (bits)
Co
nve
rsio
n R
ate
(MH
z)
0.1
1
10
100
1000
5
3050
300500
0.5
0.05
HDD/DVDGraphics
Audio
GeneralPurpose
DVC/DSC/Printer
Video/Communication
Servo
(µ-Computer)
Automobile
Meter
Pipeline ADC
Pipeline ADC is the major conversion architecture for communications and digital consumer products.
2006.10.25.
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Pipeline ADC
-
-+
+
Op amp
CMPDAC
-
-+
+
Op amp
CMPDAC
-
-+
+
Op amp
Sample & Hold 1st stage 2nd stage
Amplify (Hold) Sample Amplify
Cf
Cs
Cf
Cs
1st stage
2nd Stage
Sample Amp. Sample Amp.
Sample Amp. Sample Amp.
Transfer characteristics
Hold Sample Amplify
-Vref
+Vref
-Vref
+Vref
0 1
X2
-Vref
+Vref
-Vref
+Vref
0 1 0 1
X2
1st Stage 2nd Stage
Folding I/O characteristics makes higher resolution along with pipeline stages.
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Speed and power
High Speed ADC[Sampling Freq. VS Power]
1
10
100
1000
10000
1 10 100 1000 10000
Sampling Freq.[MSps]
Power[mW]
12Bit(Paper)10Bit(Paper)12Bit Products10Bit Products.
J SSC,ISSCC,VLSI,CICC,ESSCC & Products(≧10Bit,≧10MSps)1995-2006
MHzmWbit /3.0:10
MHzmWbit /1:12
10b12b
Conversion speed has saturated at 200 MHz Smaller mW/MHz is needed for low power operation.0.3mW/MHz for 10bit and 1mW/MHz for 12bit are the bottom lines.
200MHz
2006.10.25. A. Matsuzawa, Tokyo Tech. 6
Effect of technology scaling on analog performance
Technology scaling
and performance of pipeline ADC
2006.10.25.
A. Matsuzawa, Tokyo Tech. 7
Operating voltage trend
0
1
2
3
4
10
100
2002 2004 2006 2008 2010 2012 2014 2016
Op
erat
ing
vo
ltag
e
(V)
Des
ign
ru
le
(nm
)
Design RuleAnalog High
Analog Low
Digital Low (Low leak)
Digital High
ITRS 2003
ITRS 2001
About 1V operation
Operating voltage of scaled device will keep about 1V
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Operational amplifier for ADC
Vin+
vout-vout+
2Veff
Vs=Vdd-4Veff
2Veff
Vin-
Vdd
Output signal rangeGain
Boost amp.
Pipeline ADC needs high performance amplifier.The output signal range will be reduced along with voltage lowering.
Vs=Vdd-0.7V
Vs=0.5V @Vdd=1.2VVs=0.3V @Vdd=1.0V
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Requirements for operational amplifier
-
-+
+
Op amp
Cf
Cs Cp
Vout
VDAC
Vn
Vn
-
-+
+
Op amp
Cf
Cs
VinVn
Vn
Sampling
Amplify
GC
C
GG
f
perror
12
1
f
p
C
C2
1
106)( NdBG
N:ADC resolutionM: Stage resolution
1MN2G1
for 1.5b pipeline ADC
DC gain
pisf
f
CCC
C
β
pisf
pisfoLpoL CCC
CCCCCC
3fcN
C2g
GBWL
mclose_
πβ
Closed loop gain-bandwidth
Higher resolution requires higher open loop gain.Higher conversion frequency requires higher closed loop GBW.
2006.10.25.
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kT/C noise
R
CL
Larger SNR requires larger capacitance and larger signal swing.Low signal swing increases required capacitance.
CL
vout
φ
vn
0.1 1 10 10050
60
70
80
90
10095.918
51.938
SNRC 1 2 C
SNRC 2 2 C
SNRC 3 2 C
SNRC 5 2 C
1000.1 C
14bit
12bit
10bit
0.1 1 10 100
VFS=5V
VFS=3V
VFS=2V
VFS=1V
n=2
SN
R (
dB)
Capacitance (pF)
CkT
2d
CR1
1kTR4v
22n
CnkT
v2n n: configuration coefficient
nkTCV
dBSNR FS
8log10)(
2
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Ids GBW- 特性
0.00E+00
2.00E+09
4.00E+09
6.00E+09
8.00E+09
1.00E+10
1.20E+10
0.0E+00 5.0E- 04 1.0E- 03 1.5E- 03 2.0E- 03
Ids[A]
GBW[Hz]
90nm(CL=100fF) 90nm(CL=200fF)0.25μ m(CL=100fF) 0.25μ m(CL=200fF)
Effect of technology scaling
GBW: 10GHz
GBW: 2GHz
Conversion freq. : 1GHz
Conversion freq. : 200MHz
90nm
0.25um
Gain bandwidth of OpAmp increases along with technology scaling.However, can we increase every needed performances for ADCs?
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M5
Vbp2
Vbp1
VoutnVoutp
Vbn1
Vbn2
Vdd
VinpVinn
Vbp1
Technology scaling for analog
M5
Vbp2
Vbp1
VoutnVoutp
Vbn1
Vbn2
Vdd
VinpVinn
Vbp1
elVsig arg:
SignalCap.
ParasiticCap.
ParasiticCap.
ParasiticCap.
ParasiticCap. Parasitic
Cap.
ParasiticCap.
smallVsig :
SignalCap.
Technology scaling
Technology scaling can reduce parasitic capacitances.However signal capacitance will increase to keep the same SNR at lower voltage operation.
Parasitic capacitance smallerOperating voltage lowerSignal swing lower
Signal capacitance largerVoltage gain lower
2006.10.25.
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Performance model for pipeline ADC
Cf
Cs Cpi gm Cpo COLRL2
1
1
p
sω
OpAmpofpoleSecond
ceresisOutputR
cecapaciLoadC
cecapaciparaciticputputinputCC
loopfeedbackforcecapaciSignalCC
stageinputofcecTranscondug
p
L
oL
popi
fs
m
:
tan:
tan:
tan&:,
tan:,
tan:
2ω
βπ L
mclose C
gGBW
2_
pisf
f
CCC
C
β
pisf
pisfoLpoL CCC
CCCCCC
2fs
oL
CCC
oLfso CCCC
OpAmp
o
dspi
o
dspo
o
dspieffo
ds
o
pi
o
po
o
pio
mclose
C
I
C
I
C
IVC
I
C
C
C
C
C
CC
gGBW
112
1
112
1
2_ ππ
A. Matsuzawa, “Analog IC Technologies for Future Wireless Systems,” IEICE, Tan on Electronics, Vol. E89-C, No.4, pp. 446-454, April, 2006.
We have developed the performance model for pipeline ADC that can treat technology scaling.
2006.10.25.
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Scaling and analog device and circuit parameters
μ
ds2effox
IVC
L2W
(b)Cpi_N, Cpi_P,Cpo[fF/mA],ωp2_N,ωp2_P[GHz]
(a)WN,WP[μm/mA],VA_N, VA_P[V]
D
G
S
B
gdC dbC
gsC sbC
dbC
dsI
Veff=0.175V
DR
DR
DR
L[μm]0.1 0.2 0.3 0.4 0.51
10
100
1000
Cgd
Cgs
Cap
. [fF
/mA
],f T
[GH
z]W
[μm
/mA
]
fT
W
2/1 SS: Scaling factor
Gate width and capacitances decrease with technology scaling.
2006.10.25.
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Determination of signal capacitance
90nm 0.13μm 0.18μm 0.25μm 0.35μm
Vdd 1.2V 1.5V 1.8V 2.5V 3.3V
Vsig_pp 1.0V 1.6V 2.2V 3.6V 5.2V
2
19 21066.1
sig
N
o VC
DR[μm]
0.001
0.01
0.1
1
10
100
1000
0.1 0.50.05
Co[
pF]
8bit
10bit
12bit
14bit
Vin+
vout-vout+
2Veff
Vdd-4Veff
2Veff
Vin-
Vdd
Output signal range
Gain Boost amp.
Larger resolution requires larger signal capacitance.Furthermore, Voltage lowering increases signal capacitance more.
2006.10.25.
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10
100
1000
10000
0.01 0.1 1 10Ids[mA]
fc[MHz]
90nm 0.13μ m 0.18μ m 0.25μ m 0.35μ m
Performance curve
o
pi
o
po
o
pio
mclose
C
C
C
C
C
CCg
GBW
112
12_ π
①Co≫Cpo,Cpi
)(・π ds
effo
dsclose I�
VCI
GBW 31
_
dsopodsipieff
dsm IC�IC�
VI
g ,,2
②Cpi<Co < Cpo
) (α
・π
tConsVC
GBWoeffo
close tan311
_
③Co < Cpo 、 Co < Cpi
)(αα
・π dsdsoieffo
close I�
IVCGBW
13
11_
①
③②fFCo 50
Performance exhibits convex curve.There is the peak conversion frequency and the optimum current. Current increase results in increase of parasitic capacitances and decrease of conversion frequency in the higher current region.
2006.10.25.
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1
10
100
1000
10000
0.01 0.1 1 10Ids[mA]
fc[MHz]
90nm 0.13μ m 0.18μ m 0.25μ m 0.35μ m
8 bit
0.13μm 90nm
0.13um attains highest conversion frequency in a low current region.However 90nm is over striding 0.13um along with increase of the current.
2006.10.25.
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0.25μm
1
10
100
1000
10000
0.01 0.1 1 10Ids[mA]
fc[MHz]
90nm 0.13μ m 0.18μ m 0.25μ m 0.35μ m
10 bit
0.35μm 0.18μm 0.13μm 90nm
The best design rule depends on operating current.0.35um attains highest conversion frequency in low operating current region!
2006.10.25.
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0.1
1
10
100
1000
0.01 0.1 1 10Ids[mA]
fc[MHz]
90nm 0.13μ m 0.18μ m 0.25μ m 0.35μ m
12 bit
0.35μm 0.25μm 0.18μm
Relaxed design rule is suitable for wider current range.
2006.10.25.
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14 bit
0.01
0.1
1
10
100
0.01 0.1 1 10Ids[mA]
fc[MHz]
90nm 0.13μ m 0.18μ m 0.25μ m 0.35μ m
Scaled CMOS is not suitable for higher resolution ADC.
2006.10.25.
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Performance summary
12bit
1
10
100
1000
10000
0.01 0.1 1 10Ids[mA]
fc[MHz]
90nm 0.13μ m 0.18μ m 0.25μ m 0.35μ m
8 bit1
10
100
1000
10000
0.01 0.1 1 10Ids[mA]
fc[MHz]
90nm 0.13μ m 0.18μ m 0.25μ m 0.35μ m
10bit
0.1
1
10
100
1000
0.01 0.1 1 10Ids[mA]
fc[MHz]
90nm 0.13μ m 0.18μ m 0.25μ m 0.35μ m
12bit0.01
0.1
1
10
100
0.01 0.1 1 10Ids[mA]
fc[MHz]
90nm 0.13μ m 0.18μ m 0.25μ m 0.35μ m
14bit
Scaled CMOS is effective for just low resolution ADC.Scaled CMOS is not effective for high resolution ADC.
2006.10.25.
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Voltage gain
dsmi rgG ds
Ads
eff
dsm I
Vr
VI
g ,2
Aeff
Ai V
VV
G 102
LV operation
LV operation
VA decreases with scaling and operating voltage lowering.High gain can not be expected.
NMOS PMOS
2006.10.25.
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Voltage gain of operational amplifier
Vin+
vout-vout+Vin-
Gain Boost amp.
VVV effds 2.0
dBVV
Geff
Ai 20
2.022
20dB
20dB40dB
Total gain is 80dB @max
Voltage gain of OpAmp for scaled CMOS and LV operation is 80dB at most.
Less than 10 bit ADC can be designed with scaled and low voltage CMOS.
2006.10.25. A. Matsuzawa, Tokyo Tech. 24
Design challenges for ADC in nano-scale era
--- No use of Operational amplifier --
- Comparator controlled current source - Successive approximation ADC - Sub-ranging ADC
2006.10.25.
A. Matsuzawa, Tokyo Tech. 25
Isink
R R
Isink
R R
effoxj
ksin
oxj
m
VLWC32
WC2
I
LWC32
WC2
gGBW
2eff
oxksin V
LW
2C
I
L
Cox
k
C
32
L2
VGBW
j2
eff
0
5
10
15
20
0.1 0.2 0.3 0.4 0.5
Re
lati
ve
ba
nd
wid
th
Feature size ( )m
0
5
10
15
20
0.1 0.2 0.3 0.4 0.5
Re
lati
ve
ba
nd
wid
th
Feature size ( )mFeature size ( )m
Design rule and Speed in Comparator
Gain bandwidth (=Speed) is inversely proportional to the L2 (channel length).Technology scaling is still effective to increase the comparator speed and to reduce operating current.Furthermore, low voltage operation, such as 0.5V, is available.
2006.10.25.
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Comparator controlled current source
Vx is reaching the virtual ground voltage asymptotically
Conventional OpAmp
Vx is reaching the virtual ground voltage with constant rate
Comparator controlled current source
T. Sepke, J. K. Fiorenza, C. G. Sodini, P. Holloway, and H. Lee, “Comparator-Based Switched-Capacitor Circuits For Scaled CMOS Technologies,” IEEE, ISSCC 2006, Dig. of Tech. Papers, pp. 574-575. Feb. 2006.
Comparator controlled current source can realize the virtual ground.
Now challenge for not use of OpAmp in ADC design has started.
2006.10.25.
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Realistic comparator controlled current source
+
_
C1
C2
AGND
VxE1
E2
I1
I2
Vo
Vx
Vo
Vo(n-1)
Vo(n)
Vxo
AGND
E1 E2
I2<< I1
T. Sepke, J. K. Fiorenza, C. G. Sodini, P. Holloway, and H. Lee, “Comparator-Based Switched-Capacitor Circuits For Scaled CMOS Technologies,” IEEE, ISSCC 2006, Dig. of Tech. Papers, pp. 574-575. Feb. 2006.
Time delay (Vx Vo) causes voltage offset. Small inverse current source has been introduced. The offset voltage can be reduced and does not effect the conversion linearity.
10b, 8MHz ADC has been developed.Pd=2.5mW. Lowest Pd/MHz
2006.10.25.
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Successive approximation ADC
C C2
C4
C8
C16
C16
Vin Vref
C C2C2
C4C4
C8C8
C16C16
C16C16
Vin Vref
Binary weighted Capacitor array Comparator RAM
RAM
WR
WR
DATA
DATA
ADC 1
ADC 8
Vin+
Vin-
Refhi
Clkbuf
Reflo
Start
Start
Clk RD
RD
OUT
D. Draxelmayr, “A 6b 600MHz 10mW ADC Array in Digital 90nm CMOS,” IEEE, ISSCC 2004, Dig. of Tech. Papers, pp. 264-265, Feb. 2004.
Eight interleaved SA-ADCs with 90nm CMOSattain 600MHz operation.
Successive approximation ADC
SA-ADC
Successive approximation ADC has been used long time as a low power and low speed ADC. It doesn’t require OpAmp but capacitor array and comparator. Thus this architecture looks suitable for scaled and low voltage CMOS.
Now challenge for renewal of this conventional architecture has started.
2006.10.25.
A. Matsuzawa, Tokyo Tech. 29
Improvement of SA-ADC
Tracking Phase
Tracking Phase
MSB MSB-1 MSB-2 LSB
MSB MSB-1 MSB-2 LSB
Synchronous Conversion Phase
Asynchronous Conversion Phase
Sampling Instants
Sampling Instants
To comparatorVcm
Cu
Cu
Cu
Cu Cu
Cu CuCu
Cu
VinVcmVrefpVrefn
LSB MSB 1radix
1
S. W. M. Chen and R. W. Brodersen, “A 6b 600MS/s 5.3mW Asynchronous ADC in 0.13um CMOS,” IEEE, ISSCC 2006, Dig. of Tech. Papers, pp. 574-575. Feb. 2006.
6bit 600MHz 5.3mW ADC has been realized with 0.13um CMOS
Asynchronous clock increases conversion frequency.Use of proper radix reduces capacitance.
Capacitor ladder with some radix number
Asynchronous clock
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Sub-ranging ADC
Vdd
Vss
C1
C1
C2C2
S3 S3
S1S1
S2S2
VaVa
Vin-Vin+
Coarse ADC(CADC)
Fine ADC(FADC)
Reference ladder
Switch matrix
Encoder
Vin
Vr
Vr
63
2
7
6.6
12
7]Y. Shimizu, S. Murayama, K. Kudoh, H. Yatsuda, A. Ogawa, “ A 30mw 12b 40MS/s Subranging ADC with a High-Gain Offset-Canceling Positive-Feedback Amplifier in 90nm Digital CMOS,” IEEE, ISSCC 2006, Dig. of Tech. Papers, pp. 222-225. Feb. 2006.
Sub-ranging ADC also doesn't require OpAmp and suitable for LV operation.However it requires low offset voltage comparators. Use of positive feedback technique has realized low offset voltage.
Positive Feedback
CKT
Pd/MHz =0.75mW/MHz which is lowest value!!
Technology revival has been found.
2006.10.25.
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Summary• Technology scaling is effective for increasing analog performance if not so
much higher SNR is required.
• Technology scaling is not effective for increasing analog performance if higher SNR is required, and sometimes degrades it.
• Increase of signal capacitance to keep the SNR high at low voltage operation is essential serious issue for use of scaled CMOS.
• Furthermore, Gain lowering of OpAmp due to technology scaling and voltage lowering becomes serious issues.
• Design challenges for ADC has been started.
• No use of OpAmp is a common idea.
• Technology revivals have been found and the performance has been improved. Further improvement will be expected in future.
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