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![Page 1: Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 10.1 EE4800 CMOS Digital IC Design & Analysis Lecture 10 Combinational Circuit Design Zhuo Feng.](https://reader035.fdocuments.net/reader035/viewer/2022062321/56649da75503460f94a92e8c/html5/thumbnails/1.jpg)
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
10.10.11
EE4800 CMOS Digital IC Design & Analysis
Lecture 10 Combinational Circuit DesignZhuo Feng
![Page 2: Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 10.1 EE4800 CMOS Digital IC Design & Analysis Lecture 10 Combinational Circuit Design Zhuo Feng.](https://reader035.fdocuments.net/reader035/viewer/2022062321/56649da75503460f94a92e8c/html5/thumbnails/2.jpg)
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
10.10.22
Outline■Bubble Pushing■Compound Gates■Logical Effort Example■Input Ordering■Asymmetric Gates■Skewed Gates■Best P/N ratio■Pseudo-nMOS Logic■Dynamic Logic■Pass Transistor Logic
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Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
10.10.33
Example 11) Sketch a design using NAND, NOR, and NOT gates.
Assume ~S is available.
Y
D0S
D1S
![Page 4: Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 10.1 EE4800 CMOS Digital IC Design & Analysis Lecture 10 Combinational Circuit Design Zhuo Feng.](https://reader035.fdocuments.net/reader035/viewer/2022062321/56649da75503460f94a92e8c/html5/thumbnails/4.jpg)
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
10.10.44
Bubble Pushing■ Start with network of AND / OR gates■ Convert to NAND / NOR + inverters■ Push bubbles around to simplify logic
► Remember DeMorgan’s Law
Y Y
Y
D
Y
(a) (b)
(c) (d)
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Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
10.10.55
Example 22) Sketch a design using one compound gate
and one NOT gate. Assume ~S is available.
Y
D0SD1S
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Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
10.10.66
Compound Gates■ Logical Effort of compound gates
ABCD
Y
ABC Y
A
BC
C
A B
A
B
C
D
A
C
B
D
2
21
4
44
2
2 2
2
4
4 4
4
gA = 6/3
gB = 6/3
gC = 5/3
p = 7/3
gA =
gB =
gC =
p =
gD =
YA
A Y
gA = 3/3
p = 3/3
2
1YY
unit inverter AOI21 AOI22
A
C
DE
Y
B
Y
B C
A
D
E
A
B
C
D E
gA =
gB =
gC =
gD =
2
2 2
22
6
6
6 6
3
p =
gE =
Complex AOI
Y A B C Y A B C D Y A B C D E Y A
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Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
10.10.77
Compound Gates■ Logical Effort of compound gates
ABCD
Y
ABC Y
A
BC
C
A B
A
B
C
D
A
C
B
D
2
21
4
44
2
2 2
2
4
4 4
4
gA = 6/3
gB = 6/3
gC = 5/3
p = 7/3
gA = 6/3
gB = 6/3
gC = 6/3
p = 12/3
gD = 6/3
YA
A Y
gA = 3/3
p = 3/3
2
1YY
unit inverter AOI21 AOI22
A
C
DE
Y
B
Y
B C
A
D
E
A
B
C
D E
gA = 5/3
gB = 8/3
gC = 8/3
gD = 8/3
2
2 2
22
6
6
6 6
3
p = 16/3
gE = 8/3
Complex AOI
Y A B C Y A B C D Y A B C D E Y A
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Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
10.10.88
Example 3■ The multiplexer has a maximum input capacitance of 16
units on each input. It must drive a load of 160 units. Estimate the delay of the NAND and compound gate designs.
Y
D0S
D1S
Y
D0SD1S
H = 160 / 16 = 10B = 1N = 2
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Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
10.10.99
NAND Solution
Y
D0S
D1S
2 2 4
(4 / 3) (4 / 3) 16 / 9
160 / 9
ˆ 4.2
ˆ 12.4
N
P
G
F GBH
f F
D Nf P
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Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
10.10.1010
Compound Solution
4 1 5
(6 / 3) (1) 2
20
ˆ 4.5
ˆ 14
N
P
G
F GBH
f F
D Nf P
Y
D0SD1S
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Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
10.10.1111
Example 4■Annotate your designs with transistor
sizes that achieve this delay.
6
6 6
6
10
10Y
24
12
10
10
8
8
88
8
8
88
25
25
2525Y
16 16160 * (4/3) / 4.2 = 50 160 * 1 / 4.5 = 36
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Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
10.10.1212
Input Order■ Our parasitic delay model was too simple
► Calculate parasitic delay for Y falling▼ If A arrives latest? 2▼ If B arrives latest? 2.33
6C
2C2
2
22
B
Ax
Y
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Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
10.10.1313
Inner & Outer Inputs■ Outer input is closest to rail (B)■ Inner input is closest to output (A)
■ If input arrival time is known► Connect latest input to inner terminal
2
2
22
B
A
Y
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Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
10.10.1414
Asymmetric Gates■ Asymmetric gates favor one input over another■ Ex: suppose input A of a NAND gate is most critical
► Use smaller transistor on A (less capacitance)► Boost size of noncritical input► So total resistance is same
■ gA = 10/9
■ gB = 2
■ gtotal = gA + gB = 28/9
■ Asymmetric gate approaches g = 1 on critical input■ But total logical effort goes up
Areset
Y
4
4/3
22
reset
A
Y
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Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
10.10.1515
Symmetric Gates■ Inputs can be made perfectly symmetric
A
B
Y2
1
1
2
1
1
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Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
10.10.1616
Skewed Gates■ Skewed gates favor one edge over another■ Ex: suppose rising output of inverter is most critical
► Downsize noncritical nMOS transistor
■ Calculate logical effort by comparing to unskewed inverter with same effective resistance on that edge.
► gu = 2.5 / 3 = 5/6
► gd = 2.5 / 1.5 = 5/3
1/2
2A Y
1
2A Y
1/2
1A Y
HI-skewinverter
unskewed inverter(equal rise resistance)
unskewed inverter(equal fall resistance)
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Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
10.10.1717
HI- and LO-Skew■ Def: Logical effort of a skewed gate for a particular
transition is the ratio of the input capacitance of that gate to the input capacitance of an unskewed inverter delivering the same output current for the same transition.
■ Skewed gates reduce size of noncritical transistors► HI-skew gates favor rising output (small nMOS)► LO-skew gates favor falling output (small pMOS)
■ Logical effort is smaller for favored direction■ But larger for the other direction
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Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
10.10.1818
Catalog of Skewed Gates
1/2
2A Y
Inverter
1
1
22
B
AY
B
A
NAND2 NOR2
1/21/2
4
4
HI-skew
LO-skew1
1A Y
2
2
11
B
AY
B
A
11
2
2
gu = 5/6gd = 5/3gavg = 5/4
gu = 4/3gd = 2/3gavg = 1
gu = 1gd = 2gavg = 3/2
gu = 2gd = 1gavg = 3/2
gu = 3/2gd = 3gavg = 9/4
gu = 2gd = 1gavg = 3/2
Y
Y
1
2A Y
2
2
22
B
AY
B
A
11
4
4
unskewedgu = 1gd = 1gavg = 1
gu = 4/3gd = 4/3gavg = 4/3
gu = 5/3gd = 5/3gavg = 5/3
Y
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Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
10.10.1919
Asymmetric Skew■ Combine asymmetric and skewed gates
► Downsize noncritical transistor on unimportant input► Reduces parasitic delay for critical input
Areset
Y
4
4/3
21
reset
A
Y
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Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
10.10.2020
Best P/N Ratio■ We have selected P/N ratio for unit rise and fall
resistance ( = 2-3 for an inverter).■ Alternative: choose ratio for least average
delay■ Ex: inverter
► Delay driving identical inverter
► tpdf = (P+1)
► tpdr = (P+1)(/P)
► tpd = (P+1)(1+/P)/2 = (P + 1 + + /P)/2
► Differentiate tpd w.r.t. P
► Least delay for P =
1
PA
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Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
10.10.2121
P/N Ratios■ In general, best P/N ratio is sqrt of that giving
equal delay.► Only improves average delay slightly for inverters► But significantly decreases area and power
Inverter NAND2 NOR2
1
1.414A Y
2
2
22
B
AY
B
A
11
2
2
fastestP/N ratio gu = 1.15
gd = 0.81gavg = 0.98
gu = 4/3gd = 4/3gavg = 4/3
gu = 2gd = 1gavg = 3/2
Y
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Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
10.10.2222
Observations■ For speed:
► NAND vs. NOR► Many simple stages vs. fewer high fan-in stages► Latest-arriving input
■ For area and power:► Many simple stages vs. fewer high fan-in stages
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Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
10.10.2323
■ What makes a circuit fast?► I = C dV/dt -> tpd (C/I) V
► low capacitance► high current► small swing
■ Logical effort is proportional to C/I■ pMOS are the enemy!
► High capacitance for a given current
■ Can we take the pMOS capacitance off the input?
■ Various circuit families try to do this…
B
A
11
4
4
Y
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Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
10.10.2424
Pseudo-nMOS■ In the old days, nMOS processes had no pMOS
► Instead, use pull-up transistor that is always ON
■ In CMOS, use a pMOS that is always ON► Ratio issue► Make pMOS about ¼ effective strength of pulldown network
Vout
Vin
16/2
P/2
Ids
load
0 0.3 0.6 0.9 1.2 1.5 1.8
0
0.3
0.6
0.9
1.2
1.5
1.8
P = 24
P = 4
P = 14
Vin
Vout
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Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
10.10.2525
Pseudo-nMOS Gates■ Design for unit current on output
to compare with unit inverter.■ pMOS fights nMOS
Inverter NAND2 NOR2
AY
B
AY
A B
gu =gd =gavg =pu =pd =pavg =
Y
gu =gd =gavg =pu =pd =pavg =
gu =gd =gavg =pu =pd =pavg =
finputs
Y
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Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
10.10.2626
Pseudo-nMOS Gates■ Design for unit current on output
to compare with unit inverter.■ pMOS fights nMOS
Inverter NAND2 NOR2
4/3
2/3
AY
8/3
8/3
2/3
B
AY
A B 4/34/3
2/3
gu = 4/3gd = 4/9gavg = 8/9pu = 6/3pd = 6/9pavg = 12/9
Y
gu = 8/3gd = 8/9gavg = 16/9pu = 10/3pd = 10/9pavg = 20/9
gu = 4/3gd = 4/9gavg = 8/9pu = 10/3pd = 10/9pavg = 20/9
finputs
Y
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Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
10.10.2727
Dynamic Logic■ Dynamic gates uses a clocked pMOS pullup■ Two modes: precharge and evaluate
1
2A Y
4/3
2/3
AY
1
1
AY
Static Pseudo-nMOS Dynamic
Precharge Evaluate
Y
Precharge
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Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
10.10.2828
The Foot■ What if pulldown network is ON during
precharge?■ Use series evaluation transistor to prevent
fight.
AY
foot
precharge transistor Y
inputs
Y
inputs
footed unfooted
f f
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Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
10.10.2929
Logical Effort
Inverter NAND2 NOR2
1
1
AY
2
2
1
B
AY
A B 11
1
gd = 1/3pd = 2/3
gd = 2/3pd = 3/3
gd = 1/3pd = 3/3
Y
2
1
AY
3
3
1
B
AY
A B 22
1
gd = 2/3pd = 3/3
gd = 3/3pd = 4/3
gd = 2/3pd = 5/3
Y
footed
unfooted
32 2
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Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
10.10.3030
Monotonicity■ Dynamic gates require monotonically rising
inputs during evaluation► 0 -> 0► 0 -> 1► 1 -> 1► But not 1 -> 0
Precharge Evaluate
Y
Precharge
A
Output should rise but does not
violates monotonicity during evaluation
A
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Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
10.10.3131
Monotonicity Woes■ But dynamic gates produce monotonically
falling outputs during evaluation■ Illegal for one dynamic gate to drive another!
AX
Y
Precharge Evaluate
X
Precharge
A = 1
Y should rise but cannot
Y
X monotonically falls during evaluation
AX
Y
Precharge Evaluate
X
Precharge
A = 1
Y
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Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
10.10.3232
Domino Gates■ Follow dynamic stage with inverting static gate
► Dynamic / static pair is called domino gate► Produces monotonic outputs
Precharge Evaluate
W
Precharge
X
Y
Z
A
BC
C
AB
W XY Z =
XZH H
A
W
B C
X Y Z
domino AND
dynamicNAND
staticinverter
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Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
10.10.3333
Domino Optimizations■ Each domino gate triggers next one, like a
string of dominos toppling over■ Gates evaluate sequentially but precharge in
parallel■ Thus evaluation is more critical than precharge■ HI-skewed static stages can perform logic
S0
D0
S1
D1
S2
D2
S3
D3
S4
D4
S5
D5
S6
D6
S7
D7
YH
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Dual-Rail Domino■ Domino only performs noninverting functions:
► AND, OR but not NAND, NOR, or XOR
■ Dual-rail domino solves this problem► Takes true and complementary inputs ► Produces true and complementary outputs
sig_h sig_l Meaning
0 0 Precharged
0 1 ‘0’
1 0 ‘1’
1 1 invalid
Y_h
f
inputs
Y_l
f
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Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
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Example: AND/NAND■ Given A_h, A_l, B_h, B_l■ Compute Y_h = AB, Y_l = AB■ Pulldown networks are conduction
complements
Y_h
Y_l
A_h
B_hB_lA_l
= A*B= A*B
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Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
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Example: XOR/XNOR■Sometimes possible to share transistors
Y_h
Y_l
A_l
B_h
= A xor B
B_l
A_hA_lA_h= A xnor B
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Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
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Leakage■Dynamic node floats high during
evaluation►Transistors are leaky (IOFF 0)
►Dynamic value will leak away over time►Formerly miliseconds, now nanoseconds
■Use keeper to hold dynamic node►Must be weak enough not to fight evaluation
A
H
2
2
1 kX
Y
weak keeper
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Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
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Charge Sharing
■ Dynamic gates suffer from charge sharing
B = 0
AY
x
Cx
CY
A
x
Y
Charge sharing noise
Yx Y DD
x Y
CV V V
C C
A
x
Y
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Secondary Precharge■Solution: add secondary precharge
transistors►Typically need to precharge every other node
■Big load capacitance CY helps as well
B
AY
x
secondaryprechargetransistor
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Noise Sensitivity■Dynamic gates are very sensitive to
noise► Inputs: VIH Vtn
►Outputs: floating output susceptible noise
■Noise sources►Capacitive crosstalk►Charge sharing►Power supply noise►Feedthrough noise►And more!
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Power■Domino gates have high activity factors
►Output evaluates and precharges▼If output probability = 0.5, = 0.5
– Output rises and falls on half the cycles
►Clocked transistors have = 1
■Leads to very high power consumption
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Domino Summary■ Domino logic is attractive for high-speed
circuits► 1.3 – 2x faster than static CMOS► But many challenges:
▼ Monotonicity, leakage, charge sharing, noise
■ Widely used in high-performance microprocessors in 1990s when speed was king
■ Largely displaced by static CMOS now that power is the limiter
■ Still used in memories for area efficiency