XRM-CLINK SDK User Manual V2 - Alpha Data€¦ · XRM-CLINK SDK User Manual 1 Introduction The...

XRM-CLINK SDKUser Manual

Revision: V2.3


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Table Of Contents

1 Introduction ...................................................................................................................................... 1 1.1 Hardware Layer ............................................................................................................................. 2 1.2 Software Layer ............................................................................................................................... 22 Dependancies and Requirements .................................................................................................. 3 2.1 Software ......................................................................................................................................... 3 2.2 FPGA Designs ............................................................................................................................... 3 2.3 Supported Hardware ...................................................................................................................... 33 Example Designs ............................................................................................................................. 4 3.1 XRM-CLINK-MFB-ADB3 ................................................................................................................ 5 3.1.1 Block Diagram ........................................................................................................................... 5 3.1.2 Sub Designs .............................................................................................................................. 6 3.1.3 Main Features ............................................................................................................................ 6 3.1.4 Design Notes ............................................................................................................................. 6 3.1.5 Limitation ................................................................................................................................... 6 3.1.6 Memory Map .............................................................................................................................. 7 3.1.7 Subcomponents ......................................................................................................................... 9 3.1.7.1 ocp_int_controller .................................................................................................................. 9 3.1.7.1.1 Address Map ................................................................................................................... 9 3.1.7.2 clink_adb3 ............................................................................................................................ 10 3.1.7.2.1 adclinkchip_base ........................................................................................................... 11 3.1.7.2.2 clink_pixmap .................................................................................................................. 11 3.1.7.2.3 clink_pix_switch ............................................................................................................. 12 3.1.7.2.4 common_rs232 .............................................................................................................. 12 3.1.7.2.5 clink_cc_ctrl ................................................................................................................... 12 3.1.7.2.6 Address Map ................................................................................................................. 13 3.1.7.3 camera_link_ocp_interface .................................................................................................. 15 3.1.7.3.1 cl3_qual2strobe ............................................................................................................. 15 3.1.7.3.2 cl3_image_pack_4to1 or cl3_image_pack_2to1 ........................................................... 15 3.1.7.3.3 cl3_frame_stamper ........................................................................................................ 16 3.1.7.3.4 cl3_image signal profile ................................................................................................. 16 3.1.7.3.5 adb3_ocp_data_sink ..................................................................................................... 174 Building the FPGA ......................................................................................................................... 18 4.1 MIG Memory Cores ..................................................................................................................... 18 4.2 ISE ............................................................................................................................................... 18 4.3 nmake (Windows Only) ................................................................................................................ 18 4.3.1 Support Designs ...................................................................................................................... 185 Simulation ...................................................................................................................................... 20 5.1 ModelSim ..................................................................................................................................... 20 5.1.1 XRM-CLINK-MFB-ADB3 Testbench ........................................................................................ 20 5.1.1.1 api_application ..................................................................................................................... 20 5.1.1.2 Camera Emulation ............................................................................................................... 21 5.1.1.3 Expected output ................................................................................................................... 216 Extending the FPGA designs ........................................................................................................ 23 6.1 VHDL files .................................................................................................................................... 23 6.2 Project files .................................................................................................................................. 23 6.3 custom_app component .............................................................................................................. 23 6.3.1 MFB-ADB3 custom_app template component ........................................................................ 23 6.3.1.1 cam_data_in/cam_data_out ................................................................................................ 24 6.3.1.2 cio_i_t and cio_o_t ............................................................................................................... 25 6.3.2 Adding registers ....................................................................................................................... 267 API, Applications and Utilities ...................................................................................................... 27 7.1 XRM-CLINK API .......................................................................................................................... 27


7.1.1 ADCommon ............................................................................................................................. 27 7.1.2 ADClink .................................................................................................................................... 27 7.1.3 XIO Viewer ............................................................................................................................... 27 7.2 Building in Windows ..................................................................................................................... 29 7.2.1 Requirements .......................................................................................................................... 29 7.2.2 Build Targets ............................................................................................................................ 29 7.2.3 MSVC ...................................................................................................................................... 29 7.3 Building in Linux ........................................................................................................................... 30 7.3.1 Requirements .......................................................................................................................... 30 7.3.2 Build Targets ............................................................................................................................ 30 7.3.3 Using Command Line .............................................................................................................. 30 7.3.4 Using Netbeans IDE ................................................................................................................ 30 7.4 XRM-CLINK Applications ............................................................................................................. 32 7.4.1 ADCLink Console ..................................................................................................................... 32 7.4.1.1 Command line options ......................................................................................................... 32 7.4.1.2 Configuring the FPGA card .................................................................................................. 32 7.4.1.3 Main menu ........................................................................................................................... 33 7.4.1.3.1 Memory Test .................................................................................................................. 36 7.4.2 clseradl.dll (Windows Only) ..................................................................................................... 378 C++ API ........................................................................................................................................... 38 8.1 API Documentation ...................................................................................................................... 38 8.2 API Quick Start ............................................................................................................................ 38 8.2.1 Preprocessor Symbols ............................................................................................................. 38 8.2.2 Notation ................................................................................................................................... 38 8.2.3 Including the API ...................................................................................................................... 38 8.2.4 Programming the FPGA ........................................................................................................... 39 8.2.5 Attaching a camera .................................................................................................................. 39 8.2.6 Grabbing frames ...................................................................................................................... 40 8.2.7 Working with raw data ............................................................................................................. 40 8.2.8 Region of interest ..................................................................................................................... 40 8.2.9 Using the Camera Link's serial port ......................................................................................... 41 8.2.10 Accessing Registers in an extended FPGA design ................................................................. 41 8.2.11 Debug Output .......................................................................................................................... 429 Regsiter Details .............................................................................................................................. 43 9.1 clink_base_adb3 .......................................................................................................................... 43 9.1.1 Camera Link Control ................................................................................................................ 43 9.1.2 Camera Link Status ................................................................................................................. 43 9.1.3 Camera Link Mode .................................................................................................................. 44 9.1.4 Start Line ................................................................................................................................. 45 9.1.5 End Line ................................................................................................................................... 45 9.1.6 Start Pixel ................................................................................................................................ 45 9.1.7 End Pixel .................................................................................................................................. 46 9.1.8 CC4 High Period ...................................................................................................................... 46 9.1.9 CC4 Low Period ....................................................................................................................... 46 9.1.10 Serial control register ............................................................................................................... 46 9.1.11 Serial clock divider ................................................................................................................... 47 9.1.12 Serial TX Data ......................................................................................................................... 47 9.1.13 Serial RX Data ......................................................................................................................... 47 9.1.14 Serial TX Status ....................................................................................................................... 47 9.1.15 Serial RX Status ...................................................................................................................... 48 9.1.16 Test Pattern Register ............................................................................................................... 48 9.1.17 Pixel Clock Rate ...................................................................................................................... 49 9.1.18 CC Control Register ................................................................................................................. 49 9.1.19 CC1 High Period ...................................................................................................................... 49 9.1.20 CC1 Low Period ....................................................................................................................... 50 9.1.21 CC2 High Period ...................................................................................................................... 50


9.1.22 CC2 Low Period ....................................................................................................................... 50 9.1.23 CC3 High Period ...................................................................................................................... 50 9.1.24 CC3 Low Period ....................................................................................................................... 51 9.1.25 Major Release Version ............................................................................................................. 51 9.1.26 Minor Release Version ............................................................................................................. 51 9.1.27 Major Build Version .................................................................................................................. 51 9.1.28 Minor Build Version .................................................................................................................. 52 9.1.29 Channel Sync Select (Medium/Full Only) ................................................................................ 52 9.2 ocp_int_controller ........................................................................................................................ 53 9.2.1 IRQ Enable .............................................................................................................................. 53 9.2.2 IRQ Clear ................................................................................................................................. 53 9.2.3 IRQ Status ............................................................................................................................... 53 9.3 adb3_ocp_data_sink .................................................................................................................... 54 9.3.1 Control ..................................................................................................................................... 54 9.3.2 Buffer Elements Free Count .................................................................................................... 55 9.3.3 Status ....................................................................................................................................... 55 9.3.4 Dropped Packets Count ........................................................................................................... 56 9.3.5 Buffer Elements IRQ Count ..................................................................................................... 56 9.3.6 Buffer Elements Maximum Count ............................................................................................ 57 9.3.7 Buffer Start Address Lower ...................................................................................................... 57 9.3.8 Buffer Start Address Upper ...................................................................................................... 57 9.3.9 Buffer Elements Size ............................................................................................................... 57 9.3.10 Buffer Elements Write Count ................................................................................................... 58 9.3.11 Buffer Elements Read Count ................................................................................................... 58 9.3.12 Buffer Elements Used Count ................................................................................................... 58 9.3.13 Dropped Packets Free Count .................................................................................................. 5910 SDK Contents ................................................................................................................................. 6011 Migration ......................................................................................................................................... 61 11.1 2.2.2->2.3.x .................................................................................................................................. 6112 Known Issues ................................................................................................................................. 62

List of Tables

Table 1 Direct Slave Memory Map ................................................................................................................. 7Table 2 DMA Channel Memory Spaces .......................................................................................................... 7Table 3 Interrupt Mapping ............................................................................................................................... 7Table 4 Record definition for cl3_image_framing ......................................................................................... 16Table 5 cl3_image_framing flow control ....................................................................................................... 16Table 6 Record definition for cl3_image_framing ......................................................................................... 24Table 7 Preprocessor Symbols ..................................................................................................................... 38Table 8 Debug Masks ................................................................................................................................... 42Table 9 Pixel Bits .......................................................................................................................................... 45

List of Figures

Figure 1 XRM-CLINK SDK Dataflow ................................................................................................................ 1Figure 2 Example FPGA design ....................................................................................................................... 4Figure 3 XRM-CLINK-MFB-ADB3 .................................................................................................................... 5Figure 4 ocp_int_controller I/O Diagram .......................................................................................................... 9Figure 5 adclinkchip_base I/O Diagram ......................................................................................................... 10Figure 6 clink_base_adb3 .............................................................................................................................. 10Figure 7 RoI ................................................................................................................................................... 11


Figure 8 camera_link_ocp_interface I/O Diagram ......................................................................................... 15Figure 9 camera_link_ocp_interface .............................................................................................................. 15Figure 10 adb3_ocp_data_sink I/O Diagram ................................................................................................... 17Figure 11 XRM-CLINK SDK Testbench ........................................................................................................... 20Figure 12 Get video stream ( Visualise ) .......................................................................................................... 35


1 IntroductionThe XRM-CLINK SDK is a set of resources including an application-programming interface (API) and referenceFPGA designs intended to assist the user in creating a Camera Link based application using one of Alpha Data'sADM-XRC range of reconfigurable co-processors with one of Alpha Data's Camera Link XRMs. The provided APImakes use of the ADMXRC2 SDK(for Virtex-5 and earlier FPGA cards) and ADMXRC Gen3 SDK(for Virtex-6 andnewer FPGA cards) to take care of low-level tasks such as: Opening a card, configuring the FPGA, andperforming DMA transfer of frames of data to the local host. The ADMXRC2 or ADMXRC Gen3 SDK(s) may beused in conjunction with this SDK, or instead of the API provided with this SDK if the user desires access towriting their own functions to perform these low-level tasks.

The reference FPGA designs provide simple frame grabbers compatible with acquiring data from Base, Medium,or Full Camera Link camera(s). These designs are a starting point to perform DSP tasks on the images such asfiltering, format conversion, or compression. The designs are also extendible to perform analysis of the inputimage stream(s) on the XRC card where the FPGA may be used to implement a control system reacting to theinput image stream(s).

Bespoke examples can be requested with hardware purchases or quotations (this may add an NRE cost that willvary with the specification of the example design).

The diagram below shows the overall data flow of a system using the XRM-CLINK SDK's API and a referenceFPGA design to acquire image data from one or more Camera Link cameras into a developer's application.

Developer's FPGADesign (Target FPGA)

Bridge FPGA

Camera(s)

Developer’s Software Application

Hardware Layer Software Layer

ADMXRC2 driver

ADMXRC3 driver

Operating System

AlphaData::Common

AlphaData::CLink

XRM-CLINK API

XRM-CLINK Data Flow

Figure 1 : XRM-CLINK SDK Dataflow

Page 1Introductionad-ug-0012_v2_3_CLINK-SDKUserManual.pdf


1.1 Hardware LayerThis layer provides connectivity between Camera Link camera(s) and the Target FPGA. The Target FPGA can beused by the developer to perform their desired image processing task. A Bridge chip is also connected to theTarget FPGA. This provides a connection to the Host system running the Software Layer.

The Hardware Layer of the SDK should be used to perform all processing of the input image. It may be the casein the developer's application that acquisition of images to the Host is not necessary, however for debugging it isrecommend that the developer keeps the capability provided in the example designs of being able to captureimages directly to the Host (pre any processing performed).

1.2 Software LayerThe lowest level of interaction between the Hardware and Software layers take place via the ADMXRC driver.The driver provide the means to monitor interrupts, access the target FPGA as a Direct Slave, and initiate DMA'sbetween the Target FPGA and the Host memory.

Above the driver level the XRM-CLINK SDK provides a c++ software API. This provides two main classes thatcan be used to interact with the Hardware layer provided in the reference designs. These are ACameraCard andACamera. Together these two objects provide functions for low level register reads/writes, managing the serialover Camera Link interface, setting regions of interest when capturing image, configuring the Camera Link IP tointerface with a particular specification of camera, controlling a camera's CC lines, and acquiring raw cameradata from the Target FPGA to host memory.

Two further classes are provided as utilities objects to assist in debugging or displaying images from a cardconfigured with a design based on one of the reference design; CImage and CVideoBuffer. These objectsconvert the raw data captured from the FPGA card into an image that is 8-bits per colour making it suitable fordisplaying on a computer screen. This conversion is performed purely in software, and should only be used forvisualization purposes.

Other utility classes are also provided; for loading and saving acquired data in its raw form, and visuallydisplaying images when running on a GUI based OS.

In addition to the software API a simple raw image viewer application is also provided (XIO Viewer). This is builton the software API, and allows save raw images to be viewed.

Page 2 Introductionad-ug-0012_v2_3_CLINK-SDKUserManual.pdf


2 Dependancies and Requirements2.1 Software

Prerequisites for developing software using the XRM-CLINK SDK are as follows:

OS Requirement

All Operating Systems

Knowledge of C++ programmingKnowledge of the architecture of FPGA design and system it will be used with.Previous experience working with the ADM-XRC Gen 3 SDK or ADM-XRC Gen 2SDK.

Win32ADM-XRC3 Driver for WindowsMSVC 2010

Linux

ADM-XRC3 Driver for LinuxX11GNU g++make

VxWorksADM-XRC3 Driver for VxWorksVxWorks 5.5 or VxWorks 6.x

2.2 FPGA DesignsPrerequisites for developing FPGA designs using the XRM-CLINK SDK are as follows:

OS Requirement

All Operating SystemsKnowledge of VHDL programmingFamiliarity with the Xilinx ISE HDL toolsetXilinx ISE 13.3 (or higher) toolset

Win32 nmake ( Distributed with Microsoft Visual Studio ). For building FPGAs on thecommand line.

2.3 Supported HardwareThe following table shows a list of designs applicable to different XRM and FPGA board combinations supportedin this release.

FPGA Card / XRM XRM2-CAMERALINK XRM2-CLINK-MINI XRM2-CLINK-GIGE

ADMXRC6T1 xrm-clink-mfb-adb3-std xrm-clink-mfb-adb3-dbxrm-clink-mfb-adb3-full xrm-clink-mfb-adb3-gige

ADPEXRC6T . xrm-clink-mfb-adb3-db .

ADPEXRC6TL . xrm-clink-mfb-adb3-db .

In cases where an FMC-CLINK-MINI is being used it should be treated as a XRM-CLINK-MINI for the purposesof the documentation, and designs included in this SDK.

Page 3Dependancies and Requirementsad-ug-0012_v2_3_CLINK-SDKUserManual.pdf


3 Example DesignsThis SDK provides multiple reference FPGA designs supported by the ADCLink API. These designs can be usedas frame grabbers, or modified to perform image-processing or manipulation tasks.

Note: All of the VHDL code in these designs is provided "as is" and may require some modification to work withspecific cameras. The maximum effort has be made for each design to support all Camera Link base formatcameras, should you encounter an issue please contact [email protected], providing details of yourcamera and the issues you are encountering.

The block diagram below shows a standard Alpha Data ADM-XMC FPGA card with either one or two attachedCamera Link cameras via a XRM module. On the left of the diagram the host PCIe interface is indicated. This isconnected to the Bridge which is controlled via the ADMXRC driver and higher level ADCLink API. The Bridgecan be used to perform read or write DMAs directly between the connected Target FPGA and the Host's memoryvia PCIe, as well as providing Direct Slave access to the Target FPGA, and monitoring the interrupt line from theTarget FPGA.

DDR3 Memory

Bridge FPGA Target FPGA

DDR3 Memory

XRM-CAMERALINK, XRM-MINI, or XRM-CLINK-GIGE

Camera Link

Camera

Camera Link

Camera

DDR3 Interface

Camera Link

from Camera

Host

Interrupt

Host

Interface

DDR3 Interface

Host PCIe

FPGA Card

Figure 2 : Example FPGA design

Page 4 Example Designsad-ug-0012_v2_3_CLINK-SDKUserManual.pdf


3.1 XRM-CLINK-MFB-ADB3The MFB, or Multi-Frame Buffer, reference design uses one 256MiB bank of DDR3 RAM on the XRC perCamera Link channel. Each bank in the design is used to buffer multiple frames. This provides a buffer largeenough to allow for irregular transfer rates between the FPGA card and host system.

After the FPGA captures a frame on either channel it interrupts the host informing it that one or more frames areavailable. The FPGA continues filling the remaining buffers interrupting the host when new frames are available.

The API provides the functionally to handle transferring the acquired frames to the Host via DMA and informingthe FPGA that a particular frame has been buffered. If the FPGA runs out of buffers due to the host not beingable to empty them quickly enough the FPGA will start dropping frames until a buffer becomes available.

3.1.1 Block Diagram

The diagram below shows the components that make up the top level of the design. Data flows from the externalcamera(s) into the FPGA where it is deserialised, and converted into a suitable format for further processing. Theimage data is then streamed into a component that can be customised by the developer. After the image data ispassed out of the custom application it is buffered into a small FIFO as it is converted into ADB3_OCPcommands that can be used to write the image data into a large circular buffer instantiated in the off-chipmemory. The memory is also accessible to the host via the bridge and target FPGA design though an OCPmultiplexer instantiated in the top level of the FPGA Target FPGA design. When complete frames are bufferedthe design informs the host using the interrupt controller, and the host with initate a DMA between the memorycontroller connected to the off-chip memory and the Host's Main Memory.

i_clink_base

i_mptl_if_target_wrap

i_adb3_ocp_mux_ram

i_blk_ddr3_if

i_adb3_ocp_l_spliteqi_adb3_ocp_cross_clk_dom i_clink_custom_app

i_camera_link_ocp_interface

i_adb3_ocp_mux_ram

i_blk_ddr3_if

i_int_controller

i_adb3_ocp_full2lite_b

OCP

MASTER

OCP

SLAVE

Camera Link

from Camera

Camera Data

Stream

OCP Lite

MASTER

OCP Lite

SLAVE

Host

Interrupt

Host

Interface

Target FPGA

i_clink_base

Figure 3 : XRM-CLINK-MFB-ADB3

Page 5Example Designsad-ug-0012_v2_3_CLINK-SDKUserManual.pdf


3.1.2 Sub Designs

This design supports a number of variations for the different Camera Link XRMs available. Each sub designname is added to the end of the design name to give a full name, for example xrm-clink-mfb-adb3-std.

Sub Design Description

-std Supports a single Base Camera Link Camera attached to the XRM-CAMERALINKadaptor.

-db Supports two Base Camera Link Camera attached to the XRM-CLINK-MINI adaptor.

-full Supports a single Base, Medium or Full Camera Link Camera attached to the XRM-CLINK-MINI adaptor.

-gigeSupports a single Base Camera Link Camera attached to the XRM-CLINK-GIGEadaptor. Note: It is beyound the scope of this design to support using the ethernetinterface on this XRM.

3.1.3 Main Features

Follow a list of the main features of this design.

- Single or Dual channel image acquisition.

- Each channel can buffer multiple frame without data loss.

- Programmable CC line controller.

- Camera Serial Interface with UART engine.

- Dropped frame counter.

- Frame stamping. Includes time and sequence number.

3.1.4 Design Notes

When using a camera that produces small frames or only capturing a small part of a frame, the efficiency of theDMA operations that move the data to the host can be increased by transferring more than one frame from thecard in one operation, this can be achieved using ACamera::SetFramesInOne function provided in the API.

3.1.5 Limitation

Follows a list of some of the limitations of the design.

- The maximum number of pixels per line is 65535.

- The maximum number of lines per field is 65535.

- The frame size of captured data must be a multiple of 16 bytes.

- The maximum frame size is 128MiBs, for a solution that can cope with larger images please [email protected].



3.1.6 Memory Map

This sections give an overview of the memory map of the MFB design. The direct slave interface from the host isused to access the registers in the design. This 4MiB space is divided into 8 512KiB spaces.

Register Bank PhysicalAddress

32-bit RegisterAddress Description

i_int_controller 0x00000000 0x00000000 Base address of interrupt controller.

i_clink_main, 0 0x00080000 0x00020000 Base address of channel 0 clink_basecomponent.

i_clink_main, 1 0x00100000 0x00040000 Base address of channel 1 clink_basecomponent.

Reserved 0x00180000 0x00060000 Reserved for future use.

i_camera_link_ocp_interface, 0 0x00200000 0x00080000 Base address of channel 0 image capturecomponent.

i_camera_link_ocp_interface, 1 0x00280000 0x000A0000 Base address of channel 0 image capturecomponent.

i_clink_custom_app, 0 0x00300000 0x000C0000 Unused intended for developer's application.

i_clink_custom_app, 1 0x00380000 0x000E0000 Unused intended for developer's application.

Table 1 : Direct Slave Memory Map

Each of the DMA channels attached to the host have their own memory space (in this design only 2 DMAchannels used). Each of these memory space is independent of the Direct Slave memory space.

DMA Channel Low Address High Address Description

0 0x00000000 0x0FFFFFFF Frame buffer for Camera 0 (DDR3 Memory Bank 0).

0 0x10000000 0xFFFFFFFF Unused.

1 0x00000000 0x0FFFFFFF Frame buffer for Camera 1 (DDR3 Memory Bank 1).

1 0x10000000 0xFFFFFFFF Unused.

Table 2 : DMA Channel Memory Spaces

In additional to the memory maps the interrupt controller shares the host interrupt between various interruptsources in the design.

Interrupt Bit Description

0 Channel 0 data sink activity

1 Channel 1 data sink activity

2 Camera 0 RX serial activity

3 Camera 1 RX serial activity

4 Camera 0 de-serialisation status activity

5 Camera 1 de-serialisation status activity

6 Camera 0 TX serial activity

Table 3 : Interrupt Mapping (continued on next page)



Interrupt Bit Description

7 Camera 1 TX serial activity

8 Reserved

9 Reserved

10 Memory controller status activity

11 - 29 Reserved.

30 Channel 0 custom app (Example custom_app: Aux. Serial Tx activity)

31 Channel 1 custom app (Example custom_app: Aux. Serial Rx activity)

Table 3 : Interrupt Mapping



3.1.7 Subcomponents

The details of the subcomponents that make up the top level of the design follow.

3.1.7.1 ocp_int_controller

The ocp_int_controller take multiple interrupt as inputs (up to 32), and monitors them for activity. When aninterrupt occurs it set a corresponding bit in a status register (if the interrupt is enabled) and generate a outputinterrupt. this status register can then be cleared using the clear register so further interrupts on this inputinterrupt line can be detected.

32irqs_i

ocp_clkocp_m2s

irq_o

ocp_s2m

Figure 4: ocp_int_controller I/O Diagram

3.1.7.1.1 Address Map

Register Address Description

IRQ_ENABLE 0x0080 IRQ Enable:Each bit in this register enables a single input interrrupt.

IRQ_CLEAR 0x0084IRQ Clear:Writing a bit in this register acknowledges the interrupt seen on one ofthe inputs.

IRQ_STATUS 0x008C

IRQ Status:When the output interrupt is asserted that register shows which inputinterrupt source(s) caused the output interrupt to be assered. Afterperforming any nessacary action the corrisponding IRQ_CLEAR bitshould be written to acknowledge the processing of the interrupt.



3.1.7.2 clink_adb3

The clink_adb3 entity provides a IO layer for converting an externally connected Camera Link camera's outputinto a pixel data stream with framing information that can be used as part of an image processing pipeline. Thiscomponent also provides a UART serial engine for communication with the camera and a control module forinterfacing with the camera's CC lines.

ref_clk_200_ips_clkrst_in

reg_clk_inreg_ocp_i

clink_in

reg_ocp_o

clink_out

ser_irq_outcam_data_out

Figure 5: adclinkchip_base I/O Diagram

The module consists of several sub-components; adclinkchip_base, clink_pixmap, clink_pix_swtich,common_rs232, and clink_cc_ctrl.

i_adb3_ocp_l_spliteq

i_clink_chip

i_clock_speed_0

i_pixmap

i_pix_switch

i_common_rs232i_clink_cc_ctrl

p_registers

p_clink_irq

clink_base_adb3

Figure 6 : clink_base_adb3



3.1.7.2.1 adclinkchip_base

This black box component de-serilises the Camera Link IO to interface it with the FPGA fabric.

For detailed information on this component please refer to Camera Link Chip Base Core for Virtex-4/5/6, orCamera Link Chip Full Core for Virtex-4/5/6 for more infomation.

3.1.7.2.2 clink_pixmap

The clink_pixmap component is used to re-sample the image data before sending it further down the imageprocessing pipeline. This may be used to select only a Region of Interest (RoI) from the available image stream ifthe camera being used provides an image stream larger than required or the provided image stream containsinactive lines and pixels that should be ignored.

The diagram below shows an image provided by a camera with inactive pixels and inactive lines both before andafter the actual picture.

LVAL

FV

AL

Start of Frame

Start of Image

First Line

Last Line

End of Image

End of Frame

Region of Interest

Dead Pixels

Sta

rt of Im

ag

e

Sta

rt of L

ine

Firs

t Pix

el

La

st P

ixe

l

En

d o

f Ima

ge

En

d o

f Lin

e

Figure 7 : RoI

Using the registers REG_CLNK_START_LINE, REG_CLNK_END_LINE, REG_CLNK_START_PIXEL, andREG_CLNK_END_PIXEL the clink_pixmap can be used to acquire only the desired RoI.



3.1.7.2.3 clink_pix_switch

This component packs the data into 32-bit (or 64-bit for Medium/Full Camera Link) words to allow it to be writteninto memory more efficiently.

3.1.7.2.4 common_rs232

This component provides a UART engine for serial communication with the attached Camera.

It is controlled via register in the clink_adb3 block.

3.1.7.2.5 clink_cc_ctrl

This component can be used to drive clock or pulse signals on the CC lines to the Camera, each CC line has itsown clock/pulse circuit that can operate down to a resolution of 5.0 ns.



3.1.7.2.6 Address Map


REG_CLNK_CONTROL 0x0000 Camera Link Control:Provides basic control required to interact with the module.

REG_CLNK_STATUS 0x0004 Camera Link Status:Provides critical status information on this module.

REG_CLNK_OPMODE 0x0008Camera Link Mode:Sets the expected input data format. This is used to decide how topack the input data into the 32-bit or 64-bit output data stream.

REG_CLNK_START_LINE 0x000C Start Line:Sets the first line in the Region of Interest.

REG_CLNK_END_LINE 0x0010 End Line:Sets the last line in the Region of Interest.

REG_CLNK_START_PIXEL 0x0014 Start Pixel:Sets the first column in the Region of Interest.

REG_CLNK_END_PIXEL 0x0018 End Pixel:Sets the last column in the Region of Interest.

REG_CC4_HI 0x0020 CC4 High Period:Set period of CC4 high pulse or high clock period. 5.0 ns increments.

REG_CC4_LO 0x0024 CC4 Low Period:Set period of CC4 low pulse or low clock period. 5.0 ns increments.

REG_COMMS_CONTROL 0x0028 Serial control register:Reset register for UART engine.

REG_COMMS_CK_DIV 0x002C Serial clock divider:Sets clock rate for serial communication with Camera.

REG_COMMS_TXFIFO 0x0034 Serial TX Data:Send TX serial data FIFO.

REG_COMMS_RXFIFO 0x0038 Serial RX Data:Buffered RX serial data FIFO.

REG_COMMS_TXSTATUS 0x003C Serial TX Status:Status register for serial transmission to Camera.

REG_COMMS_RXSTATUS 0x0040 Serial RX Status:Status register for serial reception from Camera.

REG_TEST 0x0044 Test Pattern Register:Test Pattern register

REG_CLK_X 0x0048 Pixel Clock Rate:Measured camera clock rate.

REG_CC_CTRL 0x004C CC Control Register:Control register for pulse or clock generation on CC lines.







REG_CC2_LO 0x005C CC2 Low Period:Set period of CC2 low pulse or low clock period. 5.0 ns increments.



REG_MAJOR_RELEASE 0x0068 Major Release Version:A register containing versioning information.

REG_MINOR_RELEASE 0x006C Minor Release Version:A register containing versioning information.

REG_MAJOR_BUILD 0x0070 Major Build Version:A register containing versioning information.

REG_MINOR_BUILD 0x0074 Minor Build Version:A register containing versioning information.

REG_SYNC_SELECT 0x0078

Channel Sync Select (Medium/Full Only):This register is used to specify which bit in the serial Camera Link datais used to synchronize channel when more than one channel is beingused.This register should not need to be modified.



3.1.7.3 camera_link_ocp_interface

ref_clk_200

burst_clkn

burst_s2m

nreg_clk

nreg_m2s

ncam_data

nburst_m2s

nreg_s2m

nirqs

Figure 8: camera_link_ocp_interface I/O Diagram

The module consists of several sub-components; cl3_qual2strobe, cl3_image_pack_4to1 orcl3_image_pack_2to1, cl3_frame_stamper, and adb3_ocp_data_sink.

i_cl3_qual2strobe

i_cl3_image_pack_4to1 / i_cl3_image_pack_2to1

i_cl3_frame_stamper

i_adb3_ocp_data_sink

camera_data

cl3_image

cl3_image_128

adb3_ocp_l

adb3_ocp

interrupt

camera_link_ocp_interface

Figure 9 : camera_link_ocp_interface

3.1.7.3.1 cl3_qual2strobe

cl3_qual2strobe converts the camera_data signals into the strobe based cl3_framing signals and data.

3.1.7.3.2 cl3_image_pack_4to1 or cl3_image_pack_2to1

Depending on whether the design is targeted for Base, or Medium/Full the design will instantiate eithercl3_image_pack_4to1 or cl3_image_pack_2to1 to pack the 32-bit or 64-bit data into 128-bit words.



3.1.7.3.3 cl3_frame_stamper

This component adds an extra word to the end of the frame. The bottom 64-bits of the addition word contains theframe sequence number. The top 64-bits contains a time stamp with a resolution of 5.0 ns.

When the FPGA is configured the frame stamping timer starts from zero. It is up to the application to interpret thistime in relation to real time if required. For example the application could compare the time on the first grabbedframe to the system time, and then derive the time index of subsequent frame. This time stamp can also be usedto check that the image source is generating images at a regular rate using the fine resolution of the counter.

The frame sequence number part of the stamp can be used to detect missing frame in a sequence that the hostfailed to acquire.

3.1.7.3.4 cl3_image signal profile

In additon to the camera_data signal profile some parts of the design use the cl3_image profile interconnectsome components.

The camera_data signal profile has the DVAL, LVAL, and FVAL these qualify the data, and are used to derivestart and end of lines and frames. There are a few disadvantages to using them: The stream must have an emptycycle between each line or frame, often the start and end of lines need decoding from the qualifiers, and it's notpossible to have single clock cycle lines.

The cl3_image record definition has strobes instead of qualifiers which remove these limitations.

Instead of defining clocks and data in the record as with camera_data, no clock is included in the record, andthere is no fixed width for the data signal. Instead clocks should be distributed as required, and in addition to thecl3_image_framing signals a std_logic_vector of the required width should be used to transport the data.Together the data signal and the cl3_image_framing signals are know as cl3_image_n where 'n' is replaced withthe width of the data path. For example cl3_image_128 would have a 128-bit data path with the additional of thecl3_image_framing signals.

The cl3_image specification does not contain any information about formatting of the data, or how many pixelsare packed into the data per cycle.

Signal Width Description

vld 1 Data contains active pixel and other signal in this record are valid.

sof 1 First pixel in frame.

eof 1 Last pixel in frame.

sol 1 First pixel in line.

eol 1 Last pixel in line.

Table 4 : Record definition for cl3_image_framing


rdy 1 Ready to receive data.

Table 5 : cl3_image_framing flow control



3.1.7.3.5 adb3_ocp_data_sink

The function of this component is to convert streaming data input on its stream interface, to write transactions onits sync interface. These OCP transactions transfer the streaming data to a free element in a circular bufferstructure implemented externally in RAM. Once the buffer is full, further streaming data is discarded.

The component can initiate an interrupt request to the host after a chosen number of buffer elements have beenwritten. The host may then read a number of these buffer elements and indicate that they are now free using thecontrol interface.

The component may be controlled using its instantiation generics/signals for stand alone operation, and/orregisters attached to its control interface for host controlled operation.

rst

stream_ocp_clkstream_m2sstream_s2m

ctrl_ocp_clkctrl_m2sctrl_s2m

ctrl_resetctrl_pause

ctrl_buff_freectrl_drop_free

ctrl_buff_int_enctrl_drop_int_en

ctrl_flush_last

sink_ocp_clksink_m2ssink_s2m

ctrl_irq

16drop_cnt

16buff_write_cnt

16buff_read_cnt

Figure 10: adb3_ocp_data_sink I/O Diagram



4 Building the FPGAThis section documents how to build the example FPGA design.

4.1 MIG Memory CoresBefore building a design that uses DDR3, for example the -MFB-ADB3 designs, MIG cores must be created. Thiscan be done by running the following command in ~\\fpga\\coregen\\ddr3_sdram_if in Windows or Linux.

xtclsh gen_ddr3_if_mig6_v3_9.tcl <target_board>

<target_board> in the above command should be replaced the the approate target:

<target_board> Support Targets

admxrc6t1 ADMXRC6T1

adpexrc6t ADPEXRC6T

4.2 ISEISE project files (.xise) are provided for all the supported designs listed in the nmake section below. Theseproject files can be found in sub-directories in ~/fpga/ise/. Note that after building a bitfile using an ISE project itwill not have the correct name or be in the correct location to automatically be used with the API and exampleapplications. It must be renamed appropriately after generation and copied into ~\\bit\\ in the appropriatesub-folder.

4.3 nmake (Windows Only)The example FPGA designs can also be built on the command line using nmake. Nmake commands should beexecuted from the ~/fpga/nmake folder. Building the FPGA in this way will also include correctly naming theoutput bitstream, and copying it to the correct location for the example applications and APIs to automatically useit.

4.3.1 Support Designs

The following nmake commands can be used to build designs (copy/paste the appropriate line from below intothe command line). Note that the FPGA speed grade should be changed to match the target hardware if a FPGAspeed grade of better than 1 is being used.

nmake DESIGN=xrm-clink-mfb-adb3 SUB_DESIGN=db TARGET=xrc6t1 FAMILY=6v DEVICE=lx240tSPEED=1 PKG=ff1759nmake DESIGN=xrm-clink-mfb-adb3 SUB_DESIGN=db TARGET=xrc6t1 FAMILY=6v DEVICE=lx365tSPEED=1 PKG=ff1759nmake DESIGN=xrm-clink-mfb-adb3 SUB_DESIGN=db TARGET=xrc6t1 FAMILY=6v DEVICE=sx315tSPEED=1 PKG=ff1759nmake DESIGN=xrm-clink-mfb-adb3 SUB_DESIGN=db TARGET=xrc6t1 FAMILY=6v DEVICE=lx550tSPEED=1 PKG=ff1759nmake DESIGN=xrm-clink-mfb-adb3 SUB_DESIGN=db TARGET=xrc6t1 FAMILY=6v DEVICE=sx475tSPEED=1 PKG=ff1759 nmake DESIGN=xrm-clink-mfb-adb3 SUB_DESIGN=gige TARGET=xrc6t1 FAMILY=6v DEVICE=lx240t SPEED=1 PKG=ff1759nmake DESIGN=xrm-clink-mfb-adb3 SUB_DESIGN=gige TARGET=xrc6t1 FAMILY=6v DEVICE=lx365t SPEED=1 PKG=ff1759nmake DESIGN=xrm-clink-mfb-adb3 SUB_DESIGN=gige TARGET=xrc6t1 FAMILY=6v DEVICE=

Page 18 Building the FPGAad-ug-0012_v2_3_CLINK-SDKUserManual.pdf


sx315t SPEED=1 PKG=ff1759nmake DESIGN=xrm-clink-mfb-adb3 SUB_DESIGN=gige TARGET=xrc6t1 FAMILY=6v DEVICE=lx550t SPEED=1 PKG=ff1759nmake DESIGN=xrm-clink-mfb-adb3 SUB_DESIGN=gige TARGET=xrc6t1 FAMILY=6v DEVICE=sx475t SPEED=1 PKG=ff1759 nmake DESIGN=xrm-clink-mfb-adb3 SUB_DESIGN=std TARGET=xrc6t1 FAMILY=6v DEVICE=lx240t SPEED=1 PKG=ff1759nmake DESIGN=xrm-clink-mfb-adb3 SUB_DESIGN=std TARGET=xrc6t1 FAMILY=6v DEVICE=lx365t SPEED=1 PKG=ff1759nmake DESIGN=xrm-clink-mfb-adb3 SUB_DESIGN=std TARGET=xrc6t1 FAMILY=6v DEVICE=sx315t SPEED=1 PKG=ff1759nmake DESIGN=xrm-clink-mfb-adb3 SUB_DESIGN=std TARGET=xrc6t1 FAMILY=6v DEVICE=lx550t SPEED=1 PKG=ff1759nmake DESIGN=xrm-clink-mfb-adb3 SUB_DESIGN=std TARGET=xrc6t1 FAMILY=6v DEVICE=sx475t SPEED=1 PKG=ff1759 nmake DESIGN=xrm-clink-mfb-adb3 SUB_DESIGN=full TARGET=xrc6t1 FAMILY=6v DEVICE=lx240t SPEED=1 PKG=ff1759nmake DESIGN=xrm-clink-mfb-adb3 SUB_DESIGN=full TARGET=xrc6t1 FAMILY=6v DEVICE=lx365t SPEED=1 PKG=ff1759nmake DESIGN=xrm-clink-mfb-adb3 SUB_DESIGN=full TARGET=xrc6t1 FAMILY=6v DEVICE=sx315t SPEED=1 PKG=ff1759nmake DESIGN=xrm-clink-mfb-adb3 SUB_DESIGN=full TARGET=xrc6t1 FAMILY=6v DEVICE=lx550t SPEED=1 PKG=ff1759nmake DESIGN=xrm-clink-mfb-adb3 SUB_DESIGN=full TARGET=xrc6t1 FAMILY=6v DEVICE=sx475t SPEED=1 PKG=ff1759

Page 19Building the FPGAad-ug-0012_v2_3_CLINK-SDKUserManual.pdf


5 Simulation5.1 ModelSim

Simulation scripts for supported example designs can be found in sub-directories in ~\\fpga\\msim\\. Simulationcan be launched from the command line with the -do flag, for example:

> modelsim -do xrm-clink-mfb-adb3-db-xrc6t1-6vlx240t.do

5.1.1 XRM-CLINK-MFB-ADB3 Testbench

The diagram below shows the structure of the test bench.

uut(clink_top_level)test_clink

Key:DMA OCP

Direct Slave OCP On-board memory OCP

DS OCP

finti_n

DMA OCP

api_application

finti_n

xio_ext Models

xio_i

xio_o

adb3_ocp_transaction_probe

OCP DS

mptl_if_target_wrap

DS OCP

MPTL B2T

DMA OCP

MPTL T2B

MPTL Sideband

blk_clocks

clks_mgt_in

pll_ref_clk

pll_mem_clk

mptl_clk

clks_in

pll_dma_clk

pll_reg_clk

pll_mem_clkx2

DMA Switch Function

RAM OCP

App OCP

Clink OCP

DMA OCP

blk_mem_if

OCP

BANKn

BANK0

- - -

BANK1

stat

Clink Function

DS OCP

clink_in

interrupt

Clink OCP

App OCP

clink_out

cio_i

cio_o

adb3_ocp_transaction_probe

OCP DS

MPTL B2T

MPTL T2B

MPTL Sideband

DS OCP

DMA OCP

mptl_if_bridge_wrap

DM OCP

adb3_ext_clks

clks_in_mgt

mptl_clk

clks_in

ocp_clk

Figure 11 : XRM-CLINK SDK Testbench

5.1.1.1 api_application

The target design is stimulated by the 'api_application' found in one of the files listed below. The api_applicationemulates the behaviour of a program running on the host system interacting with the FPGA design. The testbench includes serial communications testing, CC line tests, resetting the Camera Link de-serialisation logic, andacquiring images. 'api_application's for the various designs can be found in these locations:

\\fpga\\vhdl\\user_app\\xrm-clink-mfb-adb3\\api_app_clink_db_frame_grabber.vhd\\fpga\\vhdl\\user_app\\xrm-clink-mfb-adb3\\api_app_clink_full_frame_grabber.vhd\\fpga\\vhdl\\user_app\\xrm-clink-mfb-adb3\\api_app_clink_std_frame_grabber.vhd\\fpga\\vhdl\\user_app\\xrm-clink-mfb-adb3\\api_app_clink_gige_frame_grabber.vhd

Page 20 Simulationad-ug-0012_v2_3_CLINK-SDKUserManual.pdf


5.1.1.2 Camera Emulation

In addition to emulating the host the attached camera(s) are simulated in 'xio_model'. The models areprogrammable and generate pixel data based on the address of the pixel. The models support several differentCamera Link output formats including all the Base Camera Link formats, and the 8 x 8-bit Full Camera Linkformat. Further Medium and Full formats will be added in future releases.

5.1.1.3 Expected output# ** Note: Camera settings update: 0# Time: 0 ps Iteration: 0 Instance: /test_clink/i_api_application# ** Note: Camera settings update: 1# Time: 0 ps Iteration: 0 Instance: /test_clink/i_api_application# ** Note: Camera setup complete# Time: 0 ps Iteration: 0 Instance: /test_clink/i_api_application# ** Note: Allocating host memory for camera 0# Time: 1965 ns Iteration: 14 Instance: /test_clink/i_api_application# ** Note: Camera 0 host memory allocated 208 bytes# Time: 1965 ns Iteration: 14 Instance: /test_clink/i_api_application# ** Note: Version# Time: 1965 ns Iteration: 14 Instance: /test_clink/i_api_application# ** Note: REG_MAJOR_RELEASE 00000002# Time: 2415 ns Iteration: 13 Instance: /test_clink/i_api_application# ** Note: REG_MINOR_RELEASE 00000002# Time: 2865 ns Iteration: 13 Instance: /test_clink/i_api_application# ** Note: REG_MAJOR_BUILD 00000002# Time: 3315 ns Iteration: 13 Instance: /test_clink/i_api_application# ** Note: REG_MINOR_BUILD 00000088# Time: 3765 ns Iteration: 13 Instance: /test_clink/i_api_application# ** Note: Testing CC lines...# Time: 3765 ns Iteration: 13 Instance: /test_clink/i_api_application# ** Note: CC lines appear to be working.# Time: 4815 ns Iteration: 13 Instance: /test_clink/i_api_application# ** Note: Testing serial interface to camera:# Time: 5890 ns Iteration: 13 Instance: /test_clink/i_api_application# ** Note: Waiting for serial interrupt...# Time: 5990 ns Iteration: 13 Instance: /test_clink/i_api_application# ** Note: Interrupt detected...# Time: 329470 ns Iteration: 13 Instance: /test_clink/i_api_application# ** Note: Serial interface with camera appears to be working# Time: 330780 ns Iteration: 13 Instance: /test_clink/i_api_application# ** Note: Resetting CLink channel 0...# Time: 330980 ns Iteration: 13 Instance: /test_clink/i_api_application# ** Note: Interrupt detected...# Time: 1904495 ns Iteration: 13 Instance: /test_clink/i_api_application# ** Note: Camera Link Channel 0 reset done and locked!# Time: 1905805 ns Iteration: 13 Instance: /test_clink/i_api_application# ** Note: Interrupt detected...# Time: 2218407500 ps Iteration: 13 Instance: /test_clink/i_api_application# ** Note: Performing DMA read of size 208# Time: 2219955 ns Iteration: 13 Instance: /test_clink/i_api_application# ** Note: DMA completed# Time: 2220360 ns Iteration: 13 Instance: /test_clink/i_api_application# ** Note: Camera Link Channel 0 received frame 1 with no errors# Time: 2220740 ns Iteration: 13 Instance: /test_clink/i_api_application# ** Note: Interrupt detected...# Time: 2321757500 ps Iteration: 13 Instance: /test_clink/i_api_application# ** Note: Performing DMA read of size 208# Time: 2323305 ns Iteration: 13 Instance: /test_clink/i_api_application# ** Note: DMA completed# Time: 2323710 ns Iteration: 13 Instance: /test_clink/i_api_application

Page 21Simulationad-ug-0012_v2_3_CLINK-SDKUserManual.pdf


# ** Note: Camera Link Channel 0 received frame 2 with no errors# Time: 2324090 ns Iteration: 13 Instance: /test_clink/i_api_application# ** Note: Testing CC lines on channel 1...# Time: 2324115 ns Iteration: 14 Instance: /test_clink/i_api_application# ** Note: CC lines appear to be working.# Time: 2325265 ns Iteration: 13 Instance: /test_clink/i_api_application# ** Note: Testing serial interface to camera:# Time: 2325265 ns Iteration: 13 Instance: /test_clink/i_api_application# ** Note: Waiting for serial interrupt...# Time: 2325365 ns Iteration: 13 Instance: /test_clink/i_api_application# ** Note: Interrupt detected...# Time: 2624045 ns Iteration: 13 Instance: /test_clink/i_api_application# ** Note: Serial interface with camera appears to be working# Time: 2625355 ns Iteration: 13 Instance: /test_clink/i_api_application# ** Note: Resetting CLink channel 1...# Time: 2625555 ns Iteration: 13 Instance: /test_clink/i_api_application# ** Note: Interrupt detected...# Time: 4200495 ns Iteration: 13 Instance: /test_clink/i_api_application# ** Note: Camera Link Channel 1 reset done and locked!# Time: 4201805 ns Iteration: 13 Instance: /test_clink/i_api_application# ** Note: Interrupt detected...# Time: 4512970 ns Iteration: 13 Instance: /test_clink/i_api_application# ** Note: Performing DMA read of size 400# Time: 4514530 ns Iteration: 13 Instance: /test_clink/i_api_application# ** Note: DMA completed# Time: 4515330 ns Iteration: 13 Instance: /test_clink/i_api_application# ** Note: Camera Link Channel 1 received frame 1 with no errors# Time: 4515705 ns Iteration: 13 Instance: /test_clink/i_api_application# ** Note: Interrupt detected...# Time: 4616320 ns Iteration: 13 Instance: /test_clink/i_api_application# ** Note: Performing DMA read of size 400# Time: 4617880 ns Iteration: 13 Instance: /test_clink/i_api_application# ** Note: DMA completed# Time: 4618680 ns Iteration: 13 Instance: /test_clink/i_api_application# ** Note: Camera Link Channel 1 received frame 2 with no errors# Time: 4619055 ns Iteration: 13 Instance: /test_clink/i_api_application# ** Failure: Simulation has finished with no errors.# Time: 4619055 ns Iteration: 14 Process:/test_clink/i_api_application/p_main_thread File:../../../vhdl/user_app/xrm-clink-mfb-adb3/api_app_clink_db.vhd

Page 22 Simulationad-ug-0012_v2_3_CLINK-SDKUserManual.pdf


6 Extending the FPGA designs6.1 VHDL files

If developing a new design or extending an existing example design it is intended that developer adds theirVHDL files to:

~\\fpga\\vhdl\\user_app\\<fpga_design_name>\\

6.2 Project filesWhen extending an example design additional files should be added to either the .prj file or .xise file being usedto build the FPGA design.

6.3 custom_app componentThe XRM-CLINK-SDK example designs have a custom_app component intended as the point where a developershould implement their application. This template component may vary in architecture between example designs.

6.3.1 MFB-ADB3 custom_app template component

The recommended point for extending the mfb-adb3 example is inside a component with the following interface.

component clink_custom_app port ( reset_in : in std_logic; reg_clk_in : in std_logic; reg_ocp_i : in ocpad_register32_m2sT_array( 0 to CLINK_CHANNELS - 1 ); reg_ocp_o : out ocpad_register32_s2mT_array( 0 to CLINK_CHANNELS - 1 ); irqs_o : out std_logic_vector( 0 to CLINK_CHANNELS - 1 ); cio_in : in cio_i_t; cio_out : out cio_o_t; mem_clk_in : in std_logic; mem_ocp_i : in ocpad_burst128_s2mT_array( 0 to CLINK_CHANNELS - 1 ); mem_ocp_o : out ocpad_burst128_m2sT_array( 0 to CLINK_CHANNELS - 1 ); cam_data_in : in camera_data_array( 0 to CLINK_CHANNELS - 1 ); cam_data_out : out camera_data_array( 0 to CLINK_CHANNELS - 1 ) );end component;

The interface above provides the following features to a developer implementing an application as an instance ofthis component.

• 32-bit wide register interface.

• User definable records for additional FPGA IO.

• Input image streams(s).

• Output image streams(s).

• External memory port.

• Appropriate clocks for registers, memory access, and image data.

Page 23Extending the FPGA designsad-ug-0012_v2_3_CLINK-SDKUserManual.pdf


6.3.1.1 cam_data_in/cam_data_out

The cam_data_in/cam_data_out ports are defined as arrays of camera_data, which is defined as follows.

type camera_data is record clk : std_logic; d : std_logic_vector( 31/63 downto 0 ); vld : std_logic; sol : std_logic; eol : std_logic; sof : std_logic; eof : std_logic;end record;

clkThis signal is a clock synchronous to the other signals in the record.

dThis signal is the image data. The format of this data will vary with the type of camera the image is sourced from,and the configuration of the decoding IP.

Framing signalsIn addition to the clock and data, five additional single bit signals are used to describe the framing of the data.These signal are also used elsewhere in the design and are known as the cl3_image_framing record.


vld 1 Data contains active pixel(s) and other signals in this record are valid.

sof 1 Current data contains first pixel in frame.

eof 1 Current data contains last pixel in frame.

sol 1 Current data contains first pixel in line.

eol 1 Current data contains last pixel in line.

Table 6 : Record definition for cl3_image_framing

Page 24 Extending the FPGA designsad-ug-0012_v2_3_CLINK-SDKUserManual.pdf


6.3.1.2 cio_i_t and cio_o_t

The cio_i/o records defined in \\fpga\\vhdl\\user_app\\<fpga_design_name>\\custom_config.vhd allow developersto add additional top-level ports that are accessible in the custom_app component.

-- Definitions for customised input ports to connect outside the FPGA.type cio_i_t is record empty : std_logic;end record;

-- Definitions for customised output ports to connect outside the FPGA.type cio_o_t is record empty : std_logic;end record;

Page 25Extending the FPGA designsad-ug-0012_v2_3_CLINK-SDKUserManual.pdf


6.3.2 Adding registers

The following example code shows how a 32-bit register (example_register) can be added into the custom core.

reg_ocp_o(i).CmdAccept <= '1'; p_custom_registers : process( reg_clk_in ) begin if rising_edge( reg_clk_in ) then if reg_ocp_i(i).Cmd = OCP_CMD_WRITE then case reg_ocp_i(i).Addr( 7 downto 0 ) is when X"00" => adb3_ocp_l_wr( example_register, reg_ocp_i(i), 0 ); when others => end case; reg_ocp_o(i).Resp <= OCP_RESP_NONE; elsif reg_ocp_i(i).Cmd = OCP_CMD_READ then case reg_ocp_i(i).Addr( 7 downto 0 ) is when X"00" => reg_ocp_o(i).Data <= example_register; when others => reg_ocp_o(i).Data <= X"DEADC0DE"; end case; reg_ocp_o(i).Resp <= OCP_RESP_VALID; else reg_ocp_o(i).Resp <= OCP_RESP_NONE; end if; end if; end process;

Note in the code above CmdAccept is always asserted, this is because the reads and writes are executed in asingle cycle, so this OCP slave is always ready to execute a new command every cycle.

In the write command the procedure adb3_ocp_l_wr is used to decode the byte enables, so only the correctbytes of example_register are changed. The last parameter of this procedure is an offset in the write commandsdata that the target should be assigned from. As the target signal is 32-bits this offset is zero. See theADM-XRC-Gen3 SDK for more details on OCP register interfacing.

Page 26 Extending the FPGA designsad-ug-0012_v2_3_CLINK-SDKUserManual.pdf


7 API, Applications and UtilitiesThe adclink API is provdes a fast way to interact with the FPGA reference designs. Modifications to the referencedesigns may require the API to be modified appropriately. The source code for the API can be found in .\api\

7.1 XRM-CLINK APIIf using a Microsoft Windows OS it is not necessary to rebuild the API unless modifications are made to it as it isprovided pre-built in DLL form.

When using or rebuilding the API it is important to note there are two main versions of the API: Debug, andRelease. The Release version should be used when deploying an application, or when developing if you are notinterested in the specifics of the FPGA interaction. The debug version of the API can be used to assist indebugging and developing new designs. This version of the API includes additional debug messages that can becaptured to assist in debug and development. See the Debug Output for more details.

Both version of the API can be built together, they are identifiable by the extra 'd' added to the name of the debugversion. Executables are also named using this convention, for example the binary adclink_consoled.exe is thedebug version of adclink_console.exe. adclink_consoled.exe is linked against and dependant on adclinkd.dll andadclink_console.exe is linked against and is dependant on adclink.dll.

7.1.1 ADCommon

This is the first of two components that make up the XRM-CLINK API. It provides classes non-specific to imagecapture to manage FPGA card operation.

7.1.2 ADClink

This is the second component of the XRM-CLINK API. It extends ADCommon to provide class for image captureand controlling the example FPGA design.

7.1.3 XIO Viewer

The XIO Viewer utility is provded to allow RAW images that are captured to be viewed.

This utility can be used from the command line (or associated with .xio files) to display raw images saved usingthe ADClink::CDiskSink class. Raw datafiles contain only the uncompressed image data and not formattinginformation. The format and size of the image is stored as part of the file name:

image_name.<Width>.<Height>.<Format>.xio;

Parameter Description

Width Positive decimal integer, indicating the horizontal number of pixels.

Height Positive decimal integer, indicating the vertical number of pixels.

Page 27API, Applications and Utilitiesad-ug-0012_v2_3_CLINK-SDKUserManual.pdf


Parameter Description

Format

One of the following strings specifies the data format:

• G8R8_B8G8

• X6G10X6R10_X6B10X6G10

• X4G12X4R12_X4B12X4G12

• X2G14X2R14_X2B14X2G14

• G16R16_B16G16

• L8

• X6L10

• X4L12

• X2L14

• L16

• X8R8G8B8

To open a file using the XIO Viewer use the target filename to open as the first argument.

Page 28 API, Applications and Utilitiesad-ug-0012_v2_3_CLINK-SDKUserManual.pdf


7.2 Building in Windows

7.2.1 Requirements

Before building software the following dependencies need to be met.

Express/Professional edition of MSVC 2010/2012

admxrc3 driver (Optional /Required for Virtex-6 FPGA cards)

admxrc2 driver (Optional /Required for FPGA cards, previous to Virtex-6)

7.2.2 Build Targets

Alpha Data provides two underlining APIs and drivers for interfacing with Alpha Data FPGA cards; ADMXRC2and ADMXRC3. The XRM-CLINK SDK wraps both of these up in the adcommon DLL. It is not necessary to haveboth installed to build the included APIs and applications.

If the system has both the ADMXRC2 and ADMXRC3 drivers installed the Debug and Release Targets should beused. This target can also be used when the system is missing either the ADMXRC2/3 drivers if the application islinked delay loading the ADMXRC2/3 DLL.

If the system has only the ADMXRC2 driver installed the DebugGen2, and ReleaseGen2 Targets should beused.


The header files included in the SDK for ADMXRC2 and ADMXRC3 are included in the XRM-CLINK-SDK, soinstallations of the ADMXRC2 and ADMXRC3 SDK are not necessary.

7.2.3 MSVC

\\api\\msvc\\api_apps.sln. This solution contains three items. adclink, adcommon, and xio_viewer. These arethe two components that make up the software API, and a image view built using the API to display raw imagesthat are captured.

\\apps\\msvc\\adclink_apps.sln.This solution can be used to rebuild and debug the adclink_consoleapplication.

After building or rebuilding the applications or DLLs they should be executed from .\\bin\\<OS>\\<architecture>\\.



7.3 Building in Linux

7.3.1 Requirements

Before building software the following dependencies need to be met.

‡ g++, gcc

‡ make

‡ admxrc3 driver (Optional /Required for Virtex-6 FPGA cards)

‡ admxrc2 driver (Optional /Required for FPGA cards, previous to Virtex-6)

‡ Netbeans 7.2 or higher (optional for IDE based development)

7.3.2 Build Targets

Alpha Data provides two underlining APIs and drivers for interfacing with Alpha Data FPGA cards; ADMXRC2and ADMXRC3. The XRM-CLINK SDK wraps both of these up in the adcommon static library. It is not necessaryto have both installed to build the included APIs and applications, but it will affect the build targets that should beused.

If the system has both the ADMXRC2 and ADMXRC3 drivers installed the Debug and Release Targets should beused.



The header files included in the SDK for ADMXRC2 and ADMXRC3 are included in the XRM-CLINK-SDK, soinstallations of the ADMXRC2 and ADMXRC3 SDK are not necessary.

7.3.3 Using Command Line

To build the example applications and API static libraries the following commands can be used:

\api\linux\ make clean all CONF=<target>

This will build the two static libraries, and example image viewer XIO Viewer application

\apps\linux\ make clean all CONF=<target>

This will build the example frame grabbing application, adclink_console.

7.3.4 Using Netbeans IDE

The makefiles included that can be executed from the command line are part of a Netbeans project.

Netbeans is a free IDE; the C/C++ components include a full interactive debugger. The latest version ofNetbeans can be downloaded here: http://netbeans.org/downloads/ (only the C/C++ version is required).

To get started there are several projects that should be opened using File->Open Project. Netbeans projects arebased on open a directory containing a nbproject sub folder instead of one file containing the project information.

\api\linux\adcommon. This is a static library that is used to wrap up many common FPGA board operations.

\api\linux\adclink. This is the second static library, which provides classes for interacting with the Camera LinkSDK bitfiles.



\api\linux\xio_viewer. The XIO Viewer is a very basic application provided as an example of how to display rawdata that has been acquired from a Camera.

\apps\linux\adclink_console. This is the example application provided to interact with the example designsprovided in the SDK.



7.4 XRM-CLINK ApplicationsThe source code and projects for the application(s) included in the XRM-CLINK SDK can be found in .\apps\

7.4.1 ADCLink Console

Two versions of this application are included with the XRM-CLINK SDK. One built with the _DEBUG flag(adclink_consoled.exe) defined and one without _DEBUG defined (adclink_console.exe). If any issues occurrunning the Release version of this application, the Debug version should be run to provided diagnosticinformation that should highlight where the fault is occurring.

7.4.1.1 Command line options

The following command line options can be specified as command line arguments to adclink_console.

Linux-bitdir <path containing FPGA Bitstreams>

Windows and VxWorks/bitdir <path containing FPGA Bitstreams>

7.4.1.2 Configuring the FPGA card

After starting the application the first prompt, shown below, asks the user to select the Alpha Data card that willbe used for Camera Link input.

------------------------------------------------------------------------------- - Select a card to use - ------------------------------------------------------------------------------- - - - xrc6t1-6vsx315t S/N: 102.............................................1 - - - -------------------------------------------------------------------------------

The next menu that appears asks the user to select which reference design/xrm combination is attached to thiscard.

------------------------------------------------------------------------------- - Select FPGA design - ------------------------------------------------------------------------------- - - - XRM-CLINK-FIFO-ADB3-STD..............................................1 - - XRM-CLINK-FIFO-ADB3-DB 2 - - XRM-CLINK-FIFO-ADB3-GIGE.............................................3 - - XRM-CLINK-MFB-ADB3-STD 4 - - XRM-CLINK-MFB-ADB3-DB................................................5 - - XRM-CLINK-MFB-ADB3-GIGE 6 - - - -------------------------------------------------------------------------------

The final stage to configuring the card is to program the card using option '1' on the following menu. The optionof not programming the card is provided to assist in debugging and gives the user a chance to abort configuringthe card ( by pressing Ctrl+C ) after making the previous selections.

------------------------------------------------------------------------------- - Program the card? - ------------------------------------------------------------------------------- - -



- Program..............................................................1 - - Don't program 2 - - - -------------------------------------------------------------------------------

After selecting to program the FPGA a prompt will be given to choose the camera that the console application willutilise.

Select option:> 1

FPGA Version: 2.2.1.79

------------------------------------------------------------------------------- - Select camera index - ------------------------------------------------------------------------------- - - - Camera 0.............................................................1 - - Camera 1 2 - - - -------------------------------------------------------------------------------

The API needs additional information about the camera that is attached to the selected input. Several examplecamera classes are included in the application, and a generic camera class that can be modified after beingselected.

------------------------------------------------------------------------------- - Select camera - ------------------------------------------------------------------------------- - - - Generic Camera.......................................................1 - - JAI_M7Plus 2 - - SI1920HD_M...........................................................3 - - Dalsa1M150SA 4 - - ICL_B0620............................................................5 - - - -------------------------------------------------------------------------------

7.4.1.3 Main menu

After programming the FPGA the Camera Link logic will be re-set and attempt to lock onto the camera(s)'s clock.A message will be displayed showing the success or failure of the reset, after which the main menu will bedisplayed.

------------------------------------------------------------------------------- - CLink Example - ------------------------------------------------------------------------------- - - - Load camera class....................................................1 - - Camera settings 2 - - Get single frame ( save as RAW ).....................................3 - - Get single frame ( save as BMP ) 4 - - Get multiple frames ( save frames as RAW )...........................5 - - Get multiple frames ( save frames as BMPs ) 6 - - Get video stream ( Visualise ).......................................7 - - Profile system 8 - - Profile system with CVideoBuffer.....................................9 - - Reset Link 0 - - TX serial command....................................................a - - Change selected camera b - - Register write.......................................................c - - Register read d - - Get clock rate.......................................................e -



- CC line control f - - Hardware reset test..................................................g - - Software sweep test h - - Memory test..........................................................i - - - - Exit.................................................................Q - - - -------------------------------------------------------------------------------

The main menu provides two options for setting up camera(s) attached to the system. The first is to load apre-defined camera class using option '1' on the menu, or alternative parameters for a CGenericCamera can besetup using option '2'.

------------------------------------------------------------------------------- - Camera Setup - ------------------------------------------------------------------------------- - - - Data format : DATA_FMT_X8R8G8B8.......................1 - - CLink format : BASE_RGB_BITS 2 - - Max frame size : 1024x1024...............................3 - - Dead pixels : 0x0 4 - - Capture frame size : 1024x1024...............................5 - - Capture offset : 0x0 6 - - Invert Clock : false...................................7 - - Invert FVAL : false 8 - - Invert LVAL : false...................................9 - - Invert DVAL : false 0 - - Ignore DVAL : false...................................a - - Serial Baud : 9600 b - - Frames In One : 1.......................................c - - - - Back.................................................................Q - - - -------------------------------------------------------------------------------

After setting up the camera a number of options are available to capture data from the camera; '3', '4', '5', and '6'.Options '3' and '4' can be used to save a single frame from the camera into either a binary format, or into a .bmpfile after the binary image data has be passed though a CImage object. Note saving the image as a bitmap willresult in reduced pixel depth of the image if the raw data is has a pixel depth of more than 8-bits per channel.

Option '5', and '6' provided the options to save multiple frames of data into a and single file raw file (which canlater be viewed with the XIO Viewer application) or mutiple .bmp files. All save files are written into the workingdirectory of the application.

Option '7' provides a real-time visual output of data being acquired.



Figure 12 : Get video stream ( Visualise )

Options '8' and '9' can be used to check that the host system is able to acquire all the image data from theFPGA. Option '7' profiles acquiring data from FPGA card without modifying it for display purposes. Option '8'profiles the system using a CVideoBuffer object to acquire the data from the FPGA card and then also performs asoftware conversion of the data, converting it to a 24-bit RGB format. After selecting an option the user shouldselect a quantity of frames that will take at least several seconds to acquire (the longer the profiling time themore accuracy the results).

Enter the number of frames to acquire: 100 Profiling... done

Runtime : 2.115 seconds Total data received : 400.000 MBs Single frame size : 4.000 MBs Total frame received : 100 frames Dropped frames : 0 frames Average data rate : 189.157 MBs-1 Average frame rate : 47.289 FPS

Option 'f' can be used to control the Camera CC lines.

------------------------------------------------------------------------------- - Camera CC Line Control - ------------------------------------------------------------------------------- - - - CC1 : low.....................................1 - - CC2 : low 2 - - CC3 : low.....................................3 - - CC4 : low 4 - - - - Back.................................................................Q - - - -------------------------------------------------------------------------------



7.4.1.3.1 Memory Test

The -MFB-ADB3 design makes use of the memory external to the FPGA, if the console application is interfacingwith one of these design's a memory test option will be available on the main menu (option 'i'). Once selectedexecution should take a few seconds to complete after which the results of the test will be displayed.

Generating test data Running test..

Download/Upload completed...

Performing error check...

Payload : 256.000 MBs TX time : 0.422 seconds TX data rate : 607.326 MBs-1 RX time : 0.346 seconds RX data rate : 740.930 MBs-1

Note: Due to the resolution of the timer used the results have limited accuracy.



7.4.2 clseradl.dll (Windows Only)

The Camera Link specification details a DLL for Windows providing an API for serial interaction with the CameraLink cameras via a frame grabber. The manufacture of frame grabber should provide the clserxxx.dll, this allowscamera manufactures to make a standard configuration application that will find Camera Link compatible DLLsand attempt to use them to interact with their camera via a 3rd parties frame grabber.

clseradl.dll provided with the XRM-CLINK SDK implements the specification above when used in conjunctionwith the adclink_console application. The DLLs has been design in this way to allow the user to configure theframe grabber correctly for their hardware configuration.

To use the DLL is should be installed in the appropriate location for the camera's manufacture's application tofind it. Before running the camera manufacture's application the adclink_console application should be started.After configuring the desired FPGA card the option 'Connect to clserall.dll' on the main menu of theadclink_console application should be started. When this option is selected it will open a small windowrepresenting the open connection to the clseradl DLL. After the connection has been opened the manufacture'sapplication can be started. As it runs, request accessing the serial port of the camera will be displayed in theconsole window of the adclink_console application.



8 C++ API8.1 API Documentation

Full documention of the software API classes, and functions can be found in the C++ API Reference Manual.

8.2 API Quick StartThis guide explains how to instantiate the various camera link classes in a C++ application in order to acquireimage data from an Alpha Data reconfigurable computing card with an attached XRM-CLINK module.

8.2.1 Preprocessor Symbols

Before starting to use the API developers should be aware of the preprocessor symbols that effect the API.

Symbol Description

_DEBUG Can be defined to enable debug macros. See Debug Output for moreinformation.

_EXCLUDE_ADMXRC_GEN2 Defining this macros removed the API's dependency on the ADMXRC2 API(also removing support for Virtex-5 and earler boards).

_EXCLUDE_ADMXRC_GEN3 Defining this macros removed the API's dependency on the ADMXRC Gen 3API (also removing support for Virtex-6 boards).

_LINUX Must be defined when compiling for Linux.

_VXWORKS Must be defined when compiling for VxWorks.

_WIN32 Must be defined when compiling for Microsoft Windows.

Table 7 : Preprocessor Symbols

8.2.2 Notation

Some variations on standard notation are used in this API for class names. Class names have three possibleprefixes: A for abstract, C for concrete class, and I for interface.

• Abstract classes ( A ) should not be directly instantiated by application code. Instead, they should beinherited from (i.e. extended) by application code, which is permitted to make use of any functions that theabstract class provides.

• Concrete classes ( C ) may be instantiated as-is by application code.

• Interface classes ( I ) provide only abstract functions, with no implementations for those functions. As such,application code may inherit from an interface class, but must override all of the abstract functions in orderto provide implementations of those functions.

• Enumerations ( E )

8.2.3 Including the API

To include the XRM-XRM-CLINK API in a project include the header <adclink.h>. The namespace AlphaData::Clink should be used to make all the include classes and enumeration easily accessible. For example:

#include <adclink.h> // Include the Alpha Data Camera Link API.

using namespace AlphaData::CLink; // Use the Camera Link API namespace.

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8.2.4 Programming the FPGA

The first step that must be taken to interact with the card is to configure the FPGA with a bitstream, and initializethe FPGA. If the reference FPGA design is being used, one of the following idioms may be used, depending onthe XRM-CLINK and camera configuration:

// For XRM-CLINK-STDACameraCard* pMyXRC = new CFIFOCameraCard( g_nCardIndex, XRM_CLink_STD );

// For XRM-CLINK-MINI (dual base)ACameraCard* pMyXRC = new CFIFOCameraCard( g_nCardIndex, XRM_CLink_DB );

After creating an object to represent the card the FPGA can be programmed:

pMyXRC->ConfigureCard( g_szOutputDir, true );if( pMyXRC->GetStatus() != CARD_OK ){ //Handle the error}

The first parameter in the ConfigureCard function sets the folder where the API will look for the .BIT file withwhich to program the FPGA. The .BIT file used to program the FPGA will be selected automatically based on thetype of card being used. To force the use a particular .BIT file, application code must extend the desired classand override the ConfigureCard function to use a specific name.

The second parameter of ConfigureCard is used to select of the FPGA is programmed or not. If the FPGA is notprogrammed the card is still opened a made accessible. It may be useful not to re-program the FPGA if anapplication crashes, so on the next run register information maybe dump showing the previous state of thesystem.

8.2.5 Attaching a camera

An ACamera object is used to represent a physical camera attached to a card. Below is an example of how toinstantiate a camera object for a camera class that is supplied as an example with this SDK:

ACamera* pMyCamera = (ACamera*)new CJAI_M7Plus( pMyXRC, 0 );

The code above creates a CJAI_M7Plus camera object associated with the first camera attached to thepreviously created ACameraCard object. Before the camera can be used, the logic associated with it should bereset and then checked to ensure that it is functioning correctly.

if( !pMyCamera->ResetLink() ){ //Handle error here}

Unless using a JAI_M7Plus the developer will need to do one of the following to make their camera compatiblewith the API:

• Extend the ACamera class (recommend).

• Alternatively, to avoid extending ACamera a class CGenericCamera is proved that takes all theparameters of the camera in its constructor.

For examples of extending the ACameraClass, refer to the source code (cam_*.cpp/.h) in the '/apps/source/clink_console' folder.

When either extending the ACamera class or using the CGenericCamera class it will be necessary to select botha EDataFormat and a ECLinkFormat. The ECLinkFormat should match the Camera Link interface formatprovided by the camera. The EDataFormat should match the format of the raw data, this parameter is used both

Page 39C++ APIad-ug-0012_v2_3_CLINK-SDKUserManual.pdf


to determine the number of bytes to transfer to the host in a frame, and in CImage and CVideoBuffer objects todetermine how the convert the received raw data into an RGB format. See pixel_switch for more information onthe use of the EDataFormat and ECLinkFormat enumerations.

8.2.6 Grabbing frames

After creating the ACameraCard and ACamera objects, frames can be grabbed from the camera into a buffer inhost memory.

// Allocate some memory for the frame to be transferred to, and create a DMAhandle.// Both of these can be re-used for each frame captured.void* pBuffer = g_pMyCamera->GetNewFrameBuffer();ADMXRC2_DMADESC* pDMADescriptor = g_pMyCamera->CreateDMADescriptor( pBuffer,g_pMyCamera->GetFrameSize() );if( !pMyCamera->GetFrame( pDMADescriptor ) ){ // Handle the error}else{ // Do something with the RAW data}

// Clean upg_pMyCamera->DestroyDMADescriptor( pDMADescriptor );g_pMyCamera->DeleteFrameBuffer( pBuffer );

The above code creates a buffer that is large enough for the largest image that the camera can generate. Notethat it is the responsibility of application code to delete this buffer when appropriate using ACamera::DeleteFrameBuffer. The second line attempts to grab a frame from the camera. If the operation fails, or the wholeframe could not be grabbed, the function returns false.

8.2.7 Working with raw data

The previous section shows how to grab raw frames from a camera attached to a camera link card. To maximizethe frame rate, processing on the host system's CPU should be kept to a minimum. Heavyweight imageprocessing tasks should be implemented as part of the FPGA design.

To assist in displaying images, the XRM-CLINK API provides two format conversion classes: CImage andCVideoBuffer. The CImage class can be used to convert raw image data into a different format and save a frameto disk as a bitmap file. The CVideoBuffer class can be instantiated to provide a triple buffer using separatethreads for acquiring data from the FPGA and performing any required software conversion for display purposes.

Note: When using the CImage or CVideoBuffer objects the output from either is only 8-bits per colour. Thedeveloper should work with the raw data rather than using these object if they require an output with a pixeldepth of more than 8 bits.

8.2.8 Region of interest

If a camera link application must perform a significant amount of image processing, minimizing the amount ofdata being acquired may be desirable. Setting a region of interest (ROI) results in a rectangular section of theimage being acquired, as opposed to the entire image. The reference FPGA design supplied with this SDKsupports setting this region via the XRM-CLINK API. The ACamera class provides the following functions thatcan be used to dynamically adjust the region of interest:

bool SetPixelOffset( unsigned int nCount );bool SetLineOffset( unsigned int nCount );



bool SetSamplePixels( unsigned int nCount );bool SetSampleLines( unsigned int nCount );

There are several caveats to note when using these functions:

• Attempting to call SetPixelOffset or SetLineOffset so that the ROI lies outside the image dimensionssupported by the camera results a return value of false and the region of interest not being modified.

• Attempting to set SetSamplePixels or SetSampleLines so that the ROI is larger than that supported by thecamera also results in a return value of false, and the region of interest not being modified.

• When either SetPixelOffset or SetLineOffset are called, this may result in the width and height of the ROI(as set by SetSamplePixels and SetSampleLines) being adjusted so that the ROI still lies within the imagedimensions supported by the camera.

Corresponding Get* functions are also provided, which can be used to verify that the requested ROI has beenset. Refer to the full XRM-CLINK API documentation for more details.

8.2.9 Using the Camera Link's serial port

The Camera Link interface provides a serial port to communicate with the camera. The SDK reference designcontain a serial engine that can be controlled using the API as follows:

Before sending or receiving any serial data the baud rate of the connection need to be and then the serialconnection reset as follows:

//Set the serial baud to 9600g_pMyCamera->SetSerialBaud( 9600 );

//Reset the serial linkg_pMyCamera->ResetSerial();

After completing the above the following functions can be used to write and read to and from an attachedcamera:

unsigned int ACamera::ReadSerial( char* pBuffer );bool ACamera::WriteSerial( const char* pBuffer, unsigned int nSize );bool ACamera::WriteSerial( const char* pBuffer );

The last function above take a null terminated string as an input parameter, eliminating the needs for specifyingthe length of the buffer being written to the camera.

8.2.10 Accessing Registers in an extended FPGA design

The XRM-CLINK API can be used to access registers in the FPGA. This can be done using the followingfunctions found in ACameraCard:

unsigned int ReadReg32( unsigned long nReg );void WriteReg32( unsigned long nReg, unsigned int nData );

These functions read and write individual 32-bit registers. The first user_core register is located at theenumeration BASE_ADDR_USER. A list of the base addresses in the FPGA reference designs is defined inCLink::EAddressMap, the register offsets for the clink_base module are defined in CLink::EControlRegister.

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8.2.11 Debug Output

A static debugging class can be included in the SDK's API; Common::CDebugger. At the start of an applicationusing the API the developer may wish to define the following for more information to be displayed aboutbehaviour of the API.

#if defined(_DEBUG) CDebugger::EnableInfos( true ); CDebugger::EnableWarnings( true ); CDebugger::Enable( true ); CDebugger::SetLevelMask( FPGAIO );#endif

There are three types of message that can be displayed, Infos, Warnings, and Errors. Both Infos and Warningscan be disabled, Errors cannot be suppressed. The API may produce a lot of Infos making it hard to find theinformation that is desired when debugging, some of the information can be suppressed by using theCDebugger::SetLevelMask function. This will hide the specified Info and Warning messages, for example in thecode above the FPGAIO messages are suppressed.

Additional debug masks are listed below:

Mask Description

FPGAIO Read / Write IO to the FPGA

ThreadEvents Thread Events

InteruptEvents Interrupt Events

CardActions Actions such as open and closing cards

Table 8 : Debug Masks



9 Regsiter DetailsThis chapter documents the register details of the various components.

9.1 clink_base_adb3

This register map describes all the registers present in the clink_base_adb3 module used to control thesub-components of this entity.

9.1.1 REG_CLNK_CONTROL - Camera Link Control (0x0000)Provides basic control required to interact with the module.

31:28 27 26 25 24 16:13 12 11 10 9 8 7 3 2 1 0

RSV CLTI CLSI CLLI CLDI CC_VAL RST DVALI FVALI LVALI DVALO

CLKI USEZ USEY IRQD OD

Field Bit(s) Mode Description

Output Disable (OD) 0 RW Disable any image stream output. This can be used during reset toprevent spurious output.

IRQ Disable (IRQD) 1 RW Disable module from generating an interrupt.

Use Y (USEY) 2 RW Enable Y Channel (Medium Camera Link).

Use Z (USEZ) 3 RW Enable Z Channel (Full Camera Link). Note USEY must be used whenUSEZ is set high.

Clock Invert (CLKI) 7 RW Invert Camera Link input clock(s).

DVAL Optional(DVALO) 8 RW Set high to ignore DVAL and use LVAL to qualify valid data.

LVAL Invert (LVALI) 9 RW Invert LVAL

FVAL Invert (FVALI) 10 RW Invert FVAL

DVAL Invert (DVALI) 11 RW Invert DVAL

Reset CLink Chip(RST) 12 W Write high to start a reset of the Camera Link chip component. This is

required before a valid image stream can be acquired.

CC Direct Drive Value(CC_VAL) 16:13 RW In direct drive mode

CLR Reset Done(CLDI) 24 W Clear reset done interrupt.

CLR Lock Lost (CLLI) 25 W Clear link lost interrupt.

CLR Stopped Clock(CLSI) 26 W Clear clocks stopped interrupt.

CLR Timeout (CLTI) 27 W Clear reset timeout interrupt.

Reserved (RSV) 31:28 R Reserved for future use. Write with previous value.

Page 43Regsiter Detailsad-ug-0012_v2_3_CLINK-SDKUserManual.pdf


9.1.2 REG_CLNK_STATUS - Camera Link Status (0x0004)Provides critical status information on this module.

31:28 27 26 25 24 23:9 8 7 6:5 4 3 2 1 0

RSV3 IRQT IRQS

IRQL IRQD

RSV2 TX RX RSV1 DONE

RSV0

RUN TOUT

LOCK


Camera Locked(LOCK) 0 R Reports that Camera Link core is locked.

Reset Timed Out(TOUT) 1 R Indicates that the last reset timed out.

Camera ClockRunning (RUN) 2 R Indicates that a running pixel clock has been detected.

Reserved (RSV0) 3 R Reserved.

Reset Done (DONE) 4 R Reports the last reset issued has been completed.

Reserved (RSV1) 6:5 R Reserved.

RX data detected(RX) 7 R Indicates that serial data has been received from the Camera and is

ready to be read from the RX FIFO.

TX FIFO full (TX) 8 R Indicates that there is no more room in the TX serial buffer.


IRQ Reset Done(IRQD) 24 R Reset done IRQ.

IRQ Lock Lost (IRQL) 25 R Link lost IRQ.

IRQ Stopped Clock(IRQS) 26 R Pixel clock stopped IRQ.

IRQ Timeout (IRQT) 27 R Reset timeout IRQ.


9.1.3 REG_CLNK_OPMODE - Camera Link Mode (0x0008)Sets the expected input data format. This is used to decide how to pack the input data into the 32-bit or 64-bitoutput data stream.

31:8 7:0

RSV OPMODE


Camera Link Mode(OPMODE) 7:0 RW

A 8-bit register whose value is used to determine the data format andhence how data is packed after being decoded from the raw CLinkinput.

Reserved (RSV) 31:8 R Reserved.

The OPMODE field is used to select how clink_pix_swtich packs the input image stream into 32-bits words.There are a total of 18 data formats defined in the Camera Link specification plus one further proprietary format

Page 44 Regsiter Detailsad-ug-0012_v2_3_CLINK-SDKUserManual.pdf


used by Sony. Only BASE camera link formats (values 0x0 to 0x9 inclusive) are supported by theclink_base_adb3 module. Medium and Full formats (enumeration values 0x0a to 0x12) are supported by theadclink_full_adb3 component.

. 31:24 23:16 15:8 7:0

8 Pixel 3 Pixel 2 Pixel 1 Pixel 0

12 0000 Pixel 1 0000 Pixel 0

14 00 Pixel 1 00 Pixel 0

16 Pixel 1 Pixel 0

32 Pixel 0

Table 9 : Pixel Bits

9.1.4 REG_CLNK_START_LINE - Start Line (0x000C)Sets the first line in the Region of Interest.

31:16 15:0

RSV START


Start (START) 15:0 RW Set the first line to start acquiring data from.

Reserved (RSV) 31:16 R Reserved

9.1.5 REG_CLNK_END_LINE - End Line (0x0010)Sets the last line in the Region of Interest.

31:16 15:0

RSV END


End (END) 15:0 RW Sets the last line to acquire data from.


9.1.6 REG_CLNK_START_PIXEL - Start Pixel (0x0014)Sets the first column in the Region of Interest.

31:16 15:0

RSV START




Start (START) 15:0 RW Sets the first pixel in each line to acquire data from.


9.1.7 REG_CLNK_END_PIXEL - End Pixel (0x0018)Sets the last column in the Region of Interest.

31:16 15:0

RSV END


End (END) 15:0 RW Sets the last pixel in each line to acquire data from.


9.1.8 REG_CC4_HI - CC4 High Period (0x0020)Set period of CC4 high pulse or high clock period. 5.0 ns increments.

31:0

HIGH


High period (HIGH) 31:0 RW Period in 5.0 ns increments.

9.1.9 REG_CC4_LO - CC4 Low Period (0x0024)Set period of CC4 low pulse or low clock period. 5.0 ns increments.

31:0

LOW


Low period (LOW) 31:0 RW Period in 5.0 ns increments.

9.1.10 REG_COMMS_CONTROL - Serial control register (0x0028)Reset register for UART engine.

31:16 15 14:0

RSV1 RST RSV0




Reserved (RSV0) 14:0 R Reserved

Serial Reset (RST) 15 RW When '1' UART serial is held in reset.


9.1.11 REG_COMMS_CK_DIV - Serial clock divider (0x002C)Sets clock rate for serial communication with Camera.

31:16 15:0

RSV CK_DIV


Serial Clock Divider(CK_DIV) 15:0 RW

16 bit register used to set the serial clock divider to achieve the requiredbaud rate. Programming a value of N-1 divides the reference clock byN.


9.1.12 REG_COMMS_TXFIFO - Serial TX Data (0x0034)Send TX serial data FIFO.

31:8 7:0

RSV TX_DATA


Serial TX Data(TX_DATA) 7:0 W Write with TX data for sending to attached camera.


9.1.13 REG_COMMS_RXFIFO - Serial RX Data (0x0038)Buffered RX serial data FIFO.

31:8 7:0

RSV RX_DATA


Serial RX Data(RX_DATA) 7:0 RW Buffered RX data register. After reading a value from it write with any

value to pop the word out of the buffer.




9.1.14 REG_COMMS_TXSTATUS - Serial TX Status (0x003C)Status register for serial transmission to Camera.

31:15 14 13 12 11 10 9:4 3:0

RSV1 E E NEE NF NE RSV0 LEVEL


TX FIFO words(LEVEL) 3:0 R Number of TX words available.


Not Empty (NE) 10 R The TX buffer still has data in that is being transmitted.

Neally Full (NF) 11 R There is not much room left in the TX buffer.

Nearly Empty (NEE) 12 R The TX buffer is nearly empty.

Empty (E) 13 R The TX buffer is empty (transmission completed).

Full (E) 14 R The TX buffer is full.


9.1.15 REG_COMMS_RXSTATUS - Serial RX Status (0x0040)Status register for serial reception from Camera.

31:15 14 13 12 11 10 9:4 3:0

RSV1 E E NF NEE NE RSV0 LEVEL


RX FIFO words(LEVEL) 3:0 - .


Not Empty (NE) 10 - .

Nearly Empty (NEE) 11 - .

Nearly Full (NF) 12 - .

Empty (E) 13 - .

Full (E) 14 - .


9.1.16 REG_TEST - Test Pattern Register (0x0044)Test Pattern register

31:1 0

RSV A_ADDR




A Port Test(A_ADDR) 0 RW Replace Pixel data from 'A Port' with pixel address.


9.1.17 REG_CLK_X - Pixel Clock Rate (0x0048)Measured camera clock rate.

31:0

RATE


Clock Rate (RATE) 31:0 R Measured Camera Clock rate.

9.1.18 REG_CC_CTRL - CC Control Register (0x004C)Control register for pulse or clock generation on CC lines.

31:24 23:20 19:16 15:12 11:8 7:4 3:0

RSV PMODE STAT CLR SET EN TMODE


Timed Mode enable(TMODE) 3:0 RW Set high to enable CC clock or pulse generator. Set low to drive CC

lines using REG_CLNK_CONTROL:CC_VAL.

Timer Enable (EN) 7:4 RW Set high to enable the corresponding timers associated with each CCline.

Set (SET) 11:8 W A write to 'Set' bits will set the CC line high and restart the high periodtimer if in Timed mode.

Clear (CLR) 15:12 W A write to 'Clear' bits will set the CC line low and restart the low periodtimer if in Timed mode.

CC Status (STAT) 19:16 R The current state of the CC lines can be checked using the 'CC Status'bits.

Pulse Mode(PMODE) 23:20 W When a pulse mode bit is set the corresponding CC line timer will

pause after completing the current period

Reserved (RSV) 31:24 R .




31:0

HIGH




31:0

LOW




31:0

HIGH



9.1.22 REG_CC2_LO - CC2 Low Period (0x005C)Set period of CC2 low pulse or low clock period. 5.0 ns increments.

31:0

LOW




31:0

HIGH






31:0

LOW



9.1.25 REG_MAJOR_RELEASE - Major Release Version (0x0068)A register containing versioning information.

31:0

MAJOR_RELEASE


(MAJOR_RELEASE) 31:0 R A 32-bit number.

9.1.26 REG_MINOR_RELEASE - Minor Release Version (0x006C)A register containing versioning information.

31:0

MINOR_RELEASE


(MINOR_RELEASE) 31:0 R A 32-bit number.

9.1.27 REG_MAJOR_BUILD - Major Build Version (0x0070)A register containing versioning information.

31:0

MAJOR_BUILD




(MAJOR_BUILD) 31:0 R A 32-bit number.

9.1.28 REG_MINOR_BUILD - Minor Build Version (0x0074)A register containing versioning information.

31:0

MINOR_BUILD


(MINOR_BUILD) 31:0 R A 32-bit number.

9.1.29 REG_SYNC_SELECT - Channel Sync Select (Medium/Full Only) (0x0078)This register is used to specify which bit in the serial Camera Link data is used to synchronize channel whenmore than one channel is being used.

This register should not need to be modified.

24:16 16:8 8:0

Z_SYNC Y_SYNC X_SYNC


X Sync (X_SYNC) 8:0 RW Select the data bit used to synchronise the X channel to Y and Z.Recommend and default value: 0x18

Y Sync (Y_SYNC) 16:8 RW Select the data bit used to synchronise the X channel to X and Z.Recommend and default value: 0x18

Z Sync (Z_SYNC) 24:16 RW Select the data bit used to synchronise the X channel to X and Y.Recommend and default value: 0x18



9.2 ocp_int_controller

The ocp_int_controller has a very simple set of register that provide the facilities to multiplex multiple inputinterrupts into a single output interrupt.

9.2.1 IRQ_ENABLE - IRQ Enable (0x0080)Each bit in this register enables a single input interrrupt.

31:0

IRQEN


IRQ Enable (IRQEN) 31:0 RW Enable interrupt mask.

9.2.2 IRQ_CLEAR - IRQ Clear (0x0084)Writing a bit in this register acknowledges the interrupt seen on one of the inputs.

31:0

IRQC


IRQ Clear (IRQC) 31:0 W Clear interrupt register.

9.2.3 IRQ_STATUS - IRQ Status (0x008C)When the output interrupt is asserted that register shows which input interrupt source(s) caused the outputinterrupt to be assered. After performing any nessacary action the corrisponding IRQ_CLEAR bit should bewritten to acknowledge the processing of the interrupt.

31:0

IRQS


IRQ Status (IRQS) 31:0 RW Enable status.



9.3 adb3_ocp_data_sink

The adb3_ocp_data_sink registers are described below.

9.3.1 CTRL - Control (0x0000)Data sink control information.

31:9 8 7 6 5 4 3 2 1 0

- LD SD BIE FL DIE DF BF PS RST


Reset (RST) 0 RWSetting this bit will cleanly complete the current sync interface OCPtransaction, reset the circular buffer elements counters, and return thestate machine to the IDLE State. This bit is auto-cleared.

Pause (PS) 1 RWSetting this bit will cleanly complete the writing of the current circularbuffer element, and hold the state machine in the PAUSE State.Clearing this bit will cleanly resume writing to the circular buffer.

Buffer Free (BF) 2 RW

Setting this bit will deduct BUFF_FREE_CNT elements from the circularbuffer elements used counter, and add BUFF_FREE_CNT elements tothe circular buffer elements read counter.This bit is auto-cleared.

Drop Free (DF) 3 RWSetting this bit will deduct DROP_FREE_CNT packets from the droppedpackets counter.This bit is auto-cleared.

Dropped IRQ Enable(DIE) 4 RW

Setting this bit will enable activation of the ctrl_irq interrupt requestoutput when the dropped packets counter is non-zero.Clearing this bit will disable activation of the ctrl_irq interrupt requestoutput from this source.

Flush Last (FL) 5 RW

Setting this bit will select flushing of the FIFO until its output dataindicates the end of the current packet (DataLast).Clearing this bit will select flushing of the FIFO until it is empty.Flushing will occur in the state machine PAUSE State.

Buffer IRQ Enable(BIE) 6 RW

Setting this bit will enable activation of the ctrl_irq interrupt requestoutput when the circular buffer used counter reaches BUFF_INT_CNT.Clearing this bit will disable activation of the ctrl_irq interrupt requestoutput from this source.

Short Drop (SD) 7 RW

Setting this bit will enable discarding (dropping) of packets which areshorter than the BUFF_SIZE expected length. Dropping a short packetwill cause the dropped packet counter to be incremented.Clearing this bit will enable padding of short packets to the BUFF_SIZE expected length.




Long Drop (LD) 8 RW

Setting this bit will enable discarding (dropping) of packets which arelonger than the BUFF_SIZE expected length. Dropping a long packetwill cause the dropped packet counter to be incremented.Clearing this bit will enable truncating of long packets to theBUFF_SIZE expected length.

- 31:9 RW Reserved. Write with previously read value.

9.3.2 BUFF_FREE_CNT - Buffer Elements Free Count (0x0004)Number of elements to change the circular buffer elements used and read counters by on buffer free.

31:16 15:0

- BUFF_FREE_CNT


Free Count(BUFF_FREE_CNT) 15:0 RW

Deduct this number of elements from the circular buffer elements usedcounter, and add this number of elements to the circular bufferelements read counter when the BF bit of the Control register is set.Defaults to dflt_buff_free_cnt.


9.3.3 STATUS - Status (0x0008)Data sink status information.

31:16 15 14 13 12 11 10:8 7 6 5 4 3 2 1 0

- D DL DS DOK - STAT S7 S6 S5 S4 S3 S2 S1 S0


FSM Idle (S0) 0 RO Current FSM state is IDLE State.

FSM Flush (S1) 1 RO Current FSM state is FLUSH State.

FSM Pause (S2) 2 RO Current FSM state is PAUSE State.

FSM Wait Burst (S3) 3 RO Current FSM state is WAITING_BURST State.

FSM Wait Cmd (S4) 4 RO Current FSM state is WAITING_CMD State.

FSM Wait Data (S5) 5 RO Current FSM state is WAITING_DATA State.

FSM Burst Complete(S6) 6 RO Current FSM state is BURST_COMPLETE State.

FSM Data Complete(S7) 7 RO Current FSM state is DATA_COMPLETE State.




Status (STAT) 10:8 RO

Status of last completed packet as follows:000 OK: No data dropped. Packet data is expected length at 'data last'.001 Short: No data dropped. Packet data is short at 'data last'.010 Long: No data dropped. Packet data is long at expected length.100 Drop OK: Data dropped. Packet data is expected length at 'datalast'.101 Drop Short: Data dropped. Packet data is short at 'data last'.110 Drop Long: Data dropped. Packet data is long at expected length.111 Drop: Data dropped. Packet data length is unknown (no 'data last'and not expected length).

- 11 RO Reserved.

Drop OK (DOK) 12 RO Cumulative status of completed packets: Data dropped, data correctlength at DataLast. Cleared by DROP_FREE bit of the Control register.

Drop Short (DS) 13 RO Cumulative status of completed packets: Data dropped, data short atDataLast. Cleared by DROP_FREE bit of the Control register.

Drop Long (DL) 14 RO Cumulative status of completed packets: Data dropped, data long atexpected length. Cleared by DROP_FREE bit of the Control register.

Drop (D) 15 RO Cumulative status of completed packets: Data dropped, before data lastor expected length. Cleared by DROP_FREE bit of the Control register.

- 31:16 RO Reserved.

9.3.4 DROP_CNT - Dropped Packets Count (0x000C)Number of dropped packets.

31:16 15:0

- DROP_CNT


Dropped Count(DROP_CNT) 15:0 RO Number of packets that have been discarded (dropped) due to the FIFO

being full.


9.3.5 BUFF_INT_CNT - Buffer Elements IRQ Count (0x0010)Minimum number of occupied circular buffer elements required to produce an interrupt request.

31:16 15:0

- BUFF_INT_CNT




IRQ Count(BUFF_INT_CNT) 15:0 RW Minimum number of used circular buffer elements required to activate

the ctrl_irq interrupt request output. Defaults to dflt_buff_int_cnt.


9.3.6 BUFF_MAX_CNT - Buffer Elements Maximum Count (0x0014)Maximum number of elements in the circular buffer.

31:16 15:0

- BUFF_MAX_CNT


Maximum Count(BUFF_MAX_CNT) 15:0 RW Number of elements to buffer.


9.3.7 START_ADDR_LS - Buffer Start Address Lower (0x0018)Address of first element in the circular buffer (LSBs).

31:0

START_ADDR_LS


Start Address Lower(START_ADDR_LS) 31:0 RW Lower 32-bits of OCP address for first element.

9.3.8 START_ADDR_MS - Buffer Start Address Upper (0x001C)Address of first element in the circular buffer (MSBs).

31:0

START_ADDR_MS


Start Address Upper(START_ADDR_MS) 31:0 RW Most significant 32-bits of byte address of first location in circular buffer.

Defaults to dflt_start_addr(63:32).



9.3.9 BUFF_SIZE - Buffer Elements Size (0x0020)Size of each element in the circular buffer.

31:28 27:0

- BUFF_SIZE


Buffer Size(BUFF_SIZE) 27:0 RW Size of circular buffer elements in bytes. Must be multiple of 16 bytes.

Defaults to dflt_buff_size.


9.3.10 BUFF_WRITE_CNT - Buffer Elements Write Count (0x0024)Number of the current element being written to the circular buffer from the FIFO. Value will increment oncompletion of an element write.

31:16 15:0

- BUFF_WRITE_CNT


Write Count(BUFF_WRITE_CNT) 15:0 RO

Contains the number of the circular buffer element available to be, orbeing, written to. Maximum value should be BUFF_MAX_CNT fromBuffer Elements Maximum Count register. Defaults to 0.


9.3.11 BUFF_READ_CNT - Buffer Elements Read Count (0x0028)Number of the earliest complete element in the circular buffer. Value will increase by BUFF_FREE_CNT elements on completion of a buffer free.

31:16 15:0

- BUFF_READ_CNT


Read Count(BUFF_READ_CNT) 15:0 RO

Contains the number of the earliest complete circular buffer element.Maximum value should be BUFF_MAX_CNT from Buffer ElementsMaximum Count register. Defaults to 0.




9.3.12 BUFF_USED_CNT - Buffer Elements Used Count (0x002C)Number of occupied elements in the circular buffer. Value will increment on completion of an element write. Valuewill decrease by BUFF_FREE_CNT elements on completion of a buffer free.

31:16 15:0

- BUFF_USED_CNT


Used Count(BUFF_USED_CNT) 15:0 RO

Contains the number of occupied elements in the circular buffer.Maximum value should be BUFF_MAX_CNT from Buffer ElementsMaximum Count register. Defaults to 0.


9.3.13 DROP_FREE_CNT - Dropped Packets Free Count (0x0030)Number of packets to be deducted from the dropped packets counter.

31:16 15:0

- DROP_FREE_CNT


Free Count(DROP_FREE_CNT) 15:0 RW Deduct this number of packets from the dropped packets counter when

the DF bit of the Control register is set. Defaults to dflt_drop_free_cnt.




10 SDK ContentsThe SDK structure is as follows:

XRM-CLINK SDK - root of XRM-CLINK SDK installation

api - Headers and Source code for API and utilities

include

linux

lib

msvc

source

apps - Source code for example applications

linux

msvc

source - Example application source code

vxworks

bin - Compiled binary applications

win32

bit - FPGA bitsteams

deps - Dependancies

doc

firmware

fpga - FPGA source code

coregen

cores

ise

make

msim

nmake

prj

scr

ucf

vhdl

libraries

user_app

Page 60 SDK Contentsad-ug-0012_v2_3_CLINK-SDKUserManual.pdf


11 Migration11.1 2.2.2->2.3.x

Update API.

Update FPGA components, prj and ucf files.

No changes required in custom_app.

Remove any interrupt handing code for the Camera's serial interface.

Page 61Migrationad-ug-0012_v2_3_CLINK-SDKUserManual.pdf


12 Known Issues- Simulation is slow. This is due to the amount of time needed to perform phase alignment with the input

Camera Link streams. Workaround: Create test benches only to simulate the components that requiredebugging. A faster simulation model of the adclinkchip component may become available in the future.

- Subtle inconsistency between layout of api and apps folder vs. deps folder. The structure of the depsfolder will be updated in a future release.

Page 62 Known Issuesad-ug-0012_v2_3_CLINK-SDKUserManual.pdf


Revision History

Revision Date Description of Change

2.2.2.x March-2011 Initial draft

2.2.2.x Augst-2012 Updated

2.2.2.x November-2012 Updated

Page 63Known Issuesad-ug-0012_v2_3_CLINK-SDKUserManual.pdf


Page Intentionally left blank

Address: 4 West Silvermills Lane,Edinburgh, EH3 5BD, UK

Telephone: +44 131 558 2600Fax: +44 131 558 2700email: [email protected]: http://www.alpha-data.com

Address: 3507 Ringsby Court Suite 105,Denver, CO 80216

Telephone: (303) 954 8768Fax: (866) 820 9956 toll freeemail: [email protected]: http://www.alpha-data.com

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