Xilinx XAPP596 4K2K Up-Converter Reference Design reference designs are up-converter, frame rate...
Transcript of Xilinx XAPP596 4K2K Up-Converter Reference Design reference designs are up-converter, frame rate...
XAPP596 (v1.0.2) June 28, 2013 www.xilinx.com 1
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Summary In the digital display market, the next innovation wave—ultra-high definition (UHD) 4K2K—is now emerging. Getting to market faster than the competition with 4K2K viewing experiences is the challenge for product development designers. Xilinx® Kintex®-7 FPGA Display Targeted Reference Designs give designers immediate access to the power efficiency and price-performance of 28 nm 7 series FPGA devices for efficiently managing increased bandwidth and algorithm complexity. Xilinx provides three reference designs enabling customers to concentrate on product differentiation by providing basic infrastructure for 4K2K digital display signal processing. These reference designs are up-converter, frame rate converter, and mosaic (multi-window). This document addresses the first reference design, the up-converter.
Introduction This high definition (HDTV) to 4K2K up-converter reference design enables up-conversion from 1080p HDTV to 4K2K progressive images. The up-conversion results in showing HDTV content, which is very popular in broadcasting and packaged media, on a 4K x 2K flat panel display.
The reference design is built from the following LogiCORE™ IP in the Xilinx Video and Image Processing Pack (VIPP):
• Video Scaler
• On-screen Display (OSD)
This reference design has two display modes. One is the up-converter mode, which shows an HDTV image on 4K2K flat display panels in various sizes, enabling zoom up to twice the original sizes. The other is the mosaic mode, which shows the same HDTV input images on each quadrant of a 4K2K screen, in live motion pictures or still images.
This document contains the following contents that enable designers to use the reference design as the basis of their 4K2K digital display product development:
• Reference design demonstration setup
• Reference design overview
• Build an HDTV to 4K2K reference design project
The advantage for application designers is that they can use this reference design for the basis of their own 4K2K up-converters, enabling them to concentrate on picture quality tuning. The picture quality of 4K2K up-converters is key to the market growth of 4K2K display products, which then enables the utilization of the large volume of HDTV (1080p @60 Hz) content available in the market today.
Application Note: Kintex-7 Family
XAPP596 (v1.0.2) June 28, 2013
4K2K Up-Converter Reference DesignAuthor: Yasushi Tatehira
Demonstration Setup
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Demonstration Setup
The demonstration involves both hardware and software setups. To quickly bring up the demonstration, the EDK project ships with a pre-built file in the EDK/implementation directory (file name: download.bit).
Hardware Inventory
The hardware required for the demonstration includes:
• Inrevium Kintex-7 FPGA ACDC1.0 base board (TB-7K-325T-IMG)
• Inrevium HDMI1.4a interface transmitter card (TB-FMCL-HDMI2-TX) x2
• Inrevium HDMI1.4a interface receiver card (TB-FMCL-HDMI2-RX) x1
• HDMI (1080p) video source
• HDMI cable (video input cable)
• HDMI to DVI cable or HDMI cable (video output cable) x4
• PC with at least one free USB port
• UART cable
• Download cable (Platform cable USB)
• 4K2K monitor supporting 4x DVI or HDMI quadrant input (for example, Astro Design DM3410-A, SONY SRM-L560)
Hardware Setup
Figure 1 illustrates the setup of the 4K2K up-converter reference design demonstration hardware.
X-Ref Target - Figure 1
Figure 1: Demonstration Hardware
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HDMI Input/Output Screen Position
Top Left(T/L)
Top Right(T/R)
Bottom Left(B/L)
Bottom Right(B/R)
(8) B/R HDMI Output
(10) Download Cable (CN1)Platform Cable USB
(6) T/R HDMI Output
(5) T/L HDMI Output
(1) HDMI Input
(15) UART Cable (CN17)
(13) DIP Switch (SW5)
(14) LED (LED23, LED24)
(12) Reset Switch (PSW1)
(11) Power Switch (SW1)ON <--> OFF
(9) AC/DC Adaptor Input
(7) B/L HDMI Output
Demonstration Setup
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Cable Connections and Board Settings
Bank Supply Voltage
Set the bank supply voltage to 2.5V (see Table 1).
VCCADC/VREFP Voltage
Open the supply voltage to VCCADC/VREFP (see Figure 2).
Table 1: FPGA Bank and Peripheral Device Voltage Selections
Bank Function VoltageVoltage Selection
SEL 2.5V 3.3V
HR12/13/14
FMC_LPC1(CN5)Variable
(3.3V/2.5V)(1) JP28 1-2 short 2-3 shortFMC_LPC2(CN6)
QSPI
HR15/16/17/18FMC_HPC1(CN3)FMC_HPC2(CN4)
Variable(3.3V/2.5V)(1) JP24 1-2 short 2-3 short
HP32/33/34 DDR3, DSW, LED, PSW, UART 1.5V - - -
Notes: 1. By default, voltage is set to 2.5V.
X-Ref Target - Figure 2
Figure 2: VCCADC/VREFP Voltage Selection
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Demonstration Setup
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DIP Switch Settings
FPGA Board DIP Switch Settings
For the DIP switch location, see item (13) in Figure 1.
SW5-8 ON
SW5-7 ON
SW5-6 ON: Controlled from UARTOFF: Auto-demonstration sequence after initialization
SW5-5 ON
SW5-4 ON
SW5-3 ON
SW5-2 ON
SW5-1 ON
HDMI1.4 RX Board DIP Switch Settings
DSW-8 Not used
DSW-7 Not used
DSW-6 Not used
DSW-5 ON
DSW-4 ON
DSW-3 ON
DSW-2 ON
DSW-1 ON
If there is an error on the screen, set DSW-5 to OFF. DSW-5 on the Rx board adjusts the clock phase to receive data from the HDMI chip.
HDMI1.4 TX Board DIP Switch Settings
DSW-8 Not used
DSW-7 Not used
DSW-6 Not used
DSW-5 ON
DSW-4 See below
DSW-3 See below
DSW-2 See below
DSW-1 See below
Change DSW-1 to DSW-4 in accordance with the signal format of the monitor:
• RGB 08 bit output: DSW-1 OFF, DSW-2 ON, DSW-3 ON, DSW-4 ON
• RGB 10 bit output: DSW-1 ON, DSW-2 ON, DSW-3 OFF, DSW-4 ON
• RGB 12 bit output: DSW-1 ON, DSW-2 OFF, DSW-3 ON, DSW-4 ON
If there is an error on the screen, set DSW-5 to OFF. DSW-5 on the Tx board adjusts the clock phase to transmit data to the HDMI chip.
Demonstration Setup
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Demonstration
Cable Connection
Connect the signal source and monitor as shown in Figure 1.
1. (1) Connect HDMI input cables.
2. (5)–(8) Connect HDMI output cables.
3. (9) Connect AC/DC adaptor cables.
4. (10) Connect download cable.
5. (15) Connect UART cable. For UART configuration, see Figure 3.
HDMI input/output positions are shown in the top left of Figure 1.
Data Downloading
1. (11) Turn the power switch on and download the FPGA program (download.bit in the EDK/implementation directory), using the program cable and the IMPACT downloading tool.
2. When the FPGA configuration is complete, (14) LED24 (red) turns off and LED23 (green) turns on.
3. (13) Set DIP switches and (12) press the Reset switch.
4. Wait for initialization to finish (writing the OSD logo from flash memory takes about 25 seconds).
Demonstration
1. Wait for the UART display screen, as shown in Figure 4.
2. Reset the HDMI 1.4 TX board.
3. Execute the 4K2K up-converter/demonstration mode by UART using the a command.
4. Press any key to break.X-Ref Target - Figure 3
Figure 3: UART Configuration
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Demonstration Setup
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Data Flow
Figure 5 shows the data flow when the combined demo sequence of the mosaic and up-converter modes is initiated by the a command on the UART screen. In Figure 5, the red arrows show the data flow throughout the input from the HDMI Rx board to the HDMI Tx board.
The data flow and timing for each operational mode is described in Operational Mode, page 24.
X-Ref Target - Figure 4
Figure 4: UART Display Screen
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Memory bandwidth and utilization calculations shown in Figure 5 are further described in Table 2. The memory utilization of this design is 38.9%, allowing additional memory data access for additional functionality.
4K2K Up-Converter Reference Design
Overview
This function can output 4K2K at 60 frames per second (fps) by inputting one 1080p 60 and performing scaling and OSD processing. The video processing IP in this design are the scaler and the OSD, which come from the Xilinx Video and Image Processing Pack. The external DDR3-SDRAM operates in 1600 Mb/s, 64 bits of the video IP, and performs AXI4-Stream data communication. The following provides a cursory description of video IP.
X-Ref Target - Figure 5
Figure 5: Data Flow
(Not used incurrent design)
xsvi_to_axi4s
axi_7series_ddrx
DDR3-SDRAM 1600M (x64 bit = 12,800 MB/s)
axi_scaler
axi_osd
MicroBlaze Processoraxi_intc
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S_AXI
axi_vtc
RX
RX
x4
64-bit
AXI4_InterConnect
xsvi_mux_tx
M_AXI
axi_vdma_deint
M_A
XIS
axi_vdma_scaler axi_vdma_osd
AXI4LITE_InterConnect
hdmi_rx
TB
-FM
CH
-HD
MI2-R
XH
DM
I1.4
xsvi_mux_rx
hdmi_tx
TB
-FM
CH
-HD
MI2-T
XH
DM
I1.4axi_uartlite
TX
TX
x4
x4 x4 x4
x4
x4 x4 x4
x4
2 3 4 51
Table 2: Memory Calculations
Memory Bandwidth 1
Memory Bandwidth 2
Memory Bandwidth 3
Memory Bandwidth 4
Memory Bandwidth 5 Total
Frame buffer size(H x V x bits) N/A 1920 *1080 *32 1920 *1080 *32 3840 *2160 *32 1920*1080 *32
fps N/A 60 15 15 60
Channels N/A 1 4 4 4
Memory bandwidth (MB/s) 0 498 498 1991 1991 4978
DDR3 SDRAM memory bandwidth (MB/s) 1600M x 64 bits 12800
Memory utilization (%) 38.9
4K2K Up-Converter Reference Design
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This design provides these two types of demonstration modes:
• 4K2K up-converter mode
• Single input mosaic mode
In the 4K2K up-converter mode, the 1080p (FHD) image source is converted into various image sizes on a 4K2K screen up to a 3840 x 2160 (4K2K) image.
FPGA Specifications
Table 3 lists the FPGA specifications.
Utilization/static timing analysis (STA) value varies depending on the tool version and tool options.
Note: The data in Table 3 indicates representative values and not guaranteed values.
Design Development Environment
Table 4 shows the FPGA development environment.
Table 3: FPGA Specifications
Item Description Remarks
Device model XC7K325T-2FFG900
Operational frequency
System clock 50 MHz
HDMI receive clock Max 148.5 MHz
HDMI transmit clock 148.5 MHz
AXI clock 160 MHz
DDR user clock 200 MHz
DDR clock 800 MHz
FPGA resource utilization
Internal slice 50,812/50,950 99%
Internal register 196,176/407,600 48%
Internal LUT 154,408/203,800 75%
I/O pin 413/500 82%
Internal block RAM (RAMB36E1) 361/445 81%
Internal block RAM (RAMB18E1) 47/890 5%
Internal DSP/multiplier 330/840 39%
Table 4: Design Development Environments
Item Description Remarks
OS Windows 7 64-bit SP3 Japanese
Synthesis tool ISE® Design Suite Foundation (ISE Service Pack 14.3)
Embedded Development Kit (EDK 14.3)
Development languages Verilog/VHDL
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4K2K Up-Converter Reference Design Description
Functional Block Diagram
Figure 6 shows the functional block diagram of the FPGA. This system converts a 1080p @60 fps image into a 4K2K @60 fps image using the Xilinx scaler IP cores with OSD overlaying.
1080p HDMI input is fed to a sxvi_axi4s block through input signal reception blocks.
The output of the sxvi_axi4s is fed into the scaler through the AXI4 interconnect.
X-Ref Target - Figure 6
Figure 6: Functional Block Diagram
xsvi_to_axi4s
axi_7series_ddrx
DDR3-SDRAM 1600M (x 64 bit = 12,800 Mb/s)
axi_scaler
axi_osdMicroBlazeaxi_intc
Progressive
RGB444 30 bit
1920xc1080x60pClock:
148.5 MHz
Progressive
RGB444 30 bit1920xc1080x60p
Clock:148.5 MHz
XAPP596_06_012133
S_AXI
axi_vtc
RX
RX
x4
64 bit
AXI4_InterConnect
xsvi_mux_tx
M_AXI
axi_vdma_deint
M_A
XIS
axi_vdma_scaler axi_vdma_osd
AXI4LITE_InterConnect
hdmi_rx
TB
-FM
CH
-HD
MI2-R
XH
DM
I1.4
xsvi_mux_rx
hdmi_tx
TB
-FM
CH
-HD
MI2-T
XH
DM
I1.4
axi_uartlite
TX
TX
x4
x4 x4
x4
x4 x4 x4
x4
AXI4-Lite Protocol Bus AXI4 Protocol Bus AXI4-S Protocol Bus XSVI Protocol Bus
DDR3 User Clock160 MHz
DDR3 Clock800 MHz
System Clock50 MHz
HDMI RX ClockMax 148.5 MHz
HDMI TX Clock148.5 MHz
Note 1:
Interface/Progressive
RGB444 30 bit
XSVI
Clock 150 MHz
Note 2:
RGB444 30 bit
AXI Stream
Clock 150 MHz
Progressive
Progressive
RGB444 30 bit
XSVI
Clock 150 MHz
Progressive
RGB444 30 bit
XSVI
Clock 150 MHz
RGB444 30 bit
AXI Stream
Clock 150 MHz
RGB444 30 bit
AXI Stream
Clock 148.50 MHz
RGB444 30 bit
AXI Stream
Clock 148.50 MHz
RGB444 30 bit
XSVI
Clock 148.50 MHz
RGB444 30 bit
AXI Stream
Clock 148.50 MHz
4K2K Up-Converter Reference Design
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The Xilinx scaler can achieve an output of 3840 x 2160p (4K2K) @24 fps (see DS840, LogiCORE IP Video Scaler v4.0). This reference design uses four Xilinx scaler cores in four-frame sequential multiplexing, resulting in up-conversion into 4K2K @60 fps (15 fps * 4). This sequence is shown in Figure 7. The timing of this sequence is described in Figure 16 in Operational Mode, page 24.
The output of the scaler goes to the OSD module so that on-screen display characters for the demonstration can be added.
X-Ref Target - Figure 7
Figure 7: 4K2K Up-Converter Time Multiplex Use of Scaler
1920
3840
1080
2160
FHD1
Scaler No. 1 Scaler No. 2
1/60 sec1/15 sec
Scaler No. 3 Scaler No. 4 Scaler No. 1 Scaler No. 2 Scaler No. 3 Scaler No. 4
FHD2 FHD3 FHD4 FHD2 FHD3 FHD4FHD1
4K2K2
4K2K1
4K2K3
4K2K4
4K2K1
4K2K2
4K2K3
4K2K4
FHD
4K2K
ScalerInput
ScalerOutput
1080p @ 60HzVideo Input
Video I/F xsvi_to_axi4s Scaler No. 1FHD � 4K2KVideo Scaler
Scaler No. 2Scaler No. 3
Scaler No. 4
DDR3 Memory Interface Block
DDR3-SDRAM
OnscreenDisplay
4K2K @ 60HzVideo Ouput
Four of FHD � 4K2K Scalers
XAPP596_07_013113
4K2K Up-Converter Reference Design
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Clock and Reset
Figure 8 shows an FPGA clock generation diagram. A 200 MHz input clock is fed to clock generation blocks and the DDR user clock, HDMI TX clock, and 50 MHz system clocks are generated. HDMI RX clocks are buffered and supplied to the system.
X-Ref Target - Figure 8
Figure 8: Clock Generation
hdmi_rx_0
clock_generator_0
clk_gen_tx_0
clk_gen_ddr_0
tb7k_glue_0
BUFG
PLLE2_ADVCLKFBIN
CLKOUT0
CLKOUT1
CLKIN1CLKOUT2
MMCME2_ADVCLKFBIN
CLKIN1 CLKOUT0
CLKFBOUT
CLKFBOUT
CLKOUT3
IBUFDSCLK_200MHZ_OSC_P/N
BUFG
BUFG
BUFG
MMCME2_ADVCLKFBIN
CLKIN1 CLKOUT0
CLKFBOUT
IDELAYE2
HDMIR0_CLKBUFG
axi_7series_ddrx_0
HDMI TX Clock148.5 MHz
CLK_200MHZ_OSC
hdmi_rx_1IDELAYE2 BUFG
hdmi_rx_2IDELAYE2 BUFG
hdmi_rx_3IDELAYE2 BUFG
HDMIR1_CLK
HDMIR2_CLK
HDMIR3_CLK
PLLE0_clk_200MHz
XAPP596_08_012113
MMCM0_clk_50MHz
System Clock50 MHz
DDR User Clock200 MHz
Input HDMI RX Channel 0 Clock74.25 MHz/148.5 MHz
freq_refclk : 800 MHz, Duty 50%, Phase 45 degrees
mem_refclk : 800 MHz, Duty 50%, Phase 0 degrees
sync_pulse : 50 MHz, Duty 6.25%,
Phase 9.84375 degrees
clk : 200 MHz, Duty 50%, Phase 0 degrees
Input HDMI RX Channel 1 Clock74.25 MHz/148.5 MHz
Input HDMI RX Channel 2 Clock74.25 MHz/148.5 MHz
Input HDMI RX Channel 3 Clock74.25 MHz/148.5 MHz
Input clock200 MHz
tx_clk
4K2K Up-Converter Reference Design
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Figure 9 shows a reset generation diagram. Several reset signals are generated in synchronization to the clocks by proc_sys_reset block from the original reset input.
Functional Descriptions of Each Block
When the user opens the EDK project file, a listing of the blocks that are on the block diagram appears, as shown in Figure 6, page 9. Figure 10 shows the screen shot of the directory listing shown when you open the EDK project. The red marked area shows the block list. (Not all the blocks in Figure 6 are shown in this screen shot.)
X-Ref Target - Figure 9
Figure 9: Reset Generation
proc_sys_reset_0
Ext_Reset_In
Dcm_locked
Slowest_sync_clk
clk_gen_ddr_0
clk_gen_tx_0
clock_generator_0
LOCKED
LOCKED
LOCKED
XAPP596_09_082712
RST
RST
RST
MB_Reset
Interconnect_aresetn
MB_Debug_Sys_Rst
BUS_STUCT_RESETidelay_ctrl
iodelay_ctrl_rdy
sys_rst
microblaze
debug_module
microblaze_0_ilmb/microblaze_0_dlmb
NOT
OR
AND
Internal Asynchronous ResetActive-Low
RESET_N
Input Asynchronous ResetActive-Low
NOT
4K2K Up-Converter Reference Design
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Description of Each Block and Resource Utilization
Table 5 provides a description of each block in Figure 6 with resource utilization.
X-Ref Target - Figure 10
Figure 10: Directory Listing of Source Files
XAPP596_10_082912
Table 5: Description of Each Block and Resource Utilization
# Module Name Slice Register LUT+LUTRAM RAM Description
1 tb7k_glue_0 0 0 0 0 Differential clock input/output buffer
2 clock_generator_0 0 0 0 0 System clock generator
3 clk_gen_tx_0 0 0 0 0 Transmit clock generator
4 clk_gen_ddr_0 0 0 0 0 DDR clock generator
5 util_vector_logic_0 1 0 1 0 NOT logic function
6 util_vector_logic_1 1 0 1 0 NOT logic function
7 util_vector_logic_2 1 0 1 0 OR logic function
8 util_vector_logic_3 1 0 1 0 AND logic function
9 util_vector_logic_4 1 0 1 0 AND logic function
10 proc_sys_reset_0 17 31 21+2 0 Reset generator
11 microblaze_0_ilmb 1 1 0 0 MicroBlaze instruction local memory bus
12 microblaze_0_dlmb 1 1 0 0 MicroBlaze data local memory bus
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13 microblaze_0_i_bram_ctrl 2 2 2 0 MicroBlaze instruction bram controller
14 microblaze_0_d_bram_ctrl 4 2 4 0 MicroBlaze data bram controller
15 microblaze_0_bram_block 0 0 0 32 MicroBlaze bram
16 microblaze_0 3111 4192 5494+377 2 MicroBlaze
17 debug_module_0 95 130 133+23 0 MicroBlaze Debug Module
18 axi_intc_0 212 287 387 0 Interrupt controller
19 axi_uartlite_0 74 87 105+18 0 UART Lite
20 axi_spi_0 172 182 252+16 0 SPI controller
21 startupe2_ctrl_0 0 0 0 0 startupe2 module
22 axi4lite_peripherals_0 1848 4202 2470+60 0 axi4lite interconnect 0
23 axi4lite_peripherals_1 1422 3573 2260+72 0 axi4lite interconnect 1
24 axi4lite_peripherals_2 1911 4492 2792+288 0 axi4lite interconnect 2
25 axi4_peripherals_0 19526 59062 48400+7569 26 axi4 interconnect 0
26 axi4_peripherals_1 3756 10406 9266+1368 0 axi4 interconnect 1
27 axi_gpio_0 88 227 241+42 0 GPIO
28 hdmi_rx_0 102 300 207+60 0 HDMI receive controller 0
29 hdmi_rx_1 101 300 219+60 0 HDMI receive controller 1
30 hdmi_rx_2 94 300 217+60 0 HDMI receive controller 2
31 hdmi_rx_3 97 300 223+60 0 HDMI receive controller 3
32 xsvi_mux_rx_0 101 314 260 0 Receive-side XSVI MUX
33 xsvi_to_axi4s_0 22 52 25 1 XSVI Interface to AXI4S interface 0
34 xsvi_to_axi4s_1 22 52 28 1 XSVI Interface to AXI4S interface 1
35 xsvi_to_axi4s_2 22 52 28 1 XSVI Interface to AXI4S interface 2
36 xsvi_to_axi4s_3 20 52 32 1 XSVI Interface to AXI4S interface 3
37 axi_vdma_deint_0 1694 4296 2722+201 7 XSVI to AXI Video Direct Memory Access 0
38 axi_vdma_deint_1 1719 4296 2453+201 7 XSVI to AXI Video Direct Memory Access 1
39 axi_vdma_deint_2 1584 4296 2864+200 7 XSVI to AXI Video Direct Memory Access 2
40 axi_vdma_deint_3 1680 4296 2631+201 7 XSVI to AXI Video Direct Memory Access 3
41 axi_scaler_0 1454 4828 2801+201 49 Video Scaler IP 0
42 axi_scaler_1 1487 4828 2661+201 49 Video Scaler IP 1
43 axi_scaler_2 1443 4828 2748+201 49 Video Scaler IP 2
44 axi_scaler_3 1469 4828 2611+201 49 Video Scaler IP 3
45 axi_vdma_scaler_0 2976 7463 4681+346 14 Scaler AXI Video Direct Memory Access 0
46 axi_vdma_scaler_1 3053 7463 4507+345 14 Scaler AXI Video Direct Memory Access 1
47 axi_vdma_scaler_2 2995 7463 4622+346 14 Scaler AXI Video Direct Memory Access 2
48 axi_vdma_scaler_3 2975 7463 4870+346 14 Scaler AXI Video Direct Memory Access 3
49 axi_vtc_0 516 736 789+2 0 AXI video timing controller
Table 5: Description of Each Block and Resource Utilization (Cont’d)
# Module Name Slice Register LUT+LUTRAM RAM Description
4K2K Up-Converter Reference Design
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The utilization/STA value varies depending on the tool version and tool options.
Note: The data in Table 5 indicates representative values and not guaranteed values.
Block Specifications
Bus Type
MicroBlaze Processor
MicroBlaze Debug Module (MDM)
50 xsvi_mux_tx_0 40 58 75 0 xsvi MUX on transmit side
51 axi_osd_0 1318 2619 2075+189 2 Video on screen display 0
52 axi_osd_1 1345 2619 2125+189 2 Video on screen display 1
53 axi_osd_2 1333 2619 107+189 2 Video on screen display 2
54 axi_osd_3 1343 2619 2135+189 2 Video on screen display 3
55 axi_vdma_osd_0 1423 3392 2269+144 7 OSD AXI Video Direct Memory Access 0
56 axi_vdma_osd_1 1416 3392 2245+145 7 OSD AXI Video Direct Memory Access 1
57 axi_vdma_osd_2 1468 3392 1983+145 7 OSD AXI Video Direct Memory Access 2
58 axi_vdma_osd_3 1475 3392 2160+145 7 OSD AXI Video Direct Memory Access 3
59 genlock_ctrl_0 55 145 92+4 0 Scaler gunlock id/fsync generate
60 hdmi_tx_0 28 79 52 0 HDMI transmit controller 0
61 hdmi_tx_1 28 79 60 0 HDMI transmit controller 1
62 hdmi_tx_2 28 79 60 0 HDMI transmit controller 2
63 hdmi_tx_3 25 79 59 0 HDMI transmit controller 3
64 axi_7series_ddrx_0 5780 8104 11211+2914 0 DDR3 SDRAM Controller
65 idelay_ctrl_0 5 16 0 0 IDELAYCTRL module
66 axi4s_chroma_0 55 118 133+36 1 axi4s interface chroma 0
67 axi4s_chroma_1 60 118 132+36 1 axi4s interface chroma 1
68 axi4s_chroma_2 60 118 132+36 1 axi4s interface chroma 2
69 axi4s_chroma_3 61 118 132+36 1 axi4s interface chroma 3
Table 5: Description of Each Block and Resource Utilization (Cont’d)
# Module Name Slice Register LUT+LUTRAM RAM Description
A32 32 bit address
D32 32 bit data
Operational frequency 50 MHz
Bus interface AXI4-Lite (50 MHz, A32, D32)
Bus interface AXI4 (160 MHz, A32, D32)
Operational frequency 50 MHz
Bus interface AXI4-Lite (50 MHz, A32, D32)
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Interrupt Controller (INTC)
UART Lite
Scaler
OSD
Operational frequency 50 MHz
Bus interface AXI4-Lite (50 MHz, A32, D32)
Up to 32 interrupts
Operational frequency 50 MHz
Bus interface AXI4-Lite (50 MHz, A32, D32)
UART parameters
Bit/second 9600
Data bit 8
Parity None
Start bit 1
Flow control None
Bus interface AXI4-Lite (50 MHz, A32, D32)
Bus interface AXI Stream Slave (148.5 MHz, D32)
Bus interface AXI Stream Master (148.5 MHz, D32)
Scaler parameters
Maximum input horizontal size 1920
Maximum input vertical size 1080
Maximum output horizontal size 3840
Maximum output vertical size 2160
Number of horizontal taps 11
Number of vertical taps 11
Maximum phase 64
Maximum coefficient sets 3
Bus interface AXI4-Lite (50 MHz, A32, D32)
Bus interface AXI Stream Slave (148.5 MHz, D32)
Bus interface XSVI input (148.5 MHz, no data)
Bus interface XSVI output (148.5 MHz, D30)
OSD parameters
Screen width 1920
Number of layers 2
layer1 imem size 96
layer1 text number strings 16
layer1 text maximum string length 64
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XAPP596 (v1.0.2) June 28, 2013 www.xilinx.com 17
vdma_deint
vdma_scaler
Bus interface AXI4-Lite (50 MHz, A32, D32)
Bus interface AXI4 S2MM (160 MHz, A32, D128)
Bus interface AXI Stream S2MM (160 MHz, A32, D32)
VDMA parameters
Use FSYNC 1
Flush on fsync 1
Include SG 0
Number of frames stored 12
Include S2MM 1
Include S2MM_SF 1
Include MM2S 0
S2MM maximum burst length 128
S2MM line buffer depth 4096
S2MM line buffer threshold 4
Bus interface AXI4-Lite (50 MHz, A32, D32)
Bus interface AXI4 S2MM (160 MHz, A32, D128)
Bus interface AXI4 MM2S (160 MHz, A32, D128)
Bus interface AXI Stream S2MM (148.5 MHz, D32)
Bus interface AXI Stream MM2S (148.5 MHz, D32)
Bus interface/VDMA parameters
Use FSYNC 1
Flush on fsync 1
Include SG 0
Number of frames stored 3
Include S2MM 1
Include S2MM_SF 1
S2MM genlock mode 1
Include MM2S 1
Include MM2S_SF 1
MM2S genlock mode 1
S2MM maximum burst length 128
S2MM line buffer depth 4096
S2MM line buffer thresh 4032
MM2S genlock mode 1
MM2S maximum burst length 128
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XAPP596 (v1.0.2) June 28, 2013 www.xilinx.com 18
vdma_osd
DDR3-SDRAM Controller
MM2S line buffer depth 4096
MM2S line buffer thresh 3840
Bus interface: AXI4-Lite (50 MHz, A32, D32)
Bus interface AXI4 MM2S (160 MHz, A32, D128)
Bus interface AXI Stream MM2S (148.5 MHz, D32)
VDMA parameters:
Use FSYNC 1
Flush on fsync 1
Include SG 0
Number of frames stored 12
Include S2MM 0
Include MM2S 1
Include MM2S_SF 1
MM2S maximum burst length 128
MM2S line buffer depth 4096
Operational frequency 800 MHz (DDR3-1600)
Bus interface AXI4 (200 MHz, A32, D512)
Structure
# of channels
# of banks 8
# of ranks 1
TCK 1250
TFAW 25000
TRAS 34000
TRCD 13910
TRFC 160000
TRP 13910
TRRD 5000
ECC None
Memory size 1 GB
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XAPP596 (v1.0.2) June 28, 2013 www.xilinx.com 19
Address Map
Figure 11 shows the map of the entire system.
X-Ref Target - Figure 11
Figure 11: Entire Address Map
MicroBlazeBootRom Space
128KB
MicroBlaze Address Map (32 bit)
H’7C24_0000
H’BFFF_FFFF
H’0000_0000
H’0003_FFFF
ReservedH’0004_0000
H’6FFF_FFFF
debug_module_0Address Space
64KB
axi_intc_0Address Space
64KB
axi_uartlite_0Address Space
64KB
H’7000_0000
H’7000_FFFFH’7100_0000
H’7100_FFFFH’7200_0000
H’7200_FFFF
hdmi_tx_0Address Space
64KB
xsvi_mux_rx_0Address Space
64KB
xsvi_mux_tx_0Address Space
64KB
H’7410_0000
H’7410_FFFF
H’7420_0000
H’7420_FFFFH’7430_0000
H’7430_FFFF
axi_vtc_0Address Space
axi_vdma_deint_0Address Space
64KB
axi_vdma_osd_0Address Space
64KB
axi_scaler_0Address Space
64KB
XAPP596_11_012313
64KB
64KBaxi_osd_0Address Space
Reserved
H’7800_0000
H’7800_FFFF
H’7820_0000
H’7820_FFFF
H’7C00_0000
H’7C00_FFFF
H’7C10_0000
H’7C10_FFFF
H’7C30_0000
H’7C30_FFFF
hdmi_rx_0Address Space
hdmi_rx_1Address Space
hdmi_rx_2Address Space
hdmi_rx_3Address Space
hdmi_tx_1Address Space
64KBH’7411_0000
H’7411_FFFF
hdmi_tx_2Address Space
64KBH’7412_0000
H’7412_FFFF
hdmi_tx_3Address Space
64KBH’7413_0000
H’7413_FFFF
axi_vdma_deint_1Address Space
64KBH’7801_0000
H’7801_FFFF
axi_vdma_deint_2Address Space
64KBH’7802_0000
H’7802_FFFF
axi_vdma_deint_3Address Space
64KBH’7803_0000
H’7803_FFFF
axi_vdma_scaler_0Address Space
64KBH’7810_0000
H’7810_FFFF
axi_vdma_scaler_1Address Space
64KBH’7811_0000
H’7811_FFFF
axi_vdma_scaler_2Address Space
64KBH’7812_0000
H’7812_FFFF
axi_vdma_scaler_3Address Space
64KBH’7813_0000
H’7813_FFFF
axi_vdma_osd_1Address Space
64KBH’7821_0000
H’7821_FFFF
axi_vdma_osd_2Address Space
64KBH’7822_0000
H’7822_FFFF
axi_vdma_osd_3Address Space
64KBH’7823_0000
H’7823_FFFF
axi_spi_0Address Space
64KBH’7830_0000
H’7830_FFFF
axi_scaler_1Address Space
axi_scaler_2Address Space
axi_scaler_3Address Space
axi_osd_1Address Space
axi_osd_2Address Space
axi_osd_3Address Space
H’7400_0000
H’7400_FFFFH’7401_0000
H’7401_FFFFH’7402_0000
H’7402_FFFFH’7403_0000
H’7403_FFFF
H’7C01_0000
H’7C01_FFFFH’7C02_0000
H’7C02_FFFFH’7C03_0000
H’7C03_FFFF
H’7C11_0000
H’7C11_FFFFH’7C12_0000
H’7C12_FFFFH’7C13_0000
H’7C13_FFFF
H’7C31_0000
H’7C31_FFFFH’7C32_0000
H’7C32_FFFFH’7C33_0000
H’7C33_FFFF
1GBH’C000_0000
H’FFFF_FFFF
DDR3 MemoryAddress Space
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
ReservedH’7431_0000
H’77FF_FFFFReserved
H’7832_0000
H’7BFF_FFFF
H’7300_0000
H’7300_FFFF64KB
axi_gpio_0Address Space
64KBH’7831_0000
H’7831_FFFF
Reserved
Reserved
Reserved
Reserved
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XAPP596 (v1.0.2) June 28, 2013 www.xilinx.com 20
Figure 12 shows the DDR address map.
External Pin List
Table 6 lists the FPGA external pins.
X-Ref Target - Figure 12
Figure 12: DDR Address Map
xsvi_to_axi4s Output Buff 0
xsvi_to_axi4s Output Buff 1
xsvi_to_axi4s Output Buff 2
xsvi_to_axi4s Output Buff 3
xsvi_to_axi4s Output Buff 4
xsvi_to_axi4s Output Buff 5
xsvi_to_axi4s Output Buff 6
xsvi_to_axi4s Output Buff 7
xsvi_to_axi4s Output Buff 8
xsvi_to_axi4s Output Buff 9
xsvi_to_axi4s Output Buff 10
xsvi_to_axi4s Output Buff 11
Scaler 0 Output Buff 0
Scaler 0 Output Buff 1
Scaler 0 Output Buff 2
Scaler 1 Output Buff 0
Scaler 1 Output Buff 1
Scaler 1 Output Buff 2
Scaler 2 Output Buff 0
Scaler 2 Output Buff 1
Scaler 2 Output Buff 2
Scaler 3 Output Buff 0
Scaler 3 Output Buff 1
Scaler 3 Output Buff 2
H'C0000000
H'C07FFFFF
H'C0800000
H'C0FFFFFF
H'C1000000
H'C17FFFFF
H'C1800000
H'C1FFFFFF
H'C2000000
H'C27FFFFF
H'C2800000
H'C2FFFFFF
H'C3000000
H'C37FFFFF
H'C3800000
H'C3FFFFFF
H'C4000000
H'C47FFFFF
H'C4800000
H'C4FFFFFF
H'C5000000
H'C57FFFFF
H'C5800000
H'C5FFFFFF
8MB
8MB
8MB
8MB
8MB
8MB
8MB
8MB
8MB
8MB
8MB
8MB
ReservedH'C6000000
H'CFFFFFFF160MB
H'D0000000
H'D1FFFFFF
H'D2000000
H'D3FFFFFF
H'D4000000
H'D5FFFFFF
H'D6000000
H'D7FFFFFF
H'D8000000
H'D9FFFFFF
H'DA000000
H'DBFFFFFF
H'DC000000
H'DDFFFFFF
H'DE000000
H'DFFFFFFF
H'E0000000
H'E1FFFFFF
H'E2000000
H'E3FFFFFF
H'E4000000
H'E5FFFFFF
H'E6000000
H'E7FFFFFF
32MB
32MB
384MB
XAPP596_12_012313
32MB
32MB
32MB
32MB
32MB
32MB
32MB
32MB
32MB
32MB
ReservedH'E8000000
H'FFFFFFFF
Table 6: External Pins
Pin Name I/O # Valid Logic Default I/O Potential Function Remarks
Global Pin
CLK_200MHZ_OSC_P I 1 – DIFF_SSTL15 Input differential clock 200 MHz positive
CLK_200MHZ_OSC_N I 1 – DIFF_SSTL15 Input differential clock 200 MHz negative
CLK_74MHZ_OSC_P I 1 – LVDS_25 Input differential clock 74 MHz positive
CLK_74MHZ_OSC_N I 1 – LVDS_25 Input differential clock 74 MHz negative
FMC_74M_OUT_P O 1 – LVDS_25 Output differential clock 74MHz positive
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XAPP596 (v1.0.2) June 28, 2013 www.xilinx.com 21
FMC_74M_OUT_N O 1 – LVDS_25 Output differential clock 74 MHz negative
HDMI Receive Pin
HDMIR0_CLK I 1 – LVCMOS25 HDMI receive channel 0 clock
HDMIR0_VS I 1 – – LVCMOS25 HDMI receive channel 0 vsync
HDMIR0_HS I 1 – – LVCMOS25 HDMI receive channel 0 hsync
HDMIR0_DE I 1 High – LVCMOS25 HDMI receive channel 0 data enable
HDMIR0_D[29:0] I 30 – – LVCMOS25 HDMI receive channel 0 data
HDMIR0_XRST I 1 Low 0 LVCMOS25 HDMI receive channel 0 reset
HDMIR1_CLK I 1 – LVCMOS25 HDMI receive channel 1 clock
HDMIR1_VS I 1 – – LVCMOS25 HDMI receive channel 1 vsync
HDMIR1_HS I 1 – – LVCMOS25 HDMI receive channel 1 hsync
HDMIR1_DE I 1 High – LVCMOS25 HDMI receive channel 1 data enable
HDMIR1_D[29:0] I 30 – – LVCMOS25 HDMI receive channel 1 data
HDMIR1_XRST I 1 Low 0 LVCMOS25 HDMI receive channel 1 reset
HDMIR2_CLK I 1 – LVCMOS25 HDMI receive channel 2clock
HDMIR2_VS I 1 – – LVCMOS25 HDMI receive channel 2 vsync
HDMIR2_HS I 1 – – LVCMOS25 HDMI receive channel 2 hsync
HDMIR2_DE I 1 High – LVCMOS25 HDMI receive channel 2 data enable
HDMIR2_D[29:0] I 30 – – LVCMOS25 HDMI receive channel 2 data
HDMIR2_XRST I 1 Low 0 LVCMOS25 HDMI receive channel 2 reset
HDMIR3_CLK I 1 – LVCMOS25 HDMI receive channel 3 clock
HDMIR3_VS I 1 – – LVCMOS25 HDMI receive channel 3 vsync
HDMIR3_HS I 1 – – LVCMOS25 HDMI receive channel 3 hsync
HDMIR3_DE I 1 High – LVCMOS25 HDMI receive channel 3 data enable
HDMIR3_D[29:0] I 30 – – LVCMOS25 HDMI receive channel 3data
HDMIR3_XRST I 1 Low 0 LVCMOS25 HDMI receive channel 3 reset
HDMI Transmit Pin
HDMIT0_CLK O 1 – LVCMOS25 HDMI transmit channel 0 clock
HDMIT0_VS O 1 – 0 LVCMOS25 HDMI transmit channel 0 vsync
HDMIT0_HS O 1 – 0 LVCMOS25 HDMI transmit channel 0 hsync
HDMIT0_DE O 1 High 0 LVCMOS25 HDMI transmit channel 0 data enable
HDMIT0_D[29:0] O 30 – All 0 LVCMOS25 HDMI transmit channel 0 data
HDMIT0_XRST O 1 Low 0 LVCMOS25 HDMI transmit channel 0 reset
Table 6: External Pins (Cont’d)
Pin Name I/O # Valid Logic Default I/O Potential Function Remarks
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XAPP596 (v1.0.2) June 28, 2013 www.xilinx.com 22
HDMIT1_CLK O 1 – LVCMOS25 HDMI transmit channel 1 clock
HDMIT1_VS O 1 – 0 LVCMOS25 HDMI transmit channel 1 vsync
HDMIT1_HS O 1 – 0 LVCMOS25 HDMI transmit channel 1 hsync
HDMIT1_DE O 1 High 0 LVCMOS25 HDMI transmit channel 1 data enable
HDMIT1_D[29:0] O 30 – All 0 LVCMOS25 HDMI transmit channel 1 data
HDMIT1_XRST O 1 Low 0 LVCMOS25 HDMI transmit channel 1 reset
HDMIT2_CLK O 1 LVCMOS25 HDMI transmit channel 2 clock
HDMIT2_VS O 1 – 0 LVCMOS25 HDMI transmit channel 2 vsync
HDMIT2_HS O 1 – 0 LVCMOS25 HDMI transmit channel 2 hsync
HDMIT2_DE O 1 High 0 LVCMOS25 HDMI transmit channel 2 data enable
HDMIT2_D[29:0] O 30 – All 0 LVCMOS25 HDMI transmit channel 2 data
HDMIT2_XRST O 1 Low 0 LVCMOS25 HDMI transmit channel 2 reset
HDMIT3_CLK O 1 – LVCMOS25 HDMI transmit channel 3 clock
HDMIT3_VS O 1 – 0 LVCMOS25 HDMI transmit channel 3 vsync
HDMIT3_HS O 1 – 0 LVCMOS25 HDMI transmit channel 3 hsync
HDMIT3_DE O 1 High 0 LVCMOS25 HDMI transmit channel transmit channel 3 data enable
HDMIT3_D[29:0] O 30 – All 0 LVCMOS25 HDMI transmit channel 3 data
HDMIT3_XRST O 1 Low 0 LVCMOS25 HDMI transmit channel 3 reset
DDR3 Pin
DDR3_CK_P[0:0] O 1 0 DIFF_SSTL15 DDR3 clock
DDR3_CK_N[0:0] O 1 1 DIFF_SSTL15 DDR3 reverse clock
DDR3_CKE[0:0] O 1 High 0 SSTL15 DDR3 clock enable
DDR3_RAS_N O 1 Low 1 SSTL15 DDR3 low address select
DDR3_CAS_N O 1 Low 1 SSTL15 DDR3 column address select
DDR3_WE_N O 1 Low 1 SSTL15 DDR3 write enable
DDR3_CS_N[0:0] O 1 Low 1 SSTL15 DDR3 chip select
DDR3_ADDR[13:0] O 14 – All 0 SSTL15 DDR3 address
DDR3_BA[2:0] O 3 – All 0 SSTL15 DDR3 bank address
DDR3_ODT[0:0] O 1 High 0 SSTL15 DDR3On Die Termination
DDR3_DQ[63:0] I/O 64 – All Z SSTL15_T_DCI DDR3 data
DDR3_DM[7:0] O 8 High All 0 SSTL15 DDR3 data mask
DDR3_DQS_ P[7:0] I/O 8 – All Z DIFF_SSTL15_T_DCI DDR3 data strobe
DDR3_DQS_ N[7:0] I/O 8 – All Z DIFF_SSTL15_T_DCI DDR3 reverse data strobe
Table 6: External Pins (Cont’d)
Pin Name I/O # Valid Logic Default I/O Potential Function Remarks
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XAPP596 (v1.0.2) June 28, 2013 www.xilinx.com 23
Switch/LED Function
Table 7 lists the pushbutton switch functions. The pushbutton PSW0 is item (12) in Figure 1.
Table 8 lists DIP switch SW5 functions. In Figure 1, DIP switch SW5 is item (13).
DDR3_RESET_N O 1 Low 1 LVCMOS15 DDR3 reset
DDR3_PARITY O 1 0 LVCMOS15 DDR3SCL
UART Pin
UART_TXD O 1 – – LVCMOS15 Uart-Lite TX Data
UART_RXD I 1 – – LVCMOS15 Uart-Lite RX Data
SPI Pin
SPI_FLASH_SS O 1 Low 1 LVCMOS25 SPI Flash Slave Select
SPI_FLASH_MISO I 1 – – LVCMOS25 SPI Flash Master in Slave out
SPI_FLASH_MOSI O 1 – – LVCMOS25 SPI Flash Master out Slave in
Debug Pin
RESET_N I 1 Low – LVCMOS15 Async reset (pushbutton switch)
DIPSW[7:0] I 8 – – LVCMOS15 Dip-Switch
LED[5:0] O 6 – All 0 LVCMOS15 LED
Notes: 1. For individual pin assignments, refer to the user constraint file (UCF) provided separately.
Table 6: External Pins (Cont’d)
Pin Name I/O # Valid Logic Default I/O Potential Function Remarks
Table 7: Pushbutton Switch Function
PSW[3:0] Function
PSW3 Reserved
PSW2 Reserved
PSW1 Reserved
PSW0 FPGA async reset
Table 8: DIP Switch Functions
DIPSW[7:0] Function
DIP Switch SW5 (Item 13 in Figure 1)
DIPSW7 GPIO Channel1 bit [7] input and connection
DIPSW6 GPIO Channel1 bit [6] input and connection
DIPSW5GPIO Channel1 bit [5] input and connectionUART control, OFF: Auto-demonstration sequence after initialization
DIPSW4 GPIO Channel1 bit [4] input and connectionON: In mosaic mode, TX0 output = TX1 output = TX2 output = TX3 output = RX0 inputOFF: In mosaic mode, TXn putput = RXn input
DIPSW3 GPIO Channel1 bit [3] input and connection
4K2K Up-Converter Reference Design
XAPP596 (v1.0.2) June 28, 2013 www.xilinx.com 24
Table 9 lists the LED function.
Operational Mode
Single Input Mosaic Mode
In mosaic mode, one channel input is supported. Live output images or memory-stored images (still or motion) are mapped on the 4K2K screen with some characters added by OSD.
Figure 13 shows the data flow in mosaic mode. The Input full HD image signal comes from the RX0 input of the HDMI card (on LPC2 FMC connector) and is fed to the xsvi_axi4s module. This image signal is fed into DDR3-SDRAM through the AXI4_InterConnect as four source images to make up the mosaic image (datapath (2)).
Four output images from memory are fed to axi_osd module (datapath (5)). These four images are T/L (top left), T/R (top right), B/L (bottom left), and B/R (bottom right), which corresponds to the quadrant position of the 4K2K display screen. In the demonstration of this reference design, live picture, still picture, and the combination from the memory can be shown.
In the axi_osd module, some characters and graphics such as the Xilinx logo from xsvi_mux_tx are overlaid. Output images from the axi_osd module are transferred to HDMI Tx card and output from Tx0, Tx1 port of 2 HDMI FMC card on HPC1, and HPC2 FMC connectors.
DIPSW2 GPIO Channel1 bit [2] input and connection
DIPSW1 GPIO Channel1 bit [1] input and connection
DIPSW0 GPIO Channel1 bit [0] input and connection
Table 9: LED Function
LED[5:0] Function
LED5 GPIO Channel2 bit [19] output and connection
LED4 GPIO Channel2 bit [18] output and connection
LED3 GPIO Channel2 bit [17] output and connection
LED2 GPIO Channel2 bit [16] output and connection
LED1 GPIO Channel2 bit [15] output and connection
LED0 ON: DDR3-SDRAM initialization OK
Table 8: DIP Switch Functions (Cont’d)
DIPSW[7:0] Function
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XAPP596 (v1.0.2) June 28, 2013 www.xilinx.com 25
Figure 14 shows mosaic mode timing. HDMI RX0 Input (60 fps) is written into a DDR3 frame buffer. Frame buffering is used to show a still image in mosaic mode and to maintain the modularity of the system. Readout from the frame buffer starts after one frame period. As a result, the output of the mosaic image is delayed one frame period (approximately 16 ms) from the input image.
Up-Converter Mode
In up-converter mode, 1ch 1080p input is supported. The pass-through output (1920 x 1080) goes to the scaler and the scalar IP upscales the image to 4K2K (3840 x 2160), and characters are added and output by the OSD.
Figure 15 shows the data flow in up-converter mode. The input full HD image signal coming from RX0 input of HDMI card (on LPC2 FMC connector) is fed to the xsvi_axi4s module. This image signal is fed into DDR3-SDRAM through AXI4_InterConnect (datapath (2)).
Four sequential frames are read out in parallel in 15 fps (4X slower than the input frame rate) and fed to axi_scaler module (datapath (3)). In the axi_scaler module, the image signal processing to increase the pixel density to 4K2K is executed. Outputs from axi_scaler module
X-Ref Target - Figure 13
Figure 13: Data Flow in Mosaic Mode
xsvi_to_axi4s
axi_7series_ddrx
DDR3-SDRAM 1600M (x 64 bit = 12,800 MB/s)
axi_scaler
axi_osd
MicroBlaze Processoraxi_intc
XAPP596_13_013113
S_AXI
axi_vtc
RX
RX
x4
64 bit
AXI4_InterConnect
xsvi_mux_tx
M_AXI
axi_vdma_deint
M_A
XIS
axi_vdma_scaler axi_vdma_osd
AXI4LITE_InterConnect
hdmi_rx
TB
-FM
CH
-HD
MI2-R
XH
DM
I1.4
xsvi_mux_rx
hdmi_tx
TB
-FM
CH
-HD
MI2-T
XH
DM
I1.4axi_uartlite
TX
TX
x4
x4 x4 x4
x4
x4 x4 x4
x4
2 3 4 51
X-Ref Target - Figure 14
Figure 14: HDMI RX0 Input
HDMI TX/OSD0 Output Frame1Frame0 Frame2 Frame4Frame3 Frame6Frame5 Frame7 Frame8 Frame10Frame9 Frame11
XAPP596_14_012313
HDMI TX/OSD1 Output Frame1Frame0 Frame2 Frame4Frame3 Frame6Frame5 Frame7 Frame8 Frame10Frame9 Frame11
HDMI TX/OSD2 Output Frame1Frame0 Frame2 Frame4Frame3 Frame6Frame5 Frame7 Frame8 Frame10Frame9 Frame11
HDMI TX/OSD3 Output Frame1Frame0 Frame2 Frame4Frame3 Frame6Frame5 Frame7 Frame8 Frame10Frame9 Frame11
1 Frame Delay1 Frame Delay1 Frame Delay1 Frame Delay
HDMI RX0 Input Frame1Frame0 Frame2 Frame4Frame3 Frame6Frame5 Frame7 Frame8 Frame10Frame9 Frame11
4K2K Up-Converter Reference Design
XAPP596 (v1.0.2) June 28, 2013 www.xilinx.com 26
are written back to the frame buffer (datapath (4)). These images are read out as four 4K2K image stream quadrants in 60 fps and fed to the axi_osd module (datapath (5)).
In the axi_osd module, some characters and graphics such as the Xilinx logo from xsvi_mux_tx are overlaid. Output images from the axi_osd module are transferred to HDMI Tx card and output from Tx0, Tx1 port of 2 HDMI FMC card on HPC1, and HPC2 FMC connectors.
Figure 16 shows the up-converter mode timing. The HDMI RX0 Input is written to a frame buffer through the AXI4_InterConnect (datapath (2)). Four sequential frames are read out in parallel and fed to axi_scaler module in 15 fps. Outputs from axi_scaler module come out right after the Frame3 input to the frame buffer (datapath (4)). As a result, a 4K2K image in 60 fps comes out approximately eight frames after the input.
X-Ref Target - Figure 15
Figure 15: Data Flow in Up-Converter Mode
xsvi_to_axi4s
axi_7series_ddrx
DDR3-SDRAM 1600M (x64 bit = 12,800 MB/s)
axi_scaler
axi_osd
MicroBlazeaxi_intc
XAPP596_15_013113
S_AXI
axi_vtc
RX
RX
64 bit
AXI4_InterConnect
xsvi_mux_tx
M_AXI
axi_vdma_deint
M_A
XIS
axi_vdma_scaler axi_vdma_osd
AXI4LITE_InterConnect
hdmi_rx
TB
-FM
CH
-HD
MI2-R
XH
DM
I1.4
xsvi_mux_rx
hdmi_tx
TB
-FM
CH
-HD
MI2-T
XH
DM
I1.4
axi_uartlite
TX
TX
x4 x4
x4
x4 x4 x4
x4
2 3 4 51
X-Ref Target - Figure 16
Figure 16: Up-Converter Mode Timing
8 Frame Delay
HDMI RX0 Input 2 Frame1Frame0 Frame2 Frame4Frame3 Frame6Frame5 Frame7
Scaler0 Output 4Frame1
Frame0
Frame2
Frame3
Scaler1 Output 4Scaler2 Output 4Scaler3 Output 4
Frame4
Frame6
Frame5
Frame7
HDMI TX/OSD0 Output Quadrant1 5Frame1Frame0 Frame2 Frame3HDMI TX/OSD1 Output Quadrant2 5
HDMI TX/OSD2 Output Quadrant3 5HDMI TX/OSD3 Output Quadrant4 5
Frame1Frame0 Frame2 Frame3
Frame1Frame0 Frame2 Frame3
Frame1Frame0 Frame2 Frame3
Frame4 Frame6Frame5 Frame7
Frame4 Frame6Frame5 Frame7
Frame4 Frame6Frame5 Frame7
Frame4 Frame6Frame5 Frame7
Frame8 Frame10Frame9 Frame11 Frame12 Frame14Frame13 Frame15
Frame8
Frame10
Frame9
Frame11
Input Synchronize
Output Free-Run Synchronize
4 Frame Delay3 Frame Delay2 Frame Delay1 Frame Delay
1 Frame 15 fps Delay1 Frame 15 fps Delay1 Frame 15 fps Delay1 Frame 15 fps Delay
XAPP596_16_013113
4 Channels [Scaler] are working independently to write frames to the external memory.4 Channels [HDMI TX/OSD] are working independently to read frames from the external memory.
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XAPP596 (v1.0.2) June 28, 2013 www.xilinx.com 27
Soft Control
The Test Menu (Figure 17) provides the following three additional commands.:
• y — Mosaic mode demonstration
• z — Up-converter mode demonstration
• a — Mosaic/up-converter combined demonstration
Figure 17 shows the UART display screen.
X-Ref Target - Figure 17
Figure 17: UART Display Screen
XAPP596_17_082912
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XAPP596 (v1.0.2) June 28, 2013 www.xilinx.com 28
Mosaic Mode
In mosaic mode, four OSDs independently output the input images from the xsvi_to_axi4s.
Figure 18 shows the relationship between the output image from the xsvi_to_axi4s and the images from each OSD.
The mosaic mode has two types: Live mode and still mode. The live mode provides real-time output of the input images and the still mode provides still images, without updating them.
Figure 19 shows the control flow.
X-Ref Target - Figure 18
Figure 18: Mosaic Mode
xsvi_to_axi4s(1920x1080)
xsvi_to_axi4s(Live or Still)(1920x1080)
xsvi_to_axi4s(Live or Still)(1920x1080)
xsvi_to_axi4s(Live or Still)(1920x1080)
OSD1(1920x1080)
OSD2(1920x1080)
OSD3(1920x1080)
OSD4(1920x1080)
xsvi_to_axi4s Output
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Up-Converter Mode
In up-converter mode, input images (1920*1080p) are scaled 1/2 to 2.0 larger (960*540 to 3840*2160) by the scaler. The scaling factor can be varied frame by frame resulting in smooth zooming. The scaled picture is mapped on the frame with 3840 * 2160 resolution and 1/4 pictures (1920*1080) are output by each OSD.
Figure 20 shows the relationship between the scaler output and the OSD output.
X-Ref Target - Figure 19
Figure 19: Control Flow in Mosaic Mode
X-Ref Target - Figure 20
Figure 20: Up-Converter Mode
Single Input Mosaic Mode (Live)
Single Input Mosaic (Still)
Single Input Mosaic (Live)
Keyboard Input
q?
Single Input Mosaic Input
No
Yes
ExitXAPP596_19_012313
(1920*1080) (1920*1080)
(1920*1080) (1920*1080)
OSD1(1920*1080)
OSD2(1920*1080)
OSD3(1920*1080)
OSD4(1920*1080)
Scaler Output
3840
2160
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Up-converter mode provides real-time effectiveness of zoom by changing the scaler and OSD parameters. The parameters change at the occurrence of an OSD VDMA interrupt signal. The software calculates parameters by the OSD VDMA interrupt handling function, and sets the parameters to scaler, VDMA, and OSD.
Figure 21 shows the control flow in up-converter mode.
X-Ref Target - Figure 21
Figure 21: Control Flow in Up-Converter Mode
Biggest Size
Up ScalerStep=0?
Down Scaler
No
Yes
Step=1?
Step=2?
No
No
Smallest Size
Yes
Yes
Caculate Parametersand Set
Caculate Parametersand Set
Parameters are Up toLargest Size (3840x2160),
Goto Step 1
Count InterruptIf the Counter has Overflowed
Goto Step 2
Parameters are Down to Smallest Size (960x540),
Goto Step 3
Count Interrupt
XAPP596_21_082712
If the Counter has OverflowedGoto Step 0
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Combined Demonstration
The general mode provides a combined demonstration by continuously switching the mosaic and up-converter modes. Figure 22 shows the control flow in general mode.
X-Ref Target - Figure 22
Figure 22: Control Flow in General Mode
Display Xilinx Logo
Single Input Mosaic Mode (Live)
Display Xilinx Logo
Up-Converter Mode
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Single Input Mosaic Mode (Still)
Single Input Mosaic Mode (Live)
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The ISE, EDK, and SDK Tool Environment
Directory Structure
Figure 23 shows the directory structure of the tool environment.
X-Ref Target - Figure 23
Figure 23: Directory Structure
MicroBlaze Processor PCOREs Applied in RTVE
RTVE EDK Project File
MicroBlaze Processor Device Drivers
ISE Tools Project
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ISE Project Environment
Creating Bit Files
To create bit files:
1. Click on the Tools menu and select Launch SmartXplorer as shown in Figure 24.
Configuration settings for SmartXplorer are shown in Figure 25.
2. Set the SmartXplorer configuration as shown in Figure 25 and click Ok.
3. Select the check box of high-lighted best strategy next to the best Strategy.
X-Ref Target - Figure 24
Figure 24: Launching SmartXplorer
X-Ref Target - Figure 25
Figure 25: SmartXplorer Configuration Settings
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4. Click the Copy Results button at the bottom of the window to copy the results of the best strategy to the current project, as shown in Figure 26.
5. In the Processes panel on the left (see Figure 27), click on Generate Programming File.
X-Ref Target - Figure 26
Figure 26: SmartXplorer Window
X-Ref Target - Figure 27
Figure 27: ISE Project Navigator Window
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Starting EDK Environment
Double click system_i – system (..\..\EDK\system.xmp) in the Hierarchy window to start the EDK environment as shown in Figure 28.
EDK Project Environment
Figure 29 shows the EDK project environment. Pcore parameters that are used for the design can be changed using the Bus Interfaces window.
Connections between modules can be changed using the Ports window.
The Address Map can be changed using the Addresses window.
X-Ref Target - Figure 28
Figure 28: ISE Window (Starting EDK Environment)
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SDK Project Environment
The SDK project (Figure 30, page 37) consists of the following three components:
RTVE_HW Hard Platform Project. The file system.xml is an EDK exported hardware information file.
RTVE_BSP BSP Project. This is a driver automatically created by the SDK Environment using system.xml.
RTVE_APP User Application.
X-Ref Target - Figure 29
Figure 29: EDK Window
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Reference Design
The reference design files for this application note can be downloaded from:
www.xilinx.com/member/display_trd/index.htm
Reference Design Checklist
The reference design checklist is shown in Table 10.
X-Ref Target - Figure 30
Figure 30: SDK Window
XAPP596_30_080912
Table 10: Reference Design Checklist
Parameter Description
General
Developer name Xilinx
Target devices (stepping level, ES, production, speed grades) Kintex-7 XC7K325T-2FFG900
Source code provided Yes
Source code format VHDL, Verilog, and C
Design uses code/IP from existing Xilinx application note/reference designs, the CORE Generator™ tool, or third party
Xilinx EDK software and CORE Generator tool
Simulation
Functional simulation performed N/A
Timing simulation performed N/A
Conclusion
XAPP596 (v1.0.2) June 28, 2013 www.xilinx.com 38
Resource Utilization
The reference design utilization summary is listed in Table 11.
Conclusion This HDTV to 4K2K up-converter reference design is part of the Kintex-7 FPGA-based Display Targeted Design Platform. This design enables easily accessible HDTV content to be shown on a 4K2K monitor or 4K2K flat panel, providing design engineers with the base for their product designs. With this base addressing the mandatory up-conversion, engineers can focus their efforts on differentiating their 4K2K digital TVs, displays, and projectors.
Revision History
The following table shows the revision history for this document.
Test bench used for functional and timing simulations N/A
Test bench format N/A
Simulator software/ version used N/A
SPICE/IBIS simulations N/A
Implementation
Synthesis software tools/version used ISE® Design Suite 14.3
Implementation software tools/versions used ISE Design Suite 14.3
Static timing analysis performed Yes
Hardware Verification
Hardware verified Yes
Hardware platform used for verification ACDC 1.0 Base Board
Table 11: Resource Utilization
Parameters Specification/ Details
Maximum frequency (by speed grade) -1 200 MHz
Device utilization without test bench (mandatory)
Slices 50525
GCLK buffers 11
Block RAM 361
GTX transceivers 0
HDL language support Verilog and VHDL
Table 10: Reference Design Checklist (Cont’d)
Parameter Description
Date Version Description of Revisions
03/01/2013 1.0 Initial Xilinx release.
04/02/2013 1.0.1 Updated the link in Reference Design, page 37.
06/28/2013 1.0.2 Removed two references to XAPP597.
Notice of Disclaimer
XAPP596 (v1.0.2) June 28, 2013 www.xilinx.com 39
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