X-by-Wire Systems
Transcript of X-by-Wire Systems
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Necessity for Active Safety
Active Safety by Electric
/Electronic Technology
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X-by-Wire Operated with a Side Stick
Power-train Platform with 11” Thickness. Layout-Free Cabin
GM <Hy-Wire> 2002 Fuel Cell Vehicle
Daimler Chrysler <R129> 1997
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Daimlar Chrysler/SL, E-class
Toyota Estima-Hybrid ariable Gear Ratio Honda/S8000
Variable Gear Ratio Toyota/Land Cruiser
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Low Emission, Human CenteredLow Emission, Human Centered
Architecture Architecture
Drivability Drivability
Free Layout Free Layout
For For
Environment Environment
Energy SavingEnergy Saving
Regenerative BrakeRegenerative Brake
DryDry
Safety Safety
With X-By-Wire, Cars becomeWith X-By-Wire, Cars become……
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Brake-By-Wire
Steer-By-Wire
Conventional X-By-Wire System
HydraulicSteering
Hydraulic Pipe
HydraulicBrake
Steering Wheel
Mechanically Connected among Actuators and Mechanics
Integrated Control ConnectingComponents
via High-Speed Bus
Brake Pedal
Controller
High-SpeedBus
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Inexpensive Dependability
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Low-Cost Dependable Technology
10 102 103 104 105 106
Aerospace Steel Railroad Automobile
(units/yr)
Production Scale of Controllers
Mass Production of LSI
Cost Reduction
Low-Cost Dependability with LSI Technology
Redundant CPUs in One Chip
Self-Checking / Failsafe Technology
Optimal Clock Diversity
and Autonomous Decentralized Concept
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Our Expertise in Dependability
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CPU
A
SC
CMP
CPU
B
FS-I/O
CLK
Self-Checking Comparator Self-checks its own operation
Compares output of two CPUs
Fail-Safe I/O Executes fail-safe mode
operation on CPU failure
Optimal Clock Diversity Operates CPUs out-of-phase
Improves noise immunity
Making Controllers Dependable : Dual CPUs
Applications
Digital ATC
Crossing Controller
Dual CPU Controller
Compares outputs of two CPUs.
Takes fail-safe mode operation, if there is a difference.
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Comparator
a0
b0
an
bn
c0
cn
Self-Checking Comparator
Comparison of two outputs
CPU A
CPU B
a0 a1 a2 an
b0 b1 b2 bn
Exclusive-OR
0 : Normal
1 : Error
Test Pattern Generator
Exclusive-OR
Error
Normal
Error
Test Pattern Generator
inputs cyclic error signals
intentionally
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Clock in A
Clock in B
Noise Sensitive Window
Distance Distance
Phase Difference
hold
set up
Effects of Time Diversity
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d
(a) Macro Effect
d
(b) Micro Effect
1.0 2.0 3.0 [clocks]
d
Corr
elat
ed E
rror
Rat
e
1.0 2.0 3.0[clocks]
(c) Overall Effect
*
Corr
elat
ed E
rror
Rat
eC
orr
elat
ed E
rror
Rat
e
Effects of Time Diversity
0
0.1
0.2
0.3
0.4
0.0 0.5 1.0 1.5 2.0
simultaneous error
coincident error
optimal points
Corr
elat
ed E
rror
Rat
e
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MP(A) MP(B)
RAM
RAM
CPU
Peripherals
RAM
RAM
CPU
PeripheralsS
elf-
Che
ckin
g C
ompa
rato
rMP(A) MP(B)
RAM
RAM
CPU
Peripherals
RAM
RAM
CPU
PeripheralsS
elf-
Che
ckin
g C
ompa
rato
r
ProcessHard MacrosRandom LogicChip SizeOperating FrequencyPower DissipationPackage
0.35 m 5 Metal CMOSPLL x 2, RAM(40KB)740k gates14.75 mm60 MHz
2.6W @ 60MHz479pin BGA
MP(A)
Self-Checking Comparator
External Bus
RAM CPU
Peripherals
MP(B)
RAM CPU
Peripherals
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Autonomous Decentralized Systems
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1
Hitachi’s R&D on Automotive Systems
Nuclear Reactor -Hydraulic Dynamics Sim.
Gas TurbineCombustion Analysis
Motors, Generators
Train Control
RISCProcessors
Power IC
Information
Service
Environment Low Emission
Safety
Drivability
Car Navigation
Target
Automotive Systems
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