WIZ812MJ Datasheetwiznethome.cafe24.com/wp-content/uploads/wiznethome... · 2015. 6. 18. · 3V3D P...
Transcript of WIZ812MJ Datasheetwiznethome.cafe24.com/wp-content/uploads/wiznethome... · 2015. 6. 18. · 3V3D P...
WIZ812MJ Datasheet (Ver. 1.2)
© 2013 WIZnet Co., Ltd. All Rights Reserved.
For more information, visit our website at www.wiznet.co.kr
WIZ812MJ Datasheet
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Document History Information
Revision Data Description
Ver. 1.0 September 17, 2008 Release with WIZ812MJ Launching
Ver. 1.1 January 28, 2009 Added temperature specification
Ver. 1.2 January 28, 2013 Hardware revision(Rev1.1) Changed operation temperature range, partlist and schematic
WIZ812MJ Datasheet
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WIZnet’s Online Technical Support
If you have something to ask about WIZnet Products, Write down your question
on Q&A Board in WIZnet website (www.wiznet.co.kr). WIZnet Engineer will give an
answer as soon as possible.
WIZ812MJ Datasheet
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Table of Contents
1. Introduction .............................................................................. 5
1.1. Features ............................................................................. 5
1.2. Block Diagram ...................................................................... 5
1.3. Difference between WIZ811MJ and WIZ812MJ .............................. 6
2. Pin Assignments & descriptions ................................................... 7
2.1. Pin Assignments ................................................................... 7
2.2. Power & Ground ................................................................... 8
2.3. MCU Interfaces ..................................................................... 8
2.4. Miscellaneous Signals ............................................................ 9
3. Timing Diagrams ..................................................................... 10
3.1. Reset Timing .................................................................... 10
3.2. Register/Memory READ Timing ............................................... 10
3.3. Register/Memory WRITE Timing .............................................. 11
3.4. SPI Timing......................................................................... 11
4. Dimensions ............................................................................. 12
5. Schematic .............................................................................. 13
6. Partlist ................................................................................... 14
WIZ812MJ Datasheet
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1. Introduction
WIZ812MJ is the network module that includes W5100 (TCP/IP hardwired chip, include PHY), MAG-JACK (RJ45 with X’FMR) with other glue logics. It can be used as a component and no effort is required to interface W5100 and Transformer. The WIZ812MJ is an ideal option for users who want to develop their Internet enabling systems rapidly. For the detailed information on implementation of Hardware TCP/IP, refer to the W5100 Datasheet. WIZ812MJ consists of W5100 and MAG-JACK.
TCP/IP, MAC protocol layer: W5100
Physical layer: Included in W5100
Connector: MAG-JACK(RJ45 with Transformer)
1.1. Features Supports 10/100 Base TX
Supports half/full duplex operation
Supports auto-negotiation and auto cross-over detection
IEEE 802.3/802.3u Compliance
Operates 3.3V with 5V I/O signal tolerance
Supports network status indicator LEDs
Includes Hardware Internet protocols: TCP, IP Ver.4, UDP, ICMP, ARP, PPPoE, IGMP
Includes Hardware Ethernet protocols: DLC, MAC
Supports 4 independent connections simultaneously
Supports MCU bus Interface and SPI Interface
Supports Direct/Indirect mode bus access
Supports Socket API for easy application programming
Interfaces with two 2.54mm pitch 2 x 10 header pin
Temperature :
[PCB rev1.0] : 0 ~ 70℃ (Operation), -40 ~ 85℃ (Storage)
[PCB rev1.1] : -40 ~ 85℃ (Operation), -40 ~ 85℃ (Storage)
1.2. Block Diagram
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1.3. Difference between WIZ811MJ and WIZ812MJ
WIZ811MJ WIZ812MJ
Two 2.54mm pitch 10x2 header
The same pin-header is mounted but pin description is different J2:9 GND -> RX_LED J2:10 GND -> TX_LED J2:19 GND -> /LINKLED
Two PCB Through Hole(Ø 3.00mm) Four PCB Through Hole(Ø 3.00mm)
55.5 x 25 x 23.5mm (W x H x D) The same size
LINKLED : Active low in link state indicates a good status for 10/100M. It is always ON when the link is OK and it flashes while in a TX or RX state.
/LINKLED : Active low in link state indicates a good status for 10/100M. It is always ON when the link is OK. It does not flashes while in a TX or RX state.
ACT_LED : Active low in active state indicates a good status for 10/100M. It is always ON when the link is OK and it flashes while in a TX or RX state.
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2. Pin Assignments & descriptions
2.1. Pin Assignments
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I : Input O : Output I/O : Bi-directional Input and output P : Power
2.2. Power & Ground Symbol Type Pin No. Description
3V3D P J1:12 , J2:1 Power : 3.3 V power supply
GND P J1:11, J2:20 Ground
2.3. MCU Interfaces
Symbol Type Pin No. Description
SCLK I J2:3 SCLK(Serial Clock) This pin is used to SPI Clock Signal pin.
/SCS I J2:4
/SCS (Slave Select) * This pin is used to SPI Slave Select signal Pin. This pin controls SPI_EN signal of W5100. When /SCS signal assert low, W5100 drive SPI mode by SPI_EN signal toggled high.
MOSI I J1:1 MOSI (Master Out Slave In) * This pin is used to SPI MOSI signal pin.
MISO I/O J1:2 MISO (Master In Slave Out) * This pin is used to SPI MISO signal pin.
A14~A8 I J1:13 ~ J1:19
Address Used as Address[14-8] pin
A7~A0 I J2:11 ~ J2:18 Address Used as Address[7-0] pin
D7~D0 I/O J1:3 ~ J1:10 Data 8 bit-wide data bus
/CS I J2:7 Module Select : Active low. /CS of W5100
/RD I J2:6 Read Enable : Active low. /RD of W5100
/WR I J2:5 Write Enable : Active low /WR of W5100
/INT O J2:8
Interrupt : Active low After reception or transmission it indicates that the W5100 requires MCU attention. By writing values to the Interrupt Status Register of W5100 the interrupt will be cleared. All interrupts can be masked by writing values to the IMR of W5100 (Interrupt Mask Register). For more details refer to the W5100 Datasheet
WIZ812MJ Datasheet
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2.4. Miscellaneous Signals Symbol Type Pin No. Description
/RESET I J2:2
Reset : This pin is active low input to initialize or re-initialize W5100. By asserting this pin low for at least 2us, all internal registers will be re-initialized to their default states.
RX_LED O J2:9 RX_LED : Receive activity LED Active low indicates the presence of receiving activity.
TX_LED O J2:10 TX_LED : Transmit activity LED Active low indicates the presence of transmitting activity.
/LINKLED O J2:19
LINKLED : Active low in link state indicates a good status for 10/100M. It is always ON when the link is OK. It does not flashes while in a TX or RX state.
NC - J1 : 20 Not Connect
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3. Timing Diagrams WIZ812MJ provides following interfaces of W5100. -. Direct/Indirect mode bus access -. SPI access
3.1. Reset Timing
Description Min Max
1 Reset Cycle Time 2 us -
2 /RESET to internal PLOCK - 10 ms
3.2. Register/Memory READ Timing
Description Min Max
1 Read Cycle Time 80 ns -
2 Valid Address to /CS low time 8 ns -
3 /CS low to /RD low time - 1 ns
4 /RD high to /CS high time - 1 ns
5 /RD low to Valid Data Output time - 80 ns
6 /RD high to Data High-Z Output time - 1 ns
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3.3. Register/Memory WRITE Timing
Description Min Max
1 Write Cycle Time 70 ns -
2 Valid Address to /CS low time 7 ns -
3 /CS low to /WR high time 70 ns -
4 /CS low to /WR low time - 1 ns
5 /WR high to /CS high time - 1 ns
6 /WR low to Valid Data time - 14 ns
3.4. SPI Timing
Description Mode Min Max
1 /SS low to SCLK Slave 21 ns -
2 Input setup time Slave 7 ns -
3 Input hold time Slave 28 ns -
4 Output setup time Slave 7 ns 14 ns
5 Output hold time Slave 21 ns -
6 SCLK time Slave 70 ns
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4. Dimensions
Symbols Dimensions (mm)
A 25.00
B 22.86
C 17.00
D 3.00
E 4.00
F 52.00
G 3.20
H 33.02
I 9.00
J 2.54
K 2.54
L 15.90
M 13.50
N 6.00
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5. Schematic
C2
21
0u
F/1
6V
C2
13
.3uF
/16V
C2
31
0u
F/1
6V
1V
8_O
UT
C2
50
.1uF
C2
40
.1uF
R1
1
4.7
K
1V
8D
C2
60
.1uF
C2
70
.1uF
3V
3D
C2
90
.1uF
C2
80
.1uF
/SC
S
D5D4D3D2
CH
GN
D
D7
1V
8D
XTL
P
D6
R1
1M
C2
15pF
Y1
25M
Hz (S
MD
)
C1
15pF
XTLP
R6
12K
(1%
)
R7
300
(1%
)
XTLN
3V
3D
XTL
N
VC
C
RS
ET_
BG
/LIN
KLE
D
AC
T_
LE
D
1V
8D
1V
8D
3V
3A
3V
3D
1V8D
RXIP
1V8D
/RE
SE
T
C1
2
0.1
uF
3V
3D
RXIN
R2
49.9
R3
49.9
C3
0.1
uF
C4
0.1
uF
R8
49.9
R9
49.9
TXO
P
C5
0.1
uF
R5
200
R4
200
SPI_EN
TXO
N
C1
3
0.1
uF
SCLK
C1
4
0.1
uF
1V8AMOSI/SCS
C6
0.1
uF
C1
00
.1uF
CH
GN
D
CH
GN
D
/WR
/RD
MISO
/CS
/INT
1V
8A
A2
A1
A0
A4
A3
A5
A7
A6
TXO
P
RXIP
A8
RXIN
TXO
N
U1
W5
10
0
RS
ET_
BG
1
VC
C3
V3
A2
NC
3
GN
DA
4
RXIP
5
RXIN
6
VC
C1
V8
A7
TXO
P8
TXO
N9
GN
DA
10
1V
8_O
UT
11
VC
C3
V3
D12
GN
DD
13
GN
DD
14
VC
C1
V8
D15
VC
C1
V8
D16
GN
DD
17
VC
C3
V3
D18
DA
TA
719
DA
TA
620
DATA521
DATA422
DATA323
DATA224
DATA125
DATA026
MISO27
MOSI28
/SCS29
SCLK30
SEN31
GNDD32
VCC1V8D33
TEST_MODE334
TEST_MODE235
TEST_MODE136
TEST_MODE037
ADDR1438
ADDR1339
ADDR1240
AD
DR
11
41
AD
DR
10
42
GN
DD
43
VC
C3
V3
D44
AD
DR
945
AD
DR
846
AD
DR
747
AD
DR
648
AD
DR
549
AD
DR
450
AD
DR
351
AD
DR
252
AD
DR
153
AD
DR
054
/CS
55
/INT
56
/WR
57
/RD
58
/RE
SE
T59
NC
60
NC61NC62OPMODE063OPMODE164OPMODE265LINKLED66SPDLED67GNDD68VCC1V8D69FDXLED70COLLED71RXLED72TXLED73VCC1V8A74XTLN75XTLP76GNDA77NC78NC79NC80
A9
U2
BS
-RB
10
00
5
TD
+1
TD
-2
TC
T3
NC
14
NC
25
NC
36
RD
+7
RD
-8
L1+
12
L2-
11
L3+
10
L4-
9
CH
_G
ND
113
CH
_G
ND
214
3V
3D
1V
8_O
UT
LINK_LEDA
10
3V
3A
3V
3D
A13A12
A11
A14
FB
21uH
1V
8A
C1
1
10u
F/1
6V
C7
10u
F/1
6V
C9
0.0
1u
F
FB
11uH
3V
3D
1V
8A
3V
3A
D1D0
U5
SN
74L
VC
1G
79D
CK
D1
CL
K2
GN
D3
Q4
VC
C5
TX_
LE
D
C1
9
0.1
uF
RX_
LE
D
/LIN
KLE
D
3V
3D
J1
HE
AD
ER
10X2
2.5
4 P
itch
1357911
13
15
17
19
246810
12
14
16
18
20
J2
HE
AD
ER
10X2
2.5
4 P
itch
1357911
13
15
17
19
246810
12
14
16
18
20
C1
8
0.1
uF
MO
SI
D3
D5
D7
MIS
O
D2
D4
D6
GH
4
CO
N8
12345678
CH
GN
D
GH
5
CO
N8
12345678
CH
GN
D
D0
GH
3
CO
N1
1
GH
1
CO
N8
12345678
3V
3D
CH
GN
D
U6
SN
74L
VC
1G
32D
CK
A1
B2
GN
D3
Y4
VC
C5
U7
SN
74L
VC
2G
08D
CT
1A
1
1B
2
2Y
3
GN
D4
2A
5
2B
6
1Y
7V
CC
8
SP
I_E
N
GH
2
CO
N8
12345678
CH
GN
D
/RE
SE
T
/INT
/RD
/CS
/WR
SC
LK
TX_LED
A0
A1
/SC
SA
2
/LIN
KLE
D
U4
SN
74L
VC
2G
14D
CK
1A
1
GN
D2
2A
32Y
4
VC
C5
1Y
6
A4
A6
A3
A5
RX_LED
A7
3V
3D
C1
7
0.1
uF
A8
A9
A10
A11
A12
A13
D1
A14
3V
3D
C2
0
0.1
uF
3V
3D
3V
3D
RX_
LE
D
Title
Size
Do
cu
me
nt N
um
ber
Re
v
Da
te:
Sheet
of
<D
oc>
1.1
WIZ
812M
J
A3
11
Th
urs
day
, Octo
be
r 04, 2
01
2
LIN
K_L
ED
AC
T_
LE
D
TX_
LE
D
WIZ812MJ Datasheet
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6. Partlist
Item Q.ty Reference Part Tech. Characteristics Package
1 2 C1,C2 15pF 50V-20% Ceramic CASE 0603
2 18
C3,C4,C5,C6,C10, C12,C13,C14,C17, C18,C19,C20,C24, C25,C26,C27,C28, C29
0.1uF 50V-20% Ceramic CASE 0603
3 4 C7,C11,C22,C23 10uF/16V 16Vmin 10% EIA/IECQ 3216
4 1 C21 3.3uF/16V 16Vmin 10% EIA/IECQ 3216
5 1 C9 0.01uF 50V-20% Ceramic CASE 0603
6 2 FB1,FB2 1uH Ferrite Inductor CASE 0805
7 2 J1,J2 2X10 2.54mm DIP STRAIGHT Header
2 X 10 2.54mm pitch
8 1 R1 1M 1/10W-5% SMD CASE 0603
9 4 R2,R3,R8,R9 49.9 (1%) 1/10W-1% SMD CASE 0603
10 2 R4,R5 200 1/10W-5% SMD CASE 0603
11 1 R6 12K (1%) 1/10W-1% SMD CASE 0603
12 1 R7 300 (1%) 1/10W-1% SMD CASE 0603
13 1 R11 4.7K 1/10W-5% SMD CASE 0603
14 1 U1 W5100 WIZnet Hardware TCP/IP LQFP80
15 1 U2 BS-RB10005 Transformer + RJ45
16 1 U4 SN74LVC2G14DCK Dual Inverting Buffer SC70-6
17 1 U5 SN74LVC1G79DCK D-type Flip Flop (vendor : TI) SC70-5
18 1 U6 SN74LVC1G32DCK OR-Gate (vendor : TI) SC70-5
19 1 U7 SN74LVC2G08DCT Dual AND-Gate (vendor : TI) SM8
20 1 Y1 25MHz (SMD) SMD Type, Industrial SX-1
21 1 PCB REV1.1 FR4, 1.6T, 4Layer