Wireless Security Systemweb.mit.edu/6.111/www/s2006/PROJECT/12/Presentation12.pdfNTSC Decoder 20 30...
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Wireless Security System Noel Campbell Vivek Shah Raymond Tong TA: Javier Castro
Transcript of Wireless Security Systemweb.mit.edu/6.111/www/s2006/PROJECT/12/Presentation12.pdfNTSC Decoder 20 30...
Wireless Security System
Noel CampbellVivek Shah
Raymond Tong
TA: Javier Castro
Video Surveillance Block Diagram
Video Capture Overview
CameraADV7185
Composite Intv_in_ycrcb
[19:0]
Clock_27MHz
tv_clock
MemoryController
Dual-PortBlock
Memory
VGAController
ycrcb [29:0]
X
WE
Y
ADDR
YCrCb toRGB
Converter
Display
NTSCDecoder
20 30
AsyncFIFO
Clock_27MHz
Z
RGB
Syncing andblanking signals
encode_busy
writing_memory
Y isolator8
Y [7:0]
Technical Considerations
Synchronization of dataADV7185 clock vs lab kit 27 MHz clock
Displaying data in VGAAcquire 240 X 240 real time video
Write data to block memory then continuously readfrom it
Memory ControllerWrite a frame worth of data into block memory
for encoding and transmission
Video Compression
Discrete CosineTransform
Inverse DiscreteCosine Transform
512 bits/block
56 bits/block
Video Encoder
8
Dual Port
Block
Memory(64x900)
Dual Port
Block Memory
(64x900)
Dual Port
Block Memory
(64x900)
Dual PortBlock
Memory
(64x900)
Dout
64
Dout
64
Dout
64
Dout
64
Multiplier
Block
Finite State MachineAddress (10)
Adder
Block
And
Truncate
Module
Matrix _int0
144
Matrix _int1
144
Matrix _int2
144
Matrix _int3
144
144Multiplier
Block
Adder
Block
288
288
288
288
DCT
Coefficients
DCT
Coefficients
Encoding _line (10)
Wireless _busy
Dual Port
Block
Memory
(80x900)
Address (10) and WE
Line_write (5)
Wireless Transmission Data is sent serially from the
labkit to the wireless kit
Data is assembled into packetsand sent from camera-end tofixed-end via CC2420 radio
Data is then sent serially fromreceiver wireless kit to thereceiver labkit
Transmitter
80 x 900Dual Port
BRAM
80Radio
Transmitter
to receiver
serialcable
Transmitter Control Unit
ShiftRegister
RS232Sender
from encoder
8
FPGA microcontroller
Receiver
80 x 900Dual Port
BRAM
Transmitter Control Unit
RS232Receiver
ShiftRegister
80RadioReceiver
serialcable
from transmitter
to decoder
FPGAmicrocontroller
Video Decoder
Address
Registers(80) Dout
80
Multiplier Block
Finite State Machine
Adder Block
Matrix_int0
144
Matrix_int1
144
144
144
144
144
Multiplier
BlockAdder Block
288
288
288
288
DCT Coefficients
DCT Coefficients
LINE_DONE (5)
LINE_READ (5)
Address (10) and WE
Block_done
Ready
Dual Port
Block Memory
(64x900)
Dual PortBlock
Memory
(64x900)
Dual PortBlock
Memory(64x900)
Dual Port
Block
Memory(64x900)
64
64
64
64
Video Display Overview
Y [7:0]
Dual-PortBlock
Memory
8
VGAController
YCrCb toRGB
ConverterDisplay
Z
RGB
Syncing andblanking signals
Addr X
Delay
Z
* Only chrominance (Y) is important if displaying grayscale image
Clock_27MHz
to all modules
decode_done MemoryController
