WGR7640 IC GNSS RF Receiver Design Guidelines · 1.3 WGR7640 within the APQ chipset ... 16 Figure...

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LM80-P0436-29 Rev B

WGR7640 IC GNSS RF Receiver Design Guidelines

LM80-P0436-29 Rev B

September 2016

https://developer.qualcomm.com/forums/qdn-forums/hardware

LM80-P0436-29 Rev B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 2

Revision history

Revision Date Description

B September 2016 Update to ‘E’ part

A August 11, 2015 Initial release


Contents

1 Overview ................................................................................................................................ 5

1.1 Purpose ..................................................................................................................................................... 5 1.2 Acronyms, abbreviations, and terms .......................................................................................................... 5 1.3 WGR7640 within the APQ chipset ............................................................................................................. 6 1.4 Overview of WGR7640 topics .................................................................................................................... 6 1.5 WGR7640 features .................................................................................................................................... 7

2 WGR7640 System.................................................................................................................. 8

2.1 GNSS receiver system block diagram ....................................................................................................... 8

3 WGR IC Details – RF ............................................................................................................. 9

3.1 WGR RF receivers high-level comments ................................................................................................... 9 3.2 WGR7640 RF receiver pin assignments .................................................................................................... 9

4 WGR IC Details – Baseband Interfaces ..............................................................................11

4.1 WGR Rx baseband interfaces with Application Processor Qualcomm (APQ) IC ..................................... 11 4.2 WGR RF GNSS input ports – schematic ................................................................................................. 11 4.3 WGR RF GNSS input ports – layout guidelines ....................................................................................... 12 4.4 GNSS receiver matching procedure ........................................................................................................ 13

5 WGR IC Details – Support Circuits .....................................................................................14

5.1 WGR support circuits high-level comments ............................................................................................. 14 5.2 GNSS LO synthesizer .............................................................................................................................. 14 5.3 WGR digital status and control ................................................................................................................ 15

6 Top-level Design Topics ......................................................................................................17

6.1 Top-level parts placement WGR .............................................................................................................. 17 6.2 Shielding recommendations ..................................................................................................................... 18 6.3 WGR DC power topology ......................................................................................................................... 18 6.4 WGR IC DC routing and bypassing – general ......................................................................................... 19 6.5 WGR ground connections ........................................................................................................................ 19

EXHIBIT 1 .................................................................................................................................21

Figures

Figure 1-1 WGR7640 within the APQ chipset ................................................................................................................ 6 Figure 1-2 WGR7640 top-level layout guidelines ........................................................................................................... 6 Figure 2-1 GNSS receiver system block diagram .......................................................................................................... 8 Figure 3-1 WGR RF receivers ........................................................................................................................................ 9 Figure 3-2 WGR7640 RF receiver pin assignments ..................................................................................................... 10 Figure 4-1 WGR Rx baseband interfaces with APQ IC ................................................................................................ 11

WGR7640 IC GNSS RF Receiver Design Guidelines Contents


Figure 4-2 WGR RF GNSS input ports ........................................................................................................................ 12 Figure 4-3 WGR RF GNSS input ports ........................................................................................................................ 12 Figure 4-4 GNSS receiver matching ............................................................................................................................ 13 Figure 5-1 WGR support circuits .................................................................................................................................. 14 Figure 5-2 GNSS LO synthesizer ................................................................................................................................. 15 Figure 5-3 WGR digital status and control ................................................................................................................... 16 Figure 6-1 Top-level parts placement WGR ................................................................................................................. 17 Figure 6-2 WGR DC power topology ............................................................................................................................ 18 Figure 6-3 WGR ground connections ........................................................................................................................... 20

Tables

Table 1-1 Acronyms, abbreviations, and terms .............................................................................................................. 5 Table 3-1 Supported frequency bands ........................................................................................................................... 9


1 Overview

1.1 Purpose

This document provides a description of the WGR7640 IC chipset capabilities. Not all features

are available, nor are all features supported in the software.

NOTE: Enabling some features may require additional licensing fees.

1.2 Acronyms, abbreviations, and terms

Table 1-1 provides definitions for the acronyms, abbreviations, and terms used in this document.

Table 1-1 Acronyms, abbreviations, and terms

Term Definition

APQ Application Processor Qualcomm

CSP Control Switching Point

GLONASS Global NAvigation Satellite System

GNSS Global Navigation Satellite System

GPS Globas Positioning System

LO Local Oscillator

PLL Phase-locked Loop

PMIC Power Management Integrated Circuit

RF Radio Frequency

SSBI Signal-Signal Beating Interference

WGR WLP GPS Receiver

WLP Wafer-level Package

WGR7640 IC GNSS RF Receiver Design Guidelines Overview


1.3 WGR7640 within the APQ chipset

PMIC

SDRAM

Memory supportPower & Ground

Multimedia

APQ

Chipset I/Fs Internal functions

GPIOs

NFC

Peripherals

eMMC

debug

WLAN / BT

WL

AN

/ B

T

fro

nt-

en

d

GNSS Rx

LO circuits

Status & control

WGR7640

Sensors

GNSS

circuitsGNSS PRx

LCD/HDMI

I2C

I2C

I2C web

cam

PMIC

clocks

I2CI2C

SPI

WCN3620

Rx

Bluetooth

RF & BB

command

external

sources

battery

Vibration

motor

Backlights,

LEDs, etcUser

Interfaces

Input Power

Management

Output Power

Managementsupply

voltages

General

Housekeeping

IC Interfaces

supply

voltages

analog

sensorsclocks

others

power-on

WLAN RF

FM radio RF & BB Su

pp

ort

& I/O

s

SSBI

data & clk

SSBI

data

SSBI

S&C

SSBI

I2CSPI

WL

AN

BT

FM

S&C

SSBI

S&C

SSBI

SD/

MMC

GNSS RX0

WLAN T/R

Connectivity

USB

Ext

audio

D

A

D

A

Au

dio

tra

nsd

uce

rs Audio

codecADCs

DACs

DMICs

OTHC

mic bias

A A

Figure 1-1 WGR7640 within the APQ chipset

1.4 Overview of WGR7640 topics

This document provides an introduction to the WGR system, followed by three major sections:

RF receivers, baseband interface, and support circuits (as shown in Figure 1-2).

LNA LPF

LPF

Qu

ad

ratu

re

do

wn

co

nve

rte

r

LO generation

& distribution

GPSBPF

GPS

antenna

WGR7640

GNSS Rx

baseband

digital status

& controlstatus & controls

SSBI

GND

BB_IP

BB_IM

BB_QP

BB_QM

RF_P

RF_M

GND

VCO

XO

to other

circuits

PLL

circuits

FDBK

GNDs

VDD_RF_1P3

VDD_RF_1P3

VDD_DIG_1P8

VDD_RF_1P3

Po

we

r su

pp

ly/

bia

s c

ircu

its

Dig

ita

l I/O

s

& c

on

tro

ls

1) RF receivers

3) Support

circuits

to PM8916

2) Baseband interface

Figure 1-2 WGR7640 top-level layout guidelines

WGR7640 IC GNSS RF Receiver Design Guidelines Overview


1.5 WGR7640 features

Salient features:

Small package: 2.07 mm × 1.51 mm × 0.63 mm

65 nm wafer-level package (WLP)

17-pin CSP

GNSS stand alone RF receiver

Compatible with Callisto (Gen8A) GPS digital baseband engine

Fully integrated synthesizer PLL, VCO, and loop filter components

Power reduction features for low-power consumption

Single-line serial bus interface (SSBI)

The chipset solution includes the APQ + WGR7640 ICs


2 WGR7640 System

2.1 GNSS receiver system block diagram

LNA LPF

LPF

Qu

ad

ratu

re

do

wn

co

nve

rte

rLO generation

& distribution

GPSBPF

GPS

antenna

VREG_L18

VREG_S4

PMIC

19.2 MHz TCXO

XO output

WGR7640

GNSS Rx

baseband

AP

Q

digital

status &

control

status & controls

SSBI

GND

BB_IP

BB_IM

BB_QP

BB_QM

RF_P

RF_M

GND

VCO

XO

to other

circuits

PLL

circuits

FDBK

GNDs

VDD_RF_1P3

VDD_RF_1P3

VDD_DIG_1P8

VDD_RF_1P3

Po

we

r su

pp

ly/

bia

s c

ircu

its

Dig

ita

l I/O

s

& c

on

tro

ls

I and Q components from the WGR7640 IC are

routed to on-chip ADC circuits in the APQ IC,

that digitize the received signals and route the

serial data streams to the Gen8A Engine.

Dedicated synthesizer used for GNSS operation;

provides the LO for the GNSS receiver

grounded via a

0 Ω resistor 0 Ω

0 Ω

WGR7640 IC can be placed

close to the GNSS antenna and

does not need a GNSS ELNA

1

3

8

9

6

14

11

5

13

16

17

15

2

4

Figure 2-1 GNSS receiver system block diagram


3 WGR IC Details – RF

3.1 WGR RF receivers high-level comments

GNSS quad

downconvert

RF_P

RF_M

LPF

LPF

BB_QM

BB_QP

BB_IM

BB_IPgnss_lo

GNSS

ELNA

BPFfilter

Placeholder components –

depends upon application

GN

SS

Rx

ba

se

ba

nd

WGR7640

RF receivers

BPF

Figure 3-1 WGR RF receivers

Receiver is implemented in 65 nm RFCMOS process which accommodates high-frequency,

high-precision analog circuits and low-power CMOS functions

Independent receive path from RF to baseband (I/Q)

Optimized for standalone operation

Consists of differential RF inputs supporting primary GPS, GLONASS, Compass, Galileo,

and QZSS navigation satellite systems. Supported frequency bands are shown in Table 3-1.

Table 3-1 Supported frequency bands

Satellite system Frequency (MHz)

GPS L1/QZSS 1575.42 ± 1 MHz

GPS L1C, Galileo E1, Compass B1-BOC 1575.42 ± 2 MHz

GPS L1 wide 1575.42 ± 10 MHz

GLONASS R1 1602 ± 4 MHz

Compass B1 1561 ± 2 MHz

3.2 WGR7640 RF receiver pin assignments

GNSS RF ports are grouped together (purple squares)

Sensitive RF signals

RF front-end (filters, etc.) located in this direction as seen in the top view

GNSS baseband (green squares)

Sensitive analog signals

Opposite side away from RF pins

WGR7640 IC GNSS RF Receiver Design Guidelines WGR IC Details – RF


APQ source located in this direction as seen in the top view

15

XO

1

GND

6

BB_I_M

11

BB_Q_M

4

RF_M

16

VDD_

RF_1P3

2

RF_P

5

VDD_

RF_1P3

3

GND

9

BB_I_P

10

GND

14

BB_Q_P

13

VDD_

RF_1P3

8

SSBI

17

VDD_

DIG_1P8

7

GND

12

GND

Figure 3-2 WGR7640 RF receiver pin assignments


4 WGR IC Details – Baseband Interfaces

4.1 WGR Rx baseband interfaces with Application Processor Qualcomm (APQ) IC

APQ deviceWGR7640 device

GNSS quad

downconvert

LPF

LPF

BB_QM

BB_QP

BB_IM

BB_IP

SSBI

GNSS_BB_QP

GNSS_BB_QM

GNSS_BB_IP

GNSS_BB_IM

gnss_lo

GPIO_81

SSBI_EXT_GPS

Figure 4-1 WGR Rx baseband interfaces with APQ IC

The baseband interface has two differential pairs: in-phase (I) and quadrature (Q):

The I and Q baseband outputs are sensitive analog signals.

Route the I and Q signals as phase-critical differential pairs.

The resistance and capacitance on each pair should be equal.

Avoid crossing these traces; if necessary, cross them only near the APQ end points.

Isolate the device from digital logic and clock traces with ground all around; treat

similarly to controlled-impedance traces.

The length of the I/Q traces between the APQ and WGR should be equal and should not

exceed 8 inches.

4.2 WGR RF GNSS input ports – schematic

Optional:

An external LNA (not required)

Space and pads for an external LNA preceded by a second bandpass filter (to allow addition

of these components if necessary)

WGR7640 IC GNSS RF Receiver Design Guidelines WGR IC Details – Baseband Interfaces


WGR7640

RF_P

RF_M

GNSS

BPF

from GNSS antenna –

may include more filtering

and/or external LNA

C15

1.2 pF

L3

10 nH

L4

10 nH

GNSS

100 W diff traces

Figure 4-2 WGR RF GNSS input ports

4.3 WGR RF GNSS input ports – layout guidelines

= stripline connection

17 13 8 3

10 5

16 12 7 2

15 11 6 1

9 414The GNSS input is extremely sensitive

and must be protected accordingly.L4

from GNSS

BPF100 W diff

L3C

15

Figure 4-3 WGR RF GNSS input ports

Traces from the filters (pink arrows) must use controlledimpedance techniques – microstrip

or stripline – designed to provide 100 Ω differential (nominal). Stripline provides higher

isolation since it is surrounded by ground planes.

The components are close to the WGR pins; routing is short and direct.

If needed, the areas directly below all component pads and signal traces are cleared of metal

on layer 2 to minimize parasitic capacitance (not shown).

Inductors should be placed in ways that limit mutual coupling.

The complementary paths within each differential pair should be as symmetrical as possible

to preserve their phase balance and maintain common-mode rejection.

Where possible, isolate matching components and traces from all other circuits and traces

using coplanar ground fill (not shown).

Trace capacitances between WGR input pins and matching components should be kept very

low.

Some extra components are included in initial layouts to increase matching flexibility but

might prove unnecessary after careful testing and evaluation.

Specific RF grounding guidelines should be followed:

The ground side of the RF components must connect as directly as possible to the nearest

ground reference and should connect to multiple ground fills on multiple layers to

provide the best grounding.

Do not allow long, thin traces to connect RF components to ground – the added trace

inductance could disrupt circuit performance.

Microvias from the ground pads directly to the PCB ground plane are recommended.

A total ground inductance of less than 100 pH is desired.

WGR7640 IC GNSS RF Receiver Design Guidelines WGR IC Details – Baseband Interfaces


4.4 GNSS receiver matching procedure

Measure the differential 100 Ω input return loss (Sdd11) looking into the WGR device’s

matching network.

Iteratively adjust the matching network with minor component changes to achieve the desired

performance, making trade-offs between the following objectives as needed:

Center the passband and provide sufficient bandwidth.

Minimize the nominal noise figure using sensitivity measurements.

Standard values of inductors and capacitors can be selected.

The type and size of inductors can affect noise figure.

C3Measure Sdd11

L3

L1C1

C2

WGR7640

Figure 4-4 GNSS receiver matching


5 WGR IC Details – Support Circuits

5.1 WGR support circuits high-level comments

WGR pins and circuits that provide secondary support functions to the RF transceiver

include:

GNSS LO synthesizer and related

19.2 MHz XO input

Digital status and control signals

Single-wire serial bus interface (SSBI)

Grounds

Pins 1 and 3 – grounded via a 0 Ω resistor

GNSS LO

circuits

WGR7640A

PQ

digital status

& control

status & controls

SSBI

GND

GND

XO

Dig

ita

l I/

Os

& c

on

tro

ls

0 Ω

0 Ω

19.2 MHz

TCXO ref clk

f_ref to other circuits

Support circuits

8

1

3

15

Figure 5-1 WGR support circuits

5.2 GNSS LO synthesizer

The integrated local oscillator (LO) generation and distribution circuits are driven by internal

VCOs to support various modes to yield highly flexible quadrature LO outputs to the GNSS

down converter.

The WGR7640 IC has a dedicated synthesizer used for GNSS operation. This synthesizer

provides the LO for the GNSS receiver.

WGR7640 IC GNSS RF Receiver Design Guidelines WGR IC Details – Support Circuits


For the WGR7640 IC, an external 19.2 MHz input signal obtained from the PMIC device is

required to provide the synthesizer frequency reference to which the PLL is phase- and

frequency-locked.

The WGR7640 IC integrates all of the PLL loop filter components on-chip. With the

integrated PLL synthesizers, the WGR7640 IC has the advantage of more flexible loop

bandwidth control, fast lock time, and low integrated phase error.

WGR7640

0.8 to

2.0 Vpp

AC-coupling

capacitor required

XO

GNSS PLL

circuits

FDBK

GNSS

VCOgnss_lo to LO

distribution circuits

REF

GNSS

control

GNSS LO synthesizer

XO_OUT_A1

PMICto other

circuits1000 pF

Loop filter

Figure 5-2 GNSS LO synthesizer

5.3 WGR digital status and control

Power (VDD_DIG_1P3) – Use the same supply that is used for APQ digital I/Os to ensure

logic compatibility and prevent latchups.

SSBI allows efficient initialization, GNSS mode and parameter controls, and programming

verification:

The APQ device’s SSBI controller is the master while the WGR circuit is the slave.

SSBI is clocked at 19.2 MHz (reference clock frequency), so good layout techniques are

extremely important.

The SSBI signal is decoded and used to set on-chip control signals to the GNSS functional

blocks. GNSS status is also reported to the APQ device through these circuits and SSBI.

WGR7640 IC GNSS RF Receiver Design Guidelines WGR IC Details – Support Circuits


Oth

er

I/O

s

Primary IC operating

modes, such as sleep,

warmup, air interface

technology, etc.

RF

tra

nsce

ive

r sta

tus &

co

ntr

ol

SS

BI

SSBI

GND

VDD_DIG_1P3 VREG_S4

(1.8 V)

Supports GNSS functions

Circuit parameters

such as gain, bias

conditions, on/off, clock

rates, LO frequencies,

etc.

Primary status &

control signaling

GND

APQ

GPIO_xx

SSBI_EXT_GPS

Figure 5-3 WGR digital status and control


6 Top-level Design Topics

6.1 Top-level parts placement WGR

1. Place the WGR section as close as possible to the GNSS antenna.

2. Digital devices and traces must not be placed near the top edge because they generate noise

that could couple onto antennas, degrading performance (self-jamming/spurs).

3. Isolate the power management circuitry – especially SMPS circuits – from the WGR circuits.

4. The 19.2 MHz clock trace between the WGR7640 and PM8921 should be well isolated.

5. Allow space for shields. Specific shielding guidelines are given next.

PMIC

APQ

eMMC

USB

conn

DC

jack

SD

WCN

3620

LC

D

HD

MI

Codec

WGR7640camera H

PH

Wireless GPS

Receiver

AUDIO

POWERDISPLAY

DIGITAL

Wireless

Connectivity

Figure 6-1 Top-level parts placement WGR

WGR7640 IC GNSS RF Receiver Design Guidelines Top-level Design Topics


6.2 Shielding recommendations

Shield the WGR7460 IC, its matching components, RF front end components, digital

(including the APQ device), and PMIC circuits.

Metal cans are better than metallized plastic.

Recommended shield partitioning:

Preserve Tx-to-Rx isolation

WGR IC and its Rx matching components in one shield and RF front end components in

another shield

Do not locate WGR matching inductors too close to shield walls (this might cause EM

coupling and inductor de-Q)

6.3 WGR DC power topology

The number of bypass capacitors required in a final design depends upon the PCB layout:

Initial designs should begin with “extra” series components (such as resistors, inductors,

or beads) and bypass capacitors.

After extensive test and evaluation, their numbers might be reduced prior to production.

Ground bypass capacitors with vias that are connected directly to the internal PCB RF ground

plane.

Avoid thin, high-inductance traces.

PMIC

5

17

13

16

1.3

V

L181

.8 V

VREG_S4

C18

0.1 mF

C20

0.1 mF

C17

1.0 mF

DNI

R8

zero

R10

zero

C19

0.1 mF

R9

zero

C16

1.0 mF

DNI

WGR7460

VDD_DIG_1P8

VDD_RF_1P3

VDD_RF_1P3

VDD_RF_1P3

Place C18, C19, and C20

close to the WGR IC

Figure 6-2 WGR DC power topology



6.4 WGR IC DC routing and bypassing – general

WGR device VDD_RF pads

VDD_RF bypass capacitor

from VREG

branch at

capacitor onlyouter layer or inner layer



from

VREG



from VREG

C

WGR circuits

DC PWR

Ground

Inductance loop

VDD vias

Ground vias

C

WGR circuitsIf on same side, keep

this distance short

Star configuration with dedicated traces

from capacitor to each WGR IC pin

Daisy-chain configuration with shared traces

from capacitor to multiple WGR IC pins

WGR IC and bypass capacitor on the same side

GOOD do not branch at

other places away

from capacitor

BAD

WGR IC and bypass capacitor on opposite sides

Opposite side bypassing is better

due to lower loop inductance

DC PWR

17 13 8 3

10 5

16 12 7 2

15 11 6 1

9 414

RF power bus

GOOD

C

17 13 8 3

10 5

16 12 7 2

15 11 6 1

9 414

RF power bus

C

BAD

6.5 WGR ground connections

Proper grounding is crucial:

Dedicate at least one layer for ground – layer 5 is shown for example

Ground plane – common point referenced by all handset circuits

Fill unused space on all layers to provide robust layer-to-layer ground

Connect bypass caps directly to surface ground fill, with multiple vias to layer 5 ground

Keep WGR ground pins separate from all other circuit grounds until they converge on layer 5:

Via each set as directly as possible to the layer 5 ground plane.

Include as much ground fill as possible to each layer between 1 and 5 below the WGR

device, connecting each stack of vias to the WGR ground fill areas.

Use a large copper mass to provide the best possible electrical ground and thermal

conductivity – both needed for WGR performance.



Layer 1

Layer 2

Layer 3

Layer 4

Layer 5

Layer 6

Layer 7

Layer 8

WGR ground pins

Below the WGR device – isolate WGR

grounds from all others on all layers

except the PCB ground plane layer

The two grounds are tied together

ONLY on the PCB ground layer

Other (non-WGR)

ground connections

Conceptual

illustration

17 13 8 3

10 5

16 12 7 2

15 11 6 1

9 414

Figure 6-3 WGR ground connections


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2. COMPLIANCE WITH LAWS; APPLICABLE LAW. You agree to comply with all applicable local, international and national laws and regulations and with U.S. Export Administration Regulations, as they apply to the subject matter of this Agreement. This Agreement is governed by the laws of the State of California, excluding California’s choice of law rules.

3. CONTRACTING PARTIES. If the Materials are downloaded on any computer owned by a corporation or other legal entity, then this Agreement is formed by and between QTI and such entity. The individual accepting the terms of this Agreement represents and warrants to QTI that they have the authority to bind such entity to the terms and conditions of this Agreement.

4. MISCELLANEOUS PROVISIONS. This Agreement, together with all exhibits attached hereto, which are incorporated herein by this reference, constitutes the entire agreement between QTI and You and supersedes all prior negotiations, representations and agreements between the parties with respect to the subject matter hereof. No addition or modification of this Agreement shall be effective unless made in writing and signed by the respective representatives of QTI and You. The restrictions, limitations, exclusions and conditions set forth in this Agreement shall apply even if QTI or any of its affiliates becomes aware of or fails to act in a manner to address any violation or failure to comply therewith. You hereby acknowledge and agree that the restrictions, limitations, conditions and exclusions imposed in this Agreement on the rights granted in this Agreement are not a derogation of the benefits of such rights. You further acknowledges that, in the absence of such restrictions, limitations, conditions and exclusions, QTI would not have entered into this Agreement with You. Each party shall be responsible for and shall bear its own expenses in connection with this Agreement. If any of the provisions of this Agreement are determined to be invalid, illegal, or otherwise unenforceable, the remaining provisions shall remain in full force and effect. This Agreement is entered into solely in the English language, and if for any reason any other language version is prepared by any party, it shall be solely for convenience and the English version shall govern and control all aspects. If You are located in the province of Quebec, Canada, the following applies: The Parties hereby confirm they have requested this Agreement and all related documents be prepared in English.

WGR7640 IC GNSS RF Receiver Design Guidelines · 1.3 WGR7640 within the APQ chipset ... 16 Figure...

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Transcript of WGR7640 IC GNSS RF Receiver Design Guidelines · 1.3 WGR7640 within the APQ chipset ... 16 Figure...