WG7310-00 WLAN+BT+FM Module TI WL1271 solution · 1. WG7310 Module Description WG7310, a WLAN ,...

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WG7310-00 WLAN+BT+FM Module

TI WL1271 solution

Hardware Design Guide

Revision 0.3

Doc No: WG7310-00-HDG-R03


CONFIDENTIAL - 1-

Contents

1. WG7310 MODULE DESCRIPTION ........................................................................3

1.1. WG7310 BLOCK DIAGRAM ...............................................................................3

1.2. PIN DESCRIPTION .................................................................................................4

2. ELECTRICAL CHARACTERISTICS .........................................................................7

2.1. ABSOLUTE MAXIMUM RATINGS.............................................................................7

2.2. RECOMMENDED OPERATING CONDITIONS ..........................................................7

2.3. EXTERNAL SLOW CLOCK INPUT (SLEEP_CLK).....................................................7

3. POWER SEQUENCE ................................................................................................9

3.1. WLAN POWER ON SEQUENCE ............................................................................9

3.2. BLUETOOTH POWER UP/DOWN SEQUENCE........................................................10

4. INTERFACE CHARACTERISTICS ......................................................................... 11

4.1. WLAN SDIO CHARACTERISTIC ......................................................................... 11

4.1.1. SDIO Read Timing ................................................................................ 11

4.1.2. SDIO Interface Write Timing ..............................................................12

4.1.3. SDIO Clock Timing ...................................................................................12

4.2. WLAN WSPI CHARACTERISTICS ........................................................................13

4.2.1. SPI Read/Write Timing.........................................................................13

4.2.2. SPI Clock Timing....................................................................................14

4.3. BLUETOOTH HCI INTERFACE ...............................................................................15

4.4. BLUETOOTH PCM INTERFACE.............................................................................16

5. DEBUG INTERFACE...............................................................................................18

5.1. WLAN RS232 TESTING PORT ............................................................................18

5.2. BLUETOOTH HCI TESTING PORT ..........................................................................18

6. REFERENCE SCHEMATIC.....................................................................................19

7. MODULE MECHANICAL OUTLINE.....................................................................21

8. LAYOUT RECOMMENDATION ...........................................................................22

8.1. RECOMMENDED BUMP PAD DESIGN *...............................................................22

8.2. RECOMMENDED STENCIL DESIGN *....................................................................22

8.3. RECOMMENDED TRACE LAYOUT ........................................................................22

9. SMT AND BAKING RECOMMENDATION ........................................................25



CONFIDENTIAL - 2-

9.1. BAKING RECOMMENDATION..............................................................................25

9.2. SMT RECOMMENDATION...................................................................................25

10. HISTORY CHANGE.............................................................................................27



CONFIDENTIAL - 3-

1. WG7310 Module Description

WG7310, a WLAN , Bluetooth and FM SiP (system in package) module, is the most demanded design for all handset and portable devices with TI WL1271 IEEE 802.11b/g/n and BT v2.1 EDR solutions to provide the best WLAN and BT coexistence interoperability and power saving technologies from TI.

1.1. WG7310 Block Diagram

WLAN

BT

FM

WL1271WL1271 FE

BPF

PA(b/g/n)

SW

DC2DC

38.4M X’tal

Matching

Matching

WG7310

VBAT

VIO

Slow CLK

Host I/F

Host Signaling

Debug I/F

TX

RX



CONFIDENTIAL - 4-

1.2. Pin Description

No. Index Name Type Description 1 A1 GND GND GROUND

2 A2 VBAT_FEM O FEM POWER SUPPLY

3 B1 BT_FUNC2: BT_WU/ DC2DC O BT WU (default) or BT DC2DC

4 B2 GND GND GROUND

5 C1 BT_FUNC6: BT_SDA O BT SDA (internal use only)

6 C2 BT_FUNC4: BT_TX_DBG O BT UARTD (reserved for debug)

7 D1 BT_FUNC5: HOST_WU O HOST WU

8 D2 GND GND GROUND

9 E1 GND GND GROUND

10 E2 DRPWPABC O WL PA BIAS (internal use only)

11 F1 BT_RF_ANT I/O BT RF ANT (internal use only)

12 F2 GND GND GROUND

13 G1 GND GND GROUND

14 G2 DRPWPDET I WL POWER DET IN (internal use only)

15 H1 WL_TX_SW O WLPA_IF (internal use only)

16 H2 GND GND GROUND

17 J1 WL_BTH_SW O WLPA_IF (internal use only)

18 J2 WL_RX_SW O WLPA_IF (internal use only)

19 K1 GND GND GROUND

20 K2 VCC_DCOW O WL DCO SUPPLY

21 L1 NC_C3/VCC_TXAW O WL PPA A SUPPLY

22 L2 GND GND GROUND

23 L3 FM_EN I FM RST

24 K3 VCC_RXW O WL LNA SUPPLY


26 K4 BT_EN I BT RST

27 L5 WB_RF_ANT I/O WL/BT RF ANT

28 K5 GND GND GROUND


30 K6 WL_RS232_RX/ I2S_M_SCL I RS232_RX (default) or I2C_M_SCL

(reserved for debug)

31 L7 SDIO_D1 I/O SDIO IF

32 K7 WL_RS232_TX/ I2S_M_SDA O RS232_TX (default) or I2C_M_SDA



CONFIDENTIAL - 5-

(reserved for debug)

33 L8 SDIO_D2 I/O SDIO IF

34 K8 SPI_CSX/ SDIO_D3 I/O SDIO IF

35 L9 SPI_DIN/ SDIO_CMD I/O SDIO IF

36 K9 SPI_DOUT/ SDIO_D0 I/O SDIO IF

37 L10 SPI_CLK/ SDIO_CLK I SDIO IF

38 K10 FM_I2S_FSYNC I/O FM I2S IF

39 L11 WL_EN I WL RST

40 K11 FM_SDA I/O FM I2C IF

41 J11 FM_SCL I/O FM I2C IF

42 J10 FM_IRQ O FM I2C IF

43 H11 FM_I2S_CLK I/O FM I2S IF

44 H10 FM_I2S_DI I FM I2S IF

45 G11 FM_I2S_DO O FM I2S IF



48 F10 SLOWCLK I SLEEP CLK

49 E11 FM_TX_ANT O FM TX ANT

50 E10 GND GND GROUND

51 D11 GND GND GROUND

52 D10 FMAUDROUT O FM AUD OUT

53 C11 FM_RX_ANT I FM RX ANT

54 C10 GND GND GROUND

55 B11 GND GND GROUND

56 B10 FMAUDLOUT O FM AUD OUT

57 A11 FMAUDRIN I FM AUD IN

58 A10 GND GND GROUND

59 A9 FMAUDLIN I FM AUD IN



62 B8 XTALP O FREF INPUT (internal use only)

63 A7 XTALM O FREF INPUT (internal use only)



66 B6 BT_FUNC1: O BT DC2DC mode (default)



CONFIDENTIAL - 6-

DC2DC/ btSPI_CLK or btSPI_CLK

67 A5 DC_REQ O DC_REQ to INTERNAL DC2DC

68 B5 TPS_DC2DC I MODE SELECTION PIN OF DC2DC

69 A4 VIO I 1.62~1.92V POWER SUPPLY, 1.8V TYP

70 B4 1V8 O 1.8V DC2DC POWER SUPPLY

71 A3 VBAT I 2.3~4.8V POWER SUPPLY, 3.3V TYP

72 B3 VDD_LDO_IN_CLASS1P5 I BT CLASS2/CLASS1.5 POWER SUPPLY

73 D4 PCM_AUD_CLK/

FM_I2S_CLK

I/O PCM I/F (default ) or FM I2S CLK

74 E4 PCM_AUD_IN/ FM_I2S_DI I/O PCM I/F (default ) or FM I2S DI


76 G4 WL_PAEN_B O WLPA_IF (internal use only)

77 H4 GND GND GROUND

78 H5 VCC_ANAW O WLANA INPUT SUPPLY

79 H6 VCC_TXBW O WL PPA BG SUPPLY

80 H7 WL_UART_DBG O WL_UART_DBG (reserved for debug)

81 H8 CLK_REQ_OUT O CLK_REQ positive polarity

82 G8 WLAN_IRQ O WLAN interrupt request

83 F8 HCI_RX/ btSPI_DIN I BT UART I/F (default) or btSPI DIN

84 E8 HCI_TX/ btSPI_DOUT O BT UART I/F (default) or btSPI DOUT

85 D8 BT_FUNC7: BT_SCL I/O BT_SCL (internal use only)

86 D7 HCI_RTS/ btSPI_IRQ I/O BT UART I/F (default) or btSPI IRQ

87 D6 HCI_CTS/ btSPI_CS I/O BT UART I/F (default) or btSPI CS

88 D5 PCM_AUD_FSYNC/

FM_I2S_FSYNC

I/O PCM I/F (default) or FM I2S FSYNC

89 E5 PCM_AUD_OUT/

FM_I2S_DO

O PCM I/F (default) or FM_I2S_DO










CONFIDENTIAL - 7-

2. Electrical Characteristics

2.1. Absolute Maximum Ratings

Over operating free-air temperature range Characteristics Value Unit

VBAT -0.5 to 5.5 V Supply Voltage Range

VIO -0.5 to 2.1 V

Input Voltage to Analog Pins -0.5 to 2.1 V

Input Voltage to all Other Pins -0.5 to VIO + 0.5V V

Operating Ambient Temperature Range -20 to 70 °C

Storage Temperature Range -45 to 85 °C

2.2. Recommended Operating Conditions

The WG7310 requires two supplies: VBAT and VIO. Voltage

Power Supply Min. Typ. Max.

VBAT 2.7V 3.3V 4.8V

VIO 1.62V 1.8V 1.92V

2.3. External Slow Clock Input (SLEEP_CLK)

The external slow clock input SLEEP_CLK must be present at all times. The slow clock is used to maintain timers that synchronize the device to the access point (AP) beacons.

Table 1. External Slow Clock Input Requirements

Characteristics Condition Min. Typ. Max. Unit

Frequency 32.768 KHz

WLAN, BT,

FM_RX

+/-150 Reference Frequency

Accuracy

FM_TX +/- 40

ppm

Input Transmit Time 10% ~ 90% 100 ns



CONFIDENTIAL - 8-

Frequency Duty Cycle 30 50 70 %

Fail Safe Maximum

Value

2.0 V

VIH 0.65xVIO VIO Input Voltage Limits

(Square Wave) VIL 0 0.35xVIO

Vpeak

Input Impedance 1 MΩ

Input Capacitance 5 pF

Rise and fall time 100 ns

Phase noise 1kHz -125 dBc/Hz



CONFIDENTIAL - 9-

3. Power Sequence

3.1. WLAN Power on Sequence

Figure 1. WLAN Power on sequence

The duration of T1 is defined as the time from WL_EN=high until Fref is valid for the SoC. T1 ~ 55ms The duration of T2 depends on:

Operation system Host enumeration for the SDIO/SPI PLL configuration Firmware download Releasing the core from reset Firmware initialization



CONFIDENTIAL - 10-

3.2. Bluetooth Power Up/Down Sequence

Power up requirements: 1. BT_EN must be low 2. VIO must be stable before releasing BT_EN. 3. Slow clock must be stable within 2 ms of BT_EN high.

Figure 2. Bluetooth Power Up/Down sequence

WG7310 indicates completion of power up sequence by asserting RTS low. This occurs up to 100ms after BT_EN goes high.



CONFIDENTIAL - 11-

4. Interface Characteristics

4.1. WLAN SDIO Characteristic

4.1.1. SDIO Read Timing

Figure 3. SDIO Single Block Read

Table 2. SDIO Read Switching characteristics

Parameter Min. Max. Unit

tCR

Delay time, assign relative address/data transfer

mode, CMD command invalid to CMD response

valid

2 64

tID Delay time, identification, CMD command invalid

to CMD response valid 5 5

Clock

Cycles

tCC Delay time, CMD command invalid to CMD

response valid 8 ---

Clock

Cycles

tRC Delay time, CMD response invalid to CMD

command valid 8 ---

Clock

Cycles

tAC Access time, CMD command invalid to SD3-SD3

read data valid 2 ---

Clock

Cycles



CONFIDENTIAL - 12-

4.1.2. SDIO Interface Write Timing

(1) CRC status and busy waveforms are only for data line 0. Data lines 1-3 are N/A. The

busy waveform is optional and may not be present.

Figure 4. SDIO Single Block Write

Table 3. SDIO Write Switching characteristics


td1 Delay time, CMD card response invalid to SD3-SD0

write data valid 2 ---

Clock

Cycles

td2 Delay time, SD3-SD0 write data invalid end to CRC

status valid 2 2

Clock

Cycles

4.1.3. SDIO Clock Timing



CONFIDENTIAL - 13-

Figure 5. SDIO Clock Timing

Table 4. SDIO Timing requirement


fclock Clock frequency, CLK 0 25 MHZ

DC Low/high duty cycle 40 60 %

tWL Pulse duration, CLK low 10 ns

tWH Pulse duration, CLK high 10 ns

tTLH Rise time, CLK 4.3 ns

tTHL Fall time, CLK 3.5 ns

tISU Setup time, input valid before CLK↑ 5 ns

t1H Hold time, input valid after CLK↑ 5 ns

tODLY1 Delay time, CLK↓ to output valid 0 14 ns

TODLY2 Delay time, CLK↓ to output invalid 0 14 ns

4.2. WLAN wSPI Characteristics

The SPI interface signals are shared with the SDIO bus in the WG7310.

4.2.1. SPI Read/Write Timing

Figure 6. SPI Read Timing



CONFIDENTIAL - 14-

Figure 7. SPI Write Timing

Table 5. SPI Read/Write Switching characteristics


tCS Delay time, CS↓ to DIN read/write command

valid 0

16 Clock

Cycles

tCR Delay time, DIN read command invalid to

DOUT/DIN card response valid 1

16 Clock

Cycles

tbusy Fixed busy delay till DOUT data valid 1 7 16/32 Clock

Cycles

tEC Delay time, DOUT data invalid CS↑ 0 16 Clock

Cycles

tDB Data block size 1 16/32 Clock

Cycles

4.2.2. SPI Clock Timing



CONFIDENTIAL - 15-

Figure 8. SPI Clock Timing

Table 6. SPI Timing requirement


fclock Clock frequency, CLK 0 48 MHZ

DC Low/high duty cycle 40 60 %

tWL Pulse duration, CLK low 5 ns

tWH Pulse duration, CLK high 5 ns

tTLH Rise time, CLK 4.3 ns

tTHL Fall time, CLK 3.5 ns

tISU Setup time, input valid before CLK↑ 5 ns

t1H Hold time, input valid after CLK↑ 5 ns

tODLY1 Delay time, CLK↑ to output valid 4 15 ns

TODLY2 Delay time, CLK↓ to output invalid 5 15 ns

4.3. Bluetooth HCI Interface

* STR: Start bit; D0…Dn: Data bits (LSB first); PAR: Parity bit (if parity is used); STP: Stop bit



CONFIDENTIAL - 16-

Table 7. BT HCI Timing characteristics

Characteristics Condition Symbol Min Typ. Max Unit

Baud rate Any rate (1) 37.5 115.2 4000 kbps

Baud rate accuracy Receive/Transmit t5/t7 -2.5to+1.5 %

CTS low to TX_DATA on t3 0 2 us

CTS high to TX_DATA off Hardware flow

control t4 1 Byte

CTS high pulse width t6 1 bit

RTS low to RX_DATA on t1 0 2 us

RTS high to RX_DATA off Interrupt set to

1/4 FIFO t2 16 Bytes

(1) Exception for 19.2MHz: Maximum baud rate = 3.84Mbps.

4.4. Bluetooth PCM Interface

Bluetooth can be setting as master or slave mode. For more stable voice performance, slave mode is recommended.

Table 8. BT PCM Slave mode Timing characteristics

Characteristics Symbol Min Typ. Max Unit

Master clock frequency 1/t1 64 16000 KHz

Clock duty cycle 40 50 60 %



CONFIDENTIAL - 17-

Synchronization clock frequency 1/t3 1/(8xt1) 1/(65535xt1) KHz

Synchronization signal width t1 165545xt1

Setup time for AUD_FSYNC high to AUD_CLK

low t2 5 ns

Hold time from AUD_CLK low to AUD_FSYNC

low t4 8 ns

Setup time for AUD_IN valid to AUD_CLK low t8 5 ns

Hold time from AUD_CLK low to AUD_IN

invalid t9 8 ns

Delay time from AUD_CLK high to AUD_OUT

data valid t5 20 ns

Delay time from AUD_CLK low to last data bit

of AUD_OUT output set to high impedance t7 20 ns



CONFIDENTIAL - 18-

5. Debug Interface

The debug interface helps customers to evaluate the HW/SW features for their application. It also helps to debug during the development stage. The WG7310 module support RS232 signals and UART signals for debug purpose. Connect RS232 and UART signals to the test points for future debug support.

5.1. WLAN RS232 Testing Port

“Direct” serial interface (RS232_TX, RS232_RX) used by WLAN TrioScope software package for WLAN RF performance test, debug and manufacturing application.

5.2. Bluetooth HCI Testing Port

HCI_TX and HCI_RX are used by Bluetooth “HCI Tester” software package for Bluetooth RF performance test, debug and manufacturing application. Please reserve test pads for all test ports debug purpose.



CONFIDENTIAL - 19-

6. Reference Schematic

Title

Size

Do

cumen

t Num

berR

ev

Date:

Sheet of

Nam

eD

ateSign

Designer

App

roval

Chief E

ng.

Eng.M

ang.R

02

WG

7310-to-1V8 H

ost Reference D

esign

WG

7310R01

Cus

tom

22

Mond

ay, June

15, 20

09

VIO_IN: 1.62~1.92V => 1.8V TYP

Slow Clock: 32.768KHz for module boot

and deep sleep

3V3

32.768K XOSC

WL_EN and BT_EN: Please attach a 3.3K ohm

up to VIO_IN if no use

** The six traces from U1 ( module ) to Host must be

treated like a bus. The bus length shall be as short

as possible and every trace length must be the same as

the others. Enough space above 1.5 time trace width or

ground shielding between trace and trace will be benefit

to make sure signal quality, especially for SDIO_CLK

trace. Besides, please remember to keep them away from

the other digital or analog signal traces. To add ground

shielding to around the buses will be good.

** It

's recomm

ended to

insert 0

ohm resis

tors in W

iFi SDIO/

SPI pa

thes and

keep them

close to

WG7310 mo

dule for

test

DS

_SD

IO_D

2R

40R

R0

402D

S_S

PI_C

SX

R5

0RR

0402

DS

_SP

I_DIN

R6

0RR

0402

DS

_SP

I_DO

UT

R7

0RR

0402

DS

_SP

I_CLK

R8

0RR

0402

R10

0RR

0402

R9

0RR

0402

R11

0RR

0402

R12

0RR

0402

R3

0RR

0402

DS

_SD

IO_D

1

TP7

Mus

t be rese

rved for te

stTP

8M

ust be

reserv

ed for test

BD

_HC

I_R

X_1V

8

***** WiFi SDIO/SPI

BD

_HC

I_TX_1V

8

BD

_HC

I_R

TS

_1V8

BD

_HC

I_C

TS

_1V8

WD

_EN

C9

1uF

/NL

C04

02

FA

_RX_A

NT

VIO

_IN

1V8

VIO

_IN

C5

1uF

/NL

C04

02

VB

AT_

IN

TP9

Mus

t be rese

rved for te

stTP

10M

ust be

reserv

ed for test

R2

3.3

KR

0402

VIO

_IN

R1

3.3KR

0402

BD

_HC

I_RT

S

VIO

_IN

BD

_HC

I_CT

S

WG7310-00

U1

WG

7310-00

10x10m

m

GN

D_01

A1

VB

AT_F

EM

_02A

2

BT_F

UN

C2: B

T_WU

/ DC

2DC

_03B

1

GN

D_04

B2

BT

_FU

NC

6: B

T_SD

A_05

C1

BT

_FU

NC

4: BT_TX

_DB

G_06

C2

BT_F

UN

C5: H

OS

T_W

U_07

D1

GN

D_08

D2

GN

D_09

E1

DR

PW

PA

BC

_10E

2

BT

_RF

_AN

T_11

F1

GN

D_12

F2

GN

D_13

G1

DR

PW

PD

ET

_14G

2

WL_T

X_SW

_15H

1

GN

D_16

H2

WL_B

TH_S

W_17

J1

WL

_RX

_SW

_18J2

GN

D_19

K1

VC

C_D

CO

W_20

K2

NC

_C

3_21

L1

GN

D_22

L2

FM

_EN

_23L3

VC

C_

RXW

_24K

3

GN

D_25

L4

BT_E

N_26

K4

WB

_RF

_AN

T_27

L5

GN

D_28

K5

GN

D_29

L6

WL_R

S2

32_RX/ I2

S_M

_SC

L_30

K6

SD

IO_

D1

_31L7

WL_R

S232_

TX/ I2S_M

_SD

A_32

K7

SD

IO_

D2

_33L8

SP

I_CS

X/ SD

IO_

D3

_34K

8

SP

I_DIN

/ SD

IO_C

MD

_35L9

SP

I_DO

UT/ S

DIO

_D

0_36

K9

SP

I_C

LK/ S

DIO

_CLK

_37L1

0

FM

_I2S_

FS

YN

C_38

K10

WL_E

N_39

L11

FM

_SD

A_40

K11

FM

_SC

L_41

J11

FM

_IRQ

_42J1

0

FM

_I2

S_C

LK_43

H11

FM

_I2S

_DI_44

H10

FM

_I2S

_DO

_45G

11

GN

D_46

G10

GN

D_47

F11

SLO

WC

LK_48

F10

FM

_TX_A

NT

_49E

11

GN

D_50

E10

GN

D_51

D11

FM

AU

DR

OU

T_52

D10

FM

_RX_A

NT

_53C

11

GN

D_54

C10

GN

D_55

B11

FM

AU

DLO

UT

_56B

10

FM

AU

DR

IN_57

A11

GN

D_58

A10

FM

AU

DLIN

_59A

9

GN

D_60

B9

GN

D_61

A8

XTALP

_62B

8

XTALM

_63A

7

GN

D_64

B7

GN

D_65

A6

BT_

FU

NC

1: DC

2D

C/ b

tSP

I_CLK

_66B

6

DC

_RE

Q_67

A5

TPS

_D

C2D

C_68

B5

VIO

_69A

4

1V8

_70B

4

VB

AT

_71A

3

VD

D_LD

O_IN

_CLA

SS

1P5

_72B

3

PC

M_A

UD

_CLK

_73D

4

PC

M_A

UD

_IN_74

E4

GN

D_75

F4

WL

_PA

EN

_B_76

G4

GN

D_77

H4

VC

C_A

NA

W_78

H5

VC

C_

TXBW

_79H

6

WL_U

AR

T_D

BG

_80H

7

CLK

_RE

Q_O

UT

_81H

8

WLA

N_IR

Q_82

G8

HC

I_RX/ btS

PI_D

IN_83

F8

HC

I_TX/ b

tSP

I_DO

UT

_84E

8

BT_F

UN

C7: B

T_SC

L_85

D8

HC

I_RT

S/ btS

PI_IR

Q_86

D7

HC

I_CT

S/ btS

PI_C

S_87

D6

PC

M_A

UD

_F

SY

NC

_88D

5

PC

M_A

UD

_OU

T_89

E5

GN

D_90

F5

GN

D_91

G5

GN

D_92

G6

GN

D_93

G7

GN

D_94

F7

GN

D_95

E7

GN

D_96

E6

C6

10uF

/NL

C08

05

3V31V8

3V3

BD

_PC

M_

AU

D_

IN

BD

_PC

M_

AU

D_

FS

YN

C

BD

_PC

M_

AU

D_

CL

K

WiFi Interface: SDIO or SPI

BT Interface: UART, PCM

BD

_PC

M_A

UD

_OU

T

Slow Clock: 32.768KHz from outside

** Boot Conditions

Scheme Brief

Fast Clock: 38.4MHz built-inside

DS

_S

DIO

_D2_

1V8

DS

_S

PI_

CLK

_1V8

DS

_S

PI_

DO

UT_1V

8

DS

_S

DIO

_D1_

1V8

DS

_S

PI_

CS

X_1V8

DS

_S

PI_

DIN

_1V8

C7

NL/2.2u

FC

0402

BD

_TX_D

BG

BD

_HO

ST

_WU

C1

810nFC

AP

1005

BD

_WU

U3

SO

T-23-5

TP

S7

3618D

BV

IN1

GN

D2

EN

3

NR

/FB

4

OU

T5

C17

0.1

uFC

AP

1005

C19

0.1uF

CA

P100

5

VIO

_IN

VB

AT

_IN

JORJIN TECHNOLOGIES INC.

C1

1uF

/NL

C0402

WG7310-00 MODULE

WG7310-to-1V8 Host Reference Design

( Preliminary-subject to change )

C8

1uF

/NL

C0402

3V3

1V8

C10

1uF

/NL

C04

02

1.8V LDO

VB

AT_IN

1V8 FM AUDIO

C16

0.1uF

C04

02

VB

AT_

IN

R19

12KR

0402

R11

81

0KR

0402

OS

C1

KK

3270022

3.2X2.5

MM

PD

1

GN

D2

O/P

3

VD

D4

WD

_RS

232_R

X

WD

_RS

232_TX

C2

1uF

/NL

C0402

C3

1uF

/NL

C0402

1V8 FM I2S

TP1

Res

erved for hos

t CP

U w

hich doesn't sup

port UA

RT w

akeup

TP3

Res

erved for hos

t CP

U w

hich doesn't sup

port UA

RT w

akeup

FD

_I2S_D

IF

D_I2S

_DO

WD

_IRQ

FD

_I2S_C

LK

FD

_I2S_F

SY

NC

TP2

Mus

t be rese

rved for te

st

BD

_EN

FA

_TX_A

NT

AS

_VC

C_A

NA

W

TP4

Mus

t be rese

rved for te

st

MD

_S

LOW

CLK

WD

_UA

RT_D

BG

TP5

Mus

t be rese

rved for te

st

TP6

Mus

t be rese

rved for te

st

FA

_AU

D_IN

_R

FA

_AU

D_IN

_L

FA

_AU

D_O

UT_R

FA

_AU

D_O

UT_L

BD

_HC

I_RX

BD

_HC

I_TX

WB

_RF

_AN

T

DS

_SD

IO_D

2D

S_S

PI_C

SX

DS

_SP

I_DIN

DS

_SP

I_DO

UT

DS

_SP

I_CLK

DS

_SD

IO_D

1

AS

_NC

_C3

AS

_VC

C_TX

BW

AS

_VC

C_R

XW

AS

_VC

C_D

CO

W

FM RF-O

UT

WB

_RF

_AN

T

ANTENNA CIRCUITS

WiFi/BT

RF-I/O

FM RF-I

N

SW

1M

M84

303x3

mm

6

2

1

3

4

5

7

8

C4

1uF

/NL

C0402

C1

310pFC

0402

C1

410pFC

0402

L1NL

L0402

AN

T1

AT801

0-E2R

9HA

A8x

1mm

1

2

FM Interface: UART (with BT together),

I2S, Audio IN/OUT

FA

_RX

_AN

T

FA

_TX_AN

T

C15

1nF

C0402

VBAT_IN: 2.3~4.8V => 3.3V TYP

L2NL/120n

HL04

02

L3100nH

L0402

L412nH

L0402

AN

T3

FM

A010

124

x5mm

1

2

AN

T2

FM

A010

124

x5mm

1

2



CONFIDENTIAL - 20-

Title

Size

Do

cu

me

nt N

um

be

rR

ev

Da

te:

Sh

ee

t of

Nam

eD

ateSign

Designer

Approval

Chief E

ng.

Eng.M

ang.R

02

WG

7310-to-3V3 H

ost Reference D

esign

WG

7310R00

Cu

stom

22

Frida

y, J

une

12

, 20

09

VIO_IN: 1.62~1.92V => 1.8V TYP

Slow Clock: 32.768KHz for module boot

and deep sleep

3V3

32.768K XOSC

WL_EN and BT_EN: Please attach a 3.3K ohm

up to VIO_IN if no use

TWL1200 1V8-to-3V3 LEVEL SHIFTER

WB

_R

F_

AN

T

DS

_SD

IO_D

2R

40

RR

04

02D

S_S

PI_

CS

XR

50

RR

04

02D

S_S

PI_

DIN

R6

0R

R0

402

DS

_SP

I_D

OU

TR

70

RR

04

02D

S_S

PI_

CLK

R8

0R

R0

402

R9

0R

R0

402

R1

00

RR

04

02

R1

10

RR

04

02

R1

20

RR

04

02

R3

0R

R0

402

DS

_SD

IO_D

1

DS

_SD

IO_D

2_

1V

8

DS

_SD

IO_D

1_

1V

8

DS

_SP

I_C

LK

_1

V8

DS

_SP

I_D

OU

T_

1V8

DS

_SP

I_D

IN_

1V

8D

S_S

PI_

CS

X_

1V

8

TP

7M

us

t be

rese

rve

d fo

r tes

tT

P8

Mu

st b

e re

serv

ed

for te

st

BD

_HC

I_R

X_

1V

8

** It's recommended to insert 0 ohm resistors in WiFi SDIO/SPI pathes and keep them close to WG7310 module for test

***** WiFi SDIO/SPI

BD

_HC

I_TX

_1

V8

** The six traces from U1 ( module ) to U2 ( level shifter )

and from U2 to Host must be treated like two buses. The

bus length shall be as short as possible and every trace

length must be the same as the others. Enough space above

1.5 time trace width or ground shielding between trace

and trace will be benefit to make sure signal quality,

especially for SDIO_CLK trace. Besides, please remember

to keep them away from the other digital or analog signal

traces. To add ground shielding to around the buses will

be good.

BD

_HC

I_R

TS

_1

V8

BD

_HC

I_C

TS

_1

V8

R2

00

R/N

LR

040

2W

D_

IRQ

** SDIO lines should be held high by the host

WD

_E

N

** SDIO_D1 and SDIO_D2 shall be connected to GND if using SPI host interface

R1

5N

LR

040

2

R1

40

R/N

LR

040

2

R1

30

R/N

LR

040

2

C9

1uF

/NL

C04

02

FA

_RX

_A

NT

WD

_E

N

BD

_EN

VIO

_IN

1V8

MD

_SL

OW

CL

K

LS

U2

TW

L1

20

04

.1x4

.1m

m

VC

CA

C4

VC

CA

D4

SD

IO_

DA

TA

0_A

B2

SD

IO_

DA

TA

1_A

C2

SD

IO_

DA

TA

2_A

C1

SD

IO_

DA

TA

3_A

B1

SD

IO_C

MD

_AA

2

SD

IO_

CL

K_A

A1

WL

AN

_E

NA

BL

E_A

D1

WL

AN

_IR

Q_A

D2

CL

K_R

EQ

_AE

1

BT

_E

NA

BL

E_A

E2

BT

_U

AR

T_

RX

_AG

1

BT_

UA

RT_

CT

S_A

F1

BT

_U

AR

T_

TX

_AG

2

BT_

UA

RT_

RT

S_A

F2

PC

M_

AU

DIO

_IN

_AF

3

PC

M_A

UD

IO_

CL

K_A

A3

PC

M_

AU

DIO

_F

_S

YN

C_A

B3

PC

M_

AU

D_

OU

T_A

G3

SL

OW

_C

LK

_AG

4

AU

D_

DIR

A4

VC

CB

C5

VC

CB

D5

SP

I_D

OU

T/ S

DIO

_D

ATA

0_

BB

6

SD

IO_

DA

TA

1_

BC

6

SD

IO_

DA

TA

2_

BC

7

SP

I_C

SX/ S

DIO

_D

AT

A3

_B

B7

SP

I_D

IN/ S

DIO

_C

MD

_BA

6

WL

AN

_E

NA

BL

E_

BD

6

WL

AN

_IR

Q_

BD

7

SP

I_C

LK

/ SD

IO_

CL

K_B

A7

CLK

_R

EQ

_B

E7

BT_

EN

AB

LE

_B

E6

BT_

UA

RT_

RX

_B

G7

BT_

UA

RT_

CT

S_B

F7

BT_

UA

RT_

TX

_B

G6

PC

M_

AU

DIO

_IN

_B

F5

PC

M_

AU

DIO

_C

LK

_B

A5

PC

M_

AU

DIO

_F

_S

YN

C_

BB

5

PC

M_

AU

D_

OU

T_B

G5

SLO

W_

CL

K_

BF

4

OE

B4

BT_

UA

RT_

RT

S_B

F6

GNDD3

GNDE4

GNDE5

GNDE3

VIO

_IN

C5

1u

F/N

LC

04

02

VB

AT

_IN

TP

9M

us

t be

rese

rve

d fo

r tes

tT

P1

0M

us

t be

rese

rve

d fo

r tes

t

R2

3.3

KR

040

2

VIO

_IN

R1

3.3

KR

04

02

BD

_HC

I_R

TS

VIO

_IN

BD

_HC

I_C

TS

WG7310-00

U1

WG

73

10

-001

0x1

0m

m

GN

D_

01

A1

VB

AT

_F

EM

_0

2A

2

BT_

FU

NC

2: B

T_W

U/ D

C2

DC

_0

3B

1

GN

D_

04

B2

BT

_F

UN

C6

: BT

_S

DA

_0

5C

1

BT

_FU

NC

4: BT

_TX

_D

BG

_0

6C

2

BT_

FU

NC

5: H

OS

T_

WU

_0

7D

1

GN

D_

08

D2

GN

D_

09

E1

DR

PW

PA

BC

_1

0E

2

BT

_R

F_

AN

T_1

1F

1

GN

D_

12

F2

GN

D_

13

G1

DR

PW

PD

ET

_1

4G

2

WL

_TX

_S

W_

15

H1

GN

D_

16

H2

WL

_B

TH

_S

W_

17

J1

WL

_RX

_S

W_

18

J2

GN

D_

19

K1

VC

C_D

CO

W_

20

K2

NC

_C

3_

21

L1

GN

D_

22

L2

FM

_E

N_

23

L3

VC

C_

RX

W_

24

K3

GN

D_

25

L4

BT

_E

N_

26

K4

WB

_R

F_

AN

T_

27

L5

GN

D_

28

K5

GN

D_

29

L6

WL

_R

S2

32

_R

X/ I2

S_M

_S

CL

_3

0K

6

SD

IO_

D1

_3

1L

7

WL

_R

S2

32

_TX

/ I2S

_M_

SD

A_

32

K7

SD

IO_

D2

_3

3L

8

SP

I_C

SX

/ SD

IO_

D3_

34

K8

SP

I_D

IN/ S

DIO

_C

MD

_3

5L

9

SP

I_D

OU

T/ S

DIO

_D

0_

36

K9

SP

I_C

LK/ S

DIO

_C

LK

_3

7L

10

FM

_I2

S_F

SY

NC

_3

8K

10

WL

_E

N_

39

L1

1

FM

_S

DA

_4

0K

11

FM

_S

CL_

41

J1

1

FM

_IR

Q_

42

J1

0

FM

_I2

S_

CLK

_4

3H

11

FM

_I2S

_D

I_4

4H

10

FM

_I2S

_D

O_

45

G1

1

GN

D_

46

G1

0

GN

D_

47

F1

1

SL

OW

CL

K_

48

F1

0

FM

_TX

_A

NT

_4

9E

11

GN

D_

50

E1

0

GN

D_

51

D1

1

FM

AU

DR

OU

T_5

2D

10

FM

_R

X_

AN

T_

53

C1

1

GN

D_

54

C1

0

GN

D_

55

B1

1

FM

AU

DL

OU

T_5

6B

10

FM

AU

DR

IN_

57

A1

1

GN

D_

58

A1

0

FM

AU

DL

IN_

59

A9

GN

D_

60

B9

GN

D_

61

A8

XT

AL

P_

62

B8

XT

AL

M_

63

A7

GN

D_

64

B7

GN

D_

65

A6

BT

_F

UN

C1

: DC

2D

C/ b

tSP

I_C

LK

_6

6B

6

DC

_R

EQ

_6

7A

5

TP

S_D

C2

DC

_6

8B

5

VIO

_6

9A

4

1V

8_7

0B

4

VB

AT

_7

1A

3

VD

D_

LD

O_IN

_C

LAS

S1

P5

_7

2B

3

PC

M_

AU

D_

CL

K_

73

D4

PC

M_

AU

D_

IN_

74

E4

GN

D_

75

F4

WL

_P

AE

N_B

_7

6G

4

GN

D_

77

H4

VC

C_

AN

AW

_7

8H

5

VC

C_

TX

BW

_7

9H

6

WL

_U

AR

T_

DB

G_

80

H7

CL

K_

RE

Q_

OU

T_

81

H8

WL

AN

_IR

Q_

82

G8

HC

I_R

X/ b

tSP

I_D

IN_

83

F8

HC

I_T

X/ btS

PI_

DO

UT

_8

4E

8

BT

_F

UN

C7

: BT

_S

CL

_8

5D

8

HC

I_R

TS/ b

tSP

I_IR

Q_

86

D7

HC

I_C

TS

/ btS

PI_

CS

_8

7D

6

PC

M_A

UD

_FS

YN

C_

88

D5

PC

M_

AU

D_

OU

T_

89

E5

GN

D_

90

F5

GN

D_

91

G5

GN

D_

92

G6

GN

D_

93

G7

GN

D_

94

F7

GN

D_

95

E7

GN

D_

96

E6

C6

10

uF

/NL

C0

805

FM RF-OUT

FM RF-IN

VB

AT

_IN

DS

_SD

IO_D

2_

1V

8D

S_S

DIO

_D1

_1

V8

BD

_H

CI_

CT

S_

1V

8

DS

_SP

I_D

OU

T_

1V8

WD

_IR

Q_

1V8

WD

_E

N_

1V8

DS

_SP

I_C

LK

_1

V8

DS

_SP

I_D

IN_

1V

8D

S_S

PI_

CS

X_

1V

8

BD

_E

N_

1V

8

BD

_P

CM

_A

UD

_IN

BD

_H

CI_

RT

S_

1V

8B

D_

HC

I_T

X_

1V8

BD

_H

CI_

RX

_1V

8

MD

_S

LOW

CLK

_1

V8

BD

_P

CM

_A

UD

_O

UT

BD

_P

CM

_A

UD

_F

SY

NC

BD

_P

CM

_A

UD

_C

LK

** AUD_DIR = R26 NL, R27 0 ohm --> AUD_FSYNC and AUD_CLK from WG7310 to Host; AUD_DIR = R26 0 ohm, R27 NL --> AUD_FSYNC and AUD_CLK from Host to WG7310

3V3

WiFi/BT RF-I/O

C11

0.1

uF

C0

402

3V31V8

1V83V3

VB

AT_

IN

BD

_PC

M_

AU

D_

IN

BD

_PC

M_

AU

D_

FS

YN

C

BD

_PC

M_

AU

D_

CL

K

WiFi Interface: SDIO or SPI

BT Interface: UART, PCM

VIO

_IN

BD

_PC

M_

AU

D_

OU

T

Slow Clock: 32.768KHz from outside

** Boot Conditions

Scheme Brief

Fast Clock: 38.4MHz built-inside

DS

_S

DIO

_D

2_

3V3

DS

_S

PI_C

LK

_3V

3

WD

_E

N_3

V3

WD

_IR

Q_

3V

3

DS

_S

PI_D

OU

T_3

V3

BD

_H

CI_

CT

S_3

V3

DS

_S

DIO

_D

1_

3V3

BD

_H

CI_

RX

_3V

3

BD

_H

CI_

TX

_3V

3B

D_

HC

I_R

TS

_3V

3

DS

_S

PI_C

SX

_3V

3D

S_

SP

I_DIN

_3V

3

BD

_P

CM

_A

UD

_F

SY

NC

_3

V3

BD

_P

CM

_A

UD

_O

UT

_3V

3

MD

_S

LO

WC

LK

_3

V3

BD

_E

N_3

V3

BD

_P

CM

_A

UD

_IN

_3V

3B

D_

PC

M_

AU

D_

CL

K_3

V3

C7

NL/2

.2u

FC

040

2

C1

20.1

uF

C0

40

2

BD

_TX

_D

BG

BD

_HO

ST

_WU

C1

81

0n

FC

AP

100

5

BD

_WU

U3

SO

T-2

3-5T

PS

73

618

DB

V

IN1

GN

D2

EN

3

NR

/FB

4

OU

T5

C1

70.1

uF

CA

P1

005

C1

90

.1u

FC

AP

10

05

VIO

_IN

VB

AT

_IN

JORJIN TECHNOLOGIES INC.

C1

1uF

/NL

C0

402

WG7310-00 MODULE

R1

6N

L/0

RR

04

02

R1

70

RR

04

02

WG7310-to-3V3 Host Reference Design

( Preliminary-subject to change )

C8

1uF

/NL

C0

402

3V31V8

C1

01u

F/N

LC

040

2

1.8V LDO

VB

AT

_IN

ANTENNA CIRCUITS

3V3 I/O to HOST

1V8 FM AUDIO

C1

60

.1u

FC

04

02

VB

AT

_IN

R19

12K

R04

02

R1

18

10K

R0

40

2

OS

C1

KK

327

00

22

3.2

X2.5

MM

PD

1

GN

D2

O/P

3

VD

D4

WD

_R

S23

2_

RX

WD

_R

S23

2_

TX

C2

1uF

/NL

C0

402

C3

1uF

/NL

C0

402

1V8 FM I2S

TP

1R

es

erve

d for h

os

t CP

U w

hic

h d

oes

n't su

pp

ort U

AR

T wa

ke

up

TP

3R

es

erve

d for h

os

t CP

U w

hic

h d

oes

n't su

pp

ort U

AR

T wa

ke

up

SW

1M

M8

43

03

x3m

m

6

2

1

3

4

5

7

8

FD

_I2S

_D

IF

D_I2

S_

DO

WD

_IR

Q

FD

_I2S

_C

LK

FD

_I2S

_F

SY

NC

TP

2M

us

t be

rese

rve

d fo

r tes

t

BD

_EN

FA

_TX

_A

NT

AS

_VC

C_

AN

AW

TP

4M

us

t be

rese

rve

d fo

r tes

t

MD

_SL

OW

CL

K

WD

_U

AR

T_

DB

G

TP

5M

us

t be

rese

rve

d fo

r tes

t

TP

6M

us

t be

rese

rve

d fo

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FM Interface: UART (with BT together),

I2S, Audio IN/OUT

VBAT_IN: 2.3~4.8V => 3.3V TYP



CONFIDENTIAL - 21-

7. Module Mechanical Outline

WG7310 Bottom View Side View

WG7310 Bottom View

‧ Pin array = 11x11 ‧ Pin number = 96 pins ‧ Bump pitch = 0.85mm ‧ Bump diameter = 0.5mm



CONFIDENTIAL - 22-

8. Layout Recommendation

8.1. Recommended Bump Pad Design *

Figure 9. Recommended Bump Pad Design

COMMENT: SMD = Solder Mask Define S/M= Solder Mask

B/P= Bump Pad

8.2. Recommended Stencil Design *

The bump pad size, it’s solder mask opening and the relevant stencil via diameter described in Section 8.1 and Section 8.2 shall be followed completely otherwise the module mounting yield rate couldn’t be insured. The recommended stencil via diameter is 570 um.

8.3. Recommended Trace Layout

Digital Signals Layout SDIO signals traces (CLK, CMD, D0, D1, D2 and D3) should

be routed in parallel to each other and as short as possible. Every trace length must be the same as the others. Enough space above 1.5 time trace width or ground shielding between trace and trace will be benefit to make sure signal quality, especially for SDIO_CLK trace. Besides, to keep them away from the other digital or analog signal traces and to add ground plane around them are also recommended strongly.



CONFIDENTIAL - 23-

SDIO/SPI Clock, Audio Clock (PCM_AUD_CLK), FM I2S Clock

(FM_I2S_CLK), FM I2C Clock (FM_SCL), these digital clock signals are a source of noise. Keep the traces of these signals as short as possible. Whenever possible, maintain a clearance around them.

RF Trace & Antenna

WB_RF_ANT and FM_RX_ANT are required as 50 ohm traces, and FM_TX_ANT is as 75ohm one. If 75 ohm is difficult to be achieved, FM_TX_ANT could be designed as 50 ohm also but the trace length between module to FM_TX_ANT matching circuit is recommended as short as possible.

Recommended 50ohm trace design for PCB layout

Height Between L1 and L2 (H): 10.0 mil

Trace (W): 14.3 mil

(W1): 14.3 mil

Thickness (T): 2.1 mil

Separation (S): 10.0 mil

Dielectric (Er): 4.3

Move all the high-speed traces and components far away from the antenna.

Check ANT vendor for the layout guideline and clearance. Matching circuit layout should be as following figure.



CONFIDENTIAL - 24-

Power Trace

Power trace for VBAT should be 40mil wide. 1.8V trace should be 18mil wide.

Ground

Having a complete Ground and more GND vias under module in layer1 for system stable and thermal dissipation as following figure.

Have a complete Ground pour in layer 2 for thermal dissipation.

Increase the GND pour in the 1st layer, move all the traces from the 1st layer to the inner layers if possible.

Move GND vias close to the pad.

Slow Clock FM RF module uses the 32-kHz clock, it is extremely

important that the slow-clock trace not be routed next to any digital signals.

The slow clock trace should not be routed above or below digital signals on other layers.



CONFIDENTIAL - 25-

9. SMT and Baking Recommendation

9.1. Baking Recommendation

Baking condition： - Follow MSL Level 4 to do baking process. - After bag is opened, devices that will be subjected to reflow

solder or other high temperature process must be a) Mounted within 72 hours of factory conditions <30°C/60% RH,

or b) Stored at <10% RH.

- Devices require bake, before mounting, if Humidity Indicator Card reads >10%

If baking is required, Devices may be baked for 8 hrs at 125 °C.

9.2. SMT Recommendation

Recommended Reflow profile：



CONFIDENTIAL - 26-

No. Item Temperature (°C) Time (sec) 1 Pre-heat D1: 140 ~ D2: 200 T1: 80 ~ 120

2 Soldering D2: = 220 T2: 60 +/- 10

3 Peak-Temp. D3: 250 °C max

Note: (1) Reflow soldering is recommended two times maximum.

(2) Add Nitrogen while Reflow process： SMT solder ability will be better.

Stencil thickness： 0.13~ 0.15 mm (Recommended) Soldering paste (without Pb)： Recommended SENJU

N705-GRN3360-K2-V can get better soldering effects.



CONFIDENTIAL - 27-

10. History Change

Revision Date Description R 0.1 2009/05/26 New release

R 0.2 2009/07/13 Modify Storage/Operating Temperature Range, Pin out

description & Reference Schematic

R 0.3 2009/08/10 Update Section 6 Reference Schematic, Section 7

Mechanical Figure for Pin1 indicator, Section 8.2

Recommended Stencil Design, Section 9 Baking Condition.

WG7310-00 WLAN+BT+FM Module TI WL1271 solution · 1. WG7310 Module Description WG7310, a WLAN ,...

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