Welcome to the presentation of the STM32L4+ Direct Memory Access controller (DMA). It covers the main features of the DMA controller module, enhanced by the new DMAMUX module.

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The DMA Controller embedded in STM32L4+ is similar to the one implemented in the STM32L4, but with an additional DMAMUX.

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The main feature of the DMA is to off-load the CPU for data transfers, from any memory-mapped source towards any memory-mapped destination.(For more information about the memory mapping and specifically addressable space for each DMA controller, refer to the L4+ AHB bus interconnect.)L4+ DMA features:• 2 DMA controllers. For each DMA controller it is possible

to do:• Programmable block transfers with 7 concurrent

channels, (each of which are independently configurable)

• Programmable channel-based priority• Data transfers via the AHB master port

(connected to the bus matrix)• There is also a DMA request multiplexer (DMAMUX) with

• Programmable selection of the source of any DMA request : from a peripheral in DMA mode or from

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a trigger• Event-triggered & synchronized DMA request

generation.

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There are 89 peripheral requests and 4 DMAMUX generated requests.There are 26 triggers and synchronization inputs, and among these 26, there are 4 DMAMUX generated events.There are 14 DMA channels/requests.

Each channel of the DMA controller is independently configurable:• A channel can be assigned to a DMA hardware request

from a peripheral in peripheral-to-memory, or memory-to-peripheral data transfers.

• Alternatively, a channel is assigned to a software request in memory-to-memory data transfers.

• A channel is programmed with a priority level.• A channel is programmed for a number of data transfers

at a block level.The software can control a channel via the separated interrupts and/or flags upon programmable events such as a block transfer complete, and/or a half-block transfer complete, and/or a transfer error.

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A channel is programmed for a number of data transfers at a block level with• Independent source and destination data size• Independent source and destination start address• Independent source and destination address increment

(either contiguously incremented or at a fixed address)• Programmable amount of data to be transferred within a

block.

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In Memory-to-memory mode, a block transfer starts as soon as the channel is enabled (there is no hardware request).

Whereas in Peripheral-to-memory, and memory-to-peripheral modes

• A block transfer starts as soon as both 1) the channel is enabled and 2) the peripheral sends a DMA hardware request

• A DMA hardware request identifies a (single) DMA data transfer

• Each DMA hardware request is paced and granted by the DMA when each data is successfully transferred to the destination

In any mode, channels arbitration is reassessed between every data transfer.

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DMAMUX is a programmable multiplexer/router of DMA requests.

The mapping of DMA requests from any peripheral to DMA channels is programmable via independent DMAMUX channels.

Additionally, up to 4 DMA requests may be internally generated by the DMAMUX following an input trigger signal.

Any generated DMA request is independently programmable in terms of the trigger selection, the edge detection, and the number of generated DMA requests upon each trigger event.

The trigger source may be EXTI0 to EXTI15, or LPTIM_OUT, DSI tearing effect, DSI end of refresh, DMA2D end of transfer, LTDC line interrupt, or any of the 4 generated DMAMUX events.

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In synchronization mode, any DMAMUX output DMA request can be synchronized with respect to a programmed and selected synchronization input.

The synchronization edge detection, and the number of transmitted DMA requests upon the synchronizer event are also programmable.

As well as managing DMA requests, DMAMUX can also generate programmable DMAMUX events which may be looped back as trigger inputs. For example this would apply to transfers chaining between different DMA channels.

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In normal/unsynchronized mode (SE=0):DMAMUX is routing one selected/input DMA request to one of its output DMA requests.On top of that, DMAMUX may be configured for generating an event (EGE=1).An event is generated every NBREQ+1 DMA requests (here NBREQ=3)

In synchronization mode (SE=1):DMAMUX is configured to synchronize a DMA (block) transfer request upon the reception of each hardware synchronization event.The block data size is programmable, via the programmed number of DMA input requests (equal to NBREQ+1) to be transmitted between two occurrences of the synchronization input.On top of that, DMAMUX can be enabled for generating an event every NBREQ+1 DMA requests.

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If there is a new synchronization occurrence before the block transfer has been completed (as paced and granted by the DMA), there is a DMAMUX synchronization overrun flag and a raised interrupt.

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Each DMA channel can notify software with an interrupt, being caused by any of the 4 possible events:• Half-block transfer completion• Block Transfer completion• Transfer error• Any of the 3 above events (aka global)

DMAMUX can generate one interrupt, caused from an overrun from any of the configured channel(s). Root cause may be :• Either a trigger overrun before the internally

generated number of DMA requests have been issued and completed

• Or/and a synchronization overrun before the number of DMA requests - external or internal requests - have been issued and completed.

This table summarizes the state of DMA versus the power state machine.