WS8B-1 WORKSHOP 8B TENSION COUPON NAS120, Workshop 8B, November 2003.
Week 8b - University of California, Berkeleyee42/sp05/pdf/week8b.pdf · Hambley Ch. 12.1. EECS42,...
Transcript of Week 8b - University of California, Berkeleyee42/sp05/pdf/week8b.pdf · Hambley Ch. 12.1. EECS42,...
Week 8b, Slide 1EECS42, Spring 2005 Prof. White
Week 8b
OUTLINEUsing pn-diodes to isolate transistors in an ICThe metal-oxide-field-effect transistor (MOSFET)
Structure of the MOSFETThe MOSFET as a controlled resistancePinch-off and current saturation in the MOSFETChannel-length modulationVelocity saturation in a short-channel MOSFET
ReadingRabaey et al. Ch. 3.3.1-3.3.2Hambley Ch. 12.1
Week 8b, Slide 2EECS42, Spring 2005 Prof. White
• The basic building block in digital ICs is the MOS transistor, whose structure contains reverse-biased diodes.– pn junctions are important for electrical isolation of
transistors located next to each other at the surface of a Si wafer.
– The junction capacitance of these diodes can limit the performance (operating speed) of digital circuits
Why are pn Junctions Important for ICs?
Week 8b, Slide 3EECS42, Spring 2005 Prof. White
p-type Si
n n n n n
regions of n-type Si
No current flows if voltages are applied between n-type regions, because two pn junctions are “back-to-back”
n-regionn-region
p-region=> n-type regions isolated in p-type substrate and vice versa
Device Isolation using pn Junctions
a b
ba
Week 8b, Slide 4EECS42, Spring 2005 Prof. White
Figure 0.1 Example of a densely populated integrated circuit –the DRAM
Column Drivers and Sense AmplifiersColumn AddressDecoder/Selector
Row
Add
ress
Dec
oder
W ord Line
Bit
Line
Dynamic Random-Access Memory (DRAM)
Week 8b, Slide 5EECS42, Spring 2005 Prof. White
p-type Si
n n
Transistor A
n n
Transistor B
We can build large circuits consisting of many transistors without worrying about current flow between devices. The p-n junctions isolate the transistors because there is always at least one reverse-biased p-n junction in every potential current path.
Week 8b, Slide 6EECS42, Spring 2005 Prof. White
Modern Field Effect Transistor (FET)
• An electric field is applied normal to the surface of the semiconductor (by applying a voltage to an overlying “gate” electrode), to modulate the conductance of the semiconductor
→ Modulate drift current flowing between 2 contacts (“source” and “drain”) by varying the voltage on the “gate” electrode
Metal-oxide-semiconductor(MOS) FET:
Week 8b, Slide 7EECS42, Spring 2005 Prof. White
• A GATE electrode is placed above (electrically insulated from) the silicon surface, and is used to control the resistance between the SOURCE and DRAIN regions
• NMOS: N-channel Metal Oxide Semiconductor
np-type silicon
oxide insulator n
L
• L = channel length
“Metal” (heavily doped poly-Si)
W• W = channel width
SOURCE
MOSFET
DRAIN
GATE
Week 8b, Slide 8EECS42, Spring 2005 Prof. White
• Without a gate-to-source voltage applied, no current can flow between the source and drain regions.
• Above a certain gate-to-source voltage (threshold voltage VT), a conducting layer of mobile electrons is formed at the Si surface beneath the oxide. These electrons can carry current between the source and drain.
N-channel MOSFET
n
p
oxide insulatorgate
n
DrainSource
Gate
ID
IG
IS
Week 8b, Slide 9EECS42, Spring 2005 Prof. White
N-channel vs. P-channel MOSFETs
• For current to flow, VGS > VT
• Enhancement mode: VT > 0
• Depletion mode: VT < 0– Transistor is ON when VG=0V
p-type Si
n+ poly-Si
n-type Si
p+ poly-Si
NMOS PMOS
n+ n+ p+ p+
• For current to flow, VGS < VT
• Enhancement mode: VT < 0
• Depletion mode: VT > 0– Transistor is ON when VG=0V
(“n+” denotes very heavily doped n-type material; “p+” denotes very heavily doped p-type material)
Week 8b, Slide 10EECS42, Spring 2005 Prof. White
MOSFET Circuit Symbols
p-type Si
n+ poly-Si
NMOS
n+ n+
n-type Si
p+ poly-Si
PMOS
p+ p+
G G
G G
S
SS
S
Body
Body
Week 8b, Slide 11EECS42, Spring 2005 Prof. White
Figure 0.1 Schematic symbol and water model for ap-channel MOSFET
Gate
Source
Drain
Flexible
Spring
membrane
Source
Gate
Drain
Water Model for P-channel MOSFET
Week 8b, Slide 12EECS42, Spring 2005 Prof. White
• The voltage applied to the GATE terminal determines whether current can flow between the SOURCE & DRAIN terminals.– For an n-channel MOSFET, the SOURCE is biased at a lower
potential (often 0 V) than the DRAIN(Electrons flow from SOURCE to DRAIN when VG > VT)
– For a p-channel MOSFET, the SOURCE is biased at a higherpotential (often the supply voltage VDD) than the DRAIN
(Holes flow from SOURCE to DRAIN when VG < VT )
• The BODY terminal is usually connected to a fixed potential.– For an n-channel MOSFET, the BODY is connected to 0 V– For a p-channel MOSFET, the BODY is connected to VDD
MOSFET Terminals
Week 8b, Slide 13EECS42, Spring 2005 Prof. White
VGS
S
semiconductoroxide
GVDS
+− +−
D
always zero!
IG
VGS
The gate is insulated from the semiconductor, so there is no significant steady gate current.
IG
NMOSFET IG vs. VGS CharacteristicConsider the current IG (flowing into G) versus VGS :
Week 8b, Slide 14EECS42, Spring 2005 Prof. White
The MOSFET as a Controlled Resistor• The MOSFET behaves as a resistor when VDS is low:
– Drain current ID increases linearly with VDS
– Resistance RDS between SOURCE & DRAIN depends on VGS• RDS is lowered as VGS increases above VT
NMOSFET Example:
ID
IDS = 0 if VGS < VT
VDS
VGS = 1 V > VT
VGS = 2 V
Inversion charge density Qi(x) = -Cox[VGS-VT-V(x)]where Cox ≡ εox / tox
oxide thickness ≡ tox
Week 8b, Slide 15EECS42, Spring 2005 Prof. White
Sheet Resistance Revisited
nnns Qntqtt
Rμμσ
ρ 111====
Consider a sample of n-type semiconductor:
where Qn is the charge per unit area
V+ _
L
tW
I
homogeneously doped sample
Week 8b, Slide 16EECS42, Spring 2005 Prof. White
VGS
S
semiconductoroxide
GVDS
ID
+− +−
D
ID
zero if VGS < VT
VDS
Next consider ID (flowing into D) versus VDS, as VGS is varied:
Below “threshold” (VGS < VT):no charge no conduction
Above threshold (VGS > VT): “inversion layer” of electrons appears, so conduction between S and D is possible
VGS > VT
NMOSFET ID vs. VDS Characteristics
Week 8b, Slide 17EECS42, Spring 2005 Prof. White
We can make RDS low by• applying a large “gate drive” (VGS − VT)• making W large and/or L small
MOSFET as a Controlled Resistor (cont’d)
)2
(
//)/(DS
TGSoxnin
sDS VVVC
WLQWLWLRR
−−===
μμ
DS
DSD R
VI =
DSDS
TGSoxnD VVVVLWCI )
2( −−= μ
average value of V(x)
Week 8b, Slide 18EECS42, Spring 2005 Prof. White
VGS > VT :
⎟⎠⎞
⎜⎝⎛=
=
=
LVWQ
WQ
vWQI
DSninv
ninv
invD
E
μ
μ
depletion regionVGS < VT:(no inversion layerat surface)
Average electron velocity v is proportional to lateral electric field E
Charge in an N-Channel MOSFET
VDS ≈ 0
VDS > 0(small)
Week 8b, Slide 19EECS42, Spring 2005 Prof. White
VDS = VGS–VT Inversion-layeris “pinched-off”at the drain end
As VDS increases above VGS–VT ≡ VDSAT, the length of the “pinch-off” region ΔL increases:• “extra” voltage (VDS – VDsat) is dropped across the distance ΔL• the voltage dropped across the inversion-layer “resistor” remains VDsat
⇒ the drain current ID saturates
VGS > VT :
VDS > VGS–VT
What Happens at Larger VDS?
Note: Electrons are swept into the drain by the E-field when they enter the pinch-off region.
Week 8b, Slide 20EECS42, Spring 2005 Prof. White
• As VDS increases, the inversion-layer charge density at the drain end of the channel is reduced; therefore, IDdoes not increase linearly with VDS.
• When VDS reaches VGS − VT, the channel is “pinched off”at the drain end, and ID saturates (i.e. it does not increase with further increases in VDS).
Summary of ID vs. VDS
n+n+
S
G
VGS
D
VDS > VGS - VT
VGS - VT+-
pinch-off region
+–
( )2
2 TGSoxnDSAT VVL
WCI −= μ
Week 8b, Slide 21EECS42, Spring 2005 Prof. White
ID vs. VDS Characteristics
The MOSFET ID-VDS curve consists of two regions:1) Resistive or “Triode” Region: 0 < VDS < VGS − VT
2) Saturation Region: VDS > VGS − VT
( )
oxnn
TGSn
DSAT
Ck
VVL
WkI
μ=′
−′
=
where
2
2
oxnn
DSDS
TGSnD
Ck
VVVVLWkI
μ=′
⎥⎦⎤
⎢⎣⎡ −−′=
where2
process transconductance parameter
“CUTOFF” region: VG < VT
Week 8b, Slide 22EECS42, Spring 2005 Prof. White
If L is small, the effect of ΔL to reduce the inversion-layer “resistor” length is significant
→ ID increases noticeably with ΔL (i.e. with VDS)
Channel-Length Modulation
ID
VDS
ID = ID′(1 + λVDS)
λ is the slope
ID′ is the intercept
Week 8b, Slide 23EECS42, Spring 2005 Prof. White
At high electric fields, the average velocity of carriers is NOT proportional to the field; it saturates at ~107 cm/sec for both electrons and holes:
Velocity Saturation
Week 8b, Slide 24EECS42, Spring 2005 Prof. White
Current Saturation in Modern MOSFETs• In digital ICs, we typically use transistors with the
shortest possible gate-length for high-speed operation.
• In a very short-channel MOSFET, ID saturates because the carrier velocity is limited to ~107 cm/sec
v is not proportional to E, due to velocity saturation
Week 8b, Slide 25EECS42, Spring 2005 Prof. White
1. ID is lower than that predicted by the mobility model
2. ID increases linearly with VGS − VT rather than quadratically in the saturation region
Consequences of Velocity Saturation
satn
DSAT
satDSAT
TGSoxDSAT
vLV
vVVVWCI
μ=
⎥⎦⎤
⎢⎣⎡ −−=
where
2
Week 8b, Slide 26EECS42, Spring 2005 Prof. White
P-Channel MOSFET ID vs. VDS
• As compared to an n-channel MOSFET, the signs of all the voltages and the currents are reversed:
Note that the effectsof velocity saturationare less pronouncedthan for an NMOSFET.Why is this the case?
Short-channel PMOSFET I-V