Week 6.1Spring 2005 14:332:331 Computer Architecture and Assembly Language Spring 2005 Week 6...

Week 6.1 Spring 2005

14:332:331Computer Architecture and Assembly Language

Spring 2005

Week 6

[Adapted from Dave Patterson’s UCB CS152 slides and

Mary Jane Irwin’s PSU CSE331 slides]


Review: Entity-Architecture Features

Entity defines externally visible characteristics Ports: channels of communication

Architecture defines the internal behavior or structure

Declaration of internal signals Description of behavior

- concurrent behavioral description: collection of CSA’s- process behavioral description: CSAs and variable

assignment statements within a process description- structural description: system described in terms of the

interconnections of its components

Design Entity-Architecture == Hardware Component

Entity == External Characteristics

Architecture (Body ) == Internal Behavior or Structure


Review: Model of Execution CSA’s are executed concurrently - textural order of

the statements is irrelevant to the correct operation

VHDL programmer specifies events - with CSA’s delays - with CSA’s with delay annotation concurrency - by having a distinct CSA for each signal


Review: Signal Resolution Resolving values of pairs of std_logic type signals

When a signal has multiple drivers (e.g., a bus), the value of the resulting signal is determined by a resolution function

Uunknown

Xforcing

unknown

0 1 Zhigh

imped

Wweak

unknown

L weak 0

Hweak 1

-don’t care

U U U U U U U U U U

X U X X X X X X X X

0 U X 0 X 0 0 0 0 X

1 U X X 1 1 1 1 1 X

Z U X 0 1 Z W L H X

W U X 0 1 W W W W X

L U X 0 1 L W L W X

H U X 0 1 H W W H X

- U X X X X X X X X


Motivation for Process Construct How would you build the logic for a 32 by 2

multiplexor given inverters and 2 input nands?

1

0

SEL

A

DOUTB

SEL

A[0]

DOUT[0]

DOUT[1]

A[1]

B[1]

B[0]

. .

.. .

..

. .

. .

.

. .

.

. .

..

. .

TA(0)

TA(1)

TB(1)

TB(0)

SELbar

Given the logic schematic, can you write the VHDL code?


MUX CSA Description

1

0

SEL

A

DOUTB

How can we describe the circuit in VHDL if we don’t know what primitive gates we will be designing with?

entity MUX32X2 is port(A,B: in std_logic_vector(31 downto 0); DOUT: out std_logic_vector(31 downto 0); SEL: in std_logic);end MUX32X2;

expands to 32 gates each

architecture conc_behavior of MUX32X2 is signal TA,TB: std_logic_vector (31 downto 0), SELbar: std_logic;begin SELbar <= not SEL after 1 ns; TA <= A nand SELbar after 2 ns; TB <= B nand SEL after 2 ns; DOUT <= TA nand TB after 2 ns;end conc_behavior;


Mux Process Description

Process fires whenever a signal in the “sensitivity list” changes

entity MUX32X2 is port(A,B: in std_logic_vector(31 downto 0); DOUT: out std_logic_vector(31 downto 0); SEL: in std_logic);end MUX32X2;

architecture process_behavior of MUX32X2 isbegin mux32x2_process: process(A, B, SEL)

begin if (SEL = ‘0’) then

DOUT <= A after 5 ns; else

DOUT <= B after 4 ns; end if;end process mux32x2_process;

end process_behavior;

1

0

SEL

A

DOUTB


VHDL Process Features

Process body is executed sequentially to completion in zero (simulation) time

Delays are associated only with assignment of values to signals

marked by CSAs <= operator

Variable assignments take effect immediately marked by := operator

Upon initialization all processes are executed once

After initialization processes are data-driven activated by events on signals in sensitivity list waiting for the occurrence of specific events using wait

statements


Process Programming Constructs if-then-else

Boolean valued expressions are evaluated sequentially until first true is encountered

case branches must cover all possible

values for the case expression

for loop loop index declared (locally) by virtue of use in loop stmt loop index cannot be assigned a value or altered in loop body

while loop condition may involve variables modified within the loop

while (condition) loop

for index in value1 to value2 loop

case (expression) is when ‘value0’ => . . .end case;

if (expression1 = ‘value1’) then . . .elsif (expression2 = ‘value2’) then . . .end if;


Behavioral Description of a Register File

library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;

entity regfile is port(write_data: in std_logic_vector(31 downto 0); dst_addr,src1_addr,src2_addr: in UNSIGNED(4 downto 0); write_cntrl: in std_logic; src1_data,src2_data: out std_logic_vector(31 downto 0));end regfile;

Register File

src1_addr

src2_addr

dst_addr

write_data

32 bits

src1_data

src2_data

32words

write_cntrl


Behavioral Description of a Register File, con’t

architecture process_behavior of regfile is type reg_array is array(0 to 31) of std_logic_vector (31 downto 0);begin regfile_process: process(src1_addr,src2_addr,write_cntrl) variable data_array: reg_array := ( (X”00000000”), (X”00000000”), . . . (X”00000000”)); variable addrofsrc1, addrofsrc2, addrofdst: integer; begin addrofsrc1 := conv_integer(src1_addr); addrofsrc2 := conv_integer(src2_addr); addrofdst := conv_integer(dst_addr); if write_cntrl = ‘1’ then data_array(addrofdst) := write_data; end if; src1_data <= data_array(addrofsrc1) after 10 ns; src2_data <= data_array(addrofsrc2) after 10 ns; end process regfile_process;end process_behavior;


Process Construct with Wait Statement

library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;

entity dff is port(D,clk: in std_logic; Q,Qbar: out std_logic);end dff;

architecture dff_behavior of dff isbegin output: process

begin wait until (clk’event and clk = ‘1’);

Q <= D after 5 ns;Qbar <= not D after 5 ns;

end process output;end dff_behavior;

DQ

clk

Qbar

positive edge-triggered

dff


Wait Statement Types Wait statements specify conditions under which a process may

resume execution after suspension wait for time expression

- suspends process for a period of time defined by the time expression

wait on signal

- suspends process until an event occurs on one (or more) of the signals

wait until condition

- suspends process until condition evaluates to specified Boolean

wait

Process resumes execution at the first statement following the wait statement

wait until (clk’event and clk = ‘1’);

wait for (20 ns);

wait on clk, reset, status;


Signal Attributes

Function attribute Function

signal_name’event Boolean value signifying a change in value on this signal

signal_name’active Boolean value singifying an assignment made to this signal (may not be a new value!)

signal_name’last_event Time since the last event on this signal

signal_name’last_active Time since the signal was last active

signal_name’last_value Previous value of this signal

Attributes are used to return various types of information about a signal


Things to Remember About Processes

A process must have either a sensitivity list or at least one wait statement

A process cannot have both a sensitivity list and a wait statement

Remember, all processes are executed once when the simulation is started

Don’t confuse signals and variables. Signals are declared either in the port definitions in the

entity description or as internal signals in the architecture description. They are used in CSAs. Signals will be updated only after the next simulation cycle.

Variable exist only inside architecture process descriptions. They are used in variable assignment statements. Variables are updated immediately.


Finite State Machine “Structure”

D(0)Q(0)

a

clk

b

z

comb

dff

dff D(1)Q(1)

FetchPC = PC+4

DecodeExec


Structural VHDL Model

in1

Qbar(0)

clk

in2

out1

System is described by its component interconnections

assumes we have previously designed entity-architecture descriptions for both comb and dff with behavioral models

comb

c_state(1) nxt_state(1)

b

az

clk

D(0)Q(0)

dff

dff D(1)Q(1)

Qbar(1)

nxt_state(0)c_state(0)

s1(0)

s1(1)

s2(0)

s2(1)


Finite State Machine Structural VHDLentity seq_circuit is port(in1,in2,clk: in std_logic; out1: out std_logic);end seq_circuit;

architecture structural of seq_circuit iscomponent comb port(a,b: in std_logic; z: out std_logic;

c_state: in std_logic_vector (1 downto 0); nxt_state: out std_logic_vector (1 downto 0));

end component;component dff port(D,clk: in std_logic; Q,Qbar: out std_logic);end component;for all: comb use entity work.comb(comb_behavior);for all: dff use entity work.dff(dff_behavior); signal s1,s2: std_logic_vector (1 downto 0);begin

C0:comb port map(a=>in1,b=>in2,c_state=>s1,z=>out1, nxt_state=>s2);

D0:dff port map(D=>s2(0),clk=>clk,Q=>s1(0),Qbar=>open);D1:dff port map(D=>s2(1),clk=>clk,Q=>s1(1),Qbar=>open);

end structural;


Summary Introduction to VHDL

A language to describe hardware- entity = symbol, architecture ~ schematic, signals =

wires

Inherently concurrent (parallel) Has time as concept Behavioral descriptions of a component

- can be specified using CSAs

- can be specified using one or more processes and sequential statements

Structural descriptions of a system are specified in terms of its interconnections

- behavioral models of each component must be provided

Week 6.1Spring 2005 14:332:331 Computer Architecture and Assembly Language Spring 2005 Week 6...

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