Walter Dso Project
59
Digital oscilloscope module with PC interface Stephan Walter <[email protected]> Department of Microengineering Swiss Federal Institute of Technology Lausanne Semester Project January 14, 2008 Supervisor Prof. Maher Kayal EPFL / LEG Assistant Fabrizio Lo Conte EPFL / LEG
Transcript of Walter Dso Project
Digital oscilloscope module with PC interface
Stephan Walter<[email protected]>
Department of MicroengineeringSwiss Federal Institute of Technology Lausanne
Semester Project
January 14, 2008
SupervisorProf. Maher Kayal
EPFL / LEG
AssistantFabrizio Lo Conte
EPFL / LEG
Contents
1 Introduction 3
2 Previous work 5
3 Specifications 10
4 Hardware design 11
5 Software 26
6 Results 32
7 Summary and outlook 37
Bibliography 39
A Code 40
B Software user’s guide 53
C Schemata 54
2
Chapter 1
Introduction
The Master’s project done by Fabrizio Lo Conte [10] presents a universal interface for the USB2.0 bus. Various different modules can be connected to the interface card. The data receivedover the serial USB bus are converted to a parallel, 16-bit wide bus. The modules are addressedby a 16-bit parallel address bus. Data can be read from or written to modules in chunks of up to1024 words.
This project builds upon this interface card to make a software-controlled DSO (digital samplingoscilloscope). It consists of the following elements:
• an analog circuit for amplifying the signal that is to be measured
• an analog-to-digital converter
• a digital circuit to temporarily store the digital data
• interface logic to communicate with the parallel data and address bus
• software running on a standard desktop PC that will collect and display the data in real-time
3
Figure 1.1: Universal USB interface (taken from [10])
4
Chapter 2
Previous work
2.1 Projects by others
The following list shows some existing work on designing a digital oscilloscope.
2.1.1 “Bitscope”
Author: BitScope Designs [3]Performance: 2 channels – 40 MS/s
Figure 2.1: Bitscope 300
5
This oscilloscope is sold commercially in different variants for USD 550.– to 1600.–. The ADC isa TLC5540 by Texas Instruments, the sample buffer is a Micron MT 5C2568. These are controlledby a PIC microcontroller by Microchip. Interfaces to a PC by Ethernet or USB.
2.1.2 “PC-based DSO”
Author: “area26” [2]Performance: 4 channels – 100 MS/sThis project consists of a main board with an Altera FPGA and up to four ADC boards withcircuits of type MAX1449 by Maxim. The oscilloscope interfaces to a PC over Ethernet.
2.1.3 “DSOA Mk3”
Author: D. Jones [7]Performance: 2 channels – 20 MS/sThe ADC is a Philips TDA8703, the sample buffer is an IDT 7202. There is a parallel (printer)port connection to a PC.
2.1.4 “Oscilloscopio digitale”
Author: L. Lutti [11]The ADC is a Texas Instruments ADS830, the sample buffer is a CY7C199. These are controlledby a Xilinx CPLD.
2.1.5 “DSO”
Author: J. Glaser [5]Performance: 4 channels – 80 MS/sThe ADC is a MAX1448 by Maxim, controlled by a Xilinx FPGA. Interfaces to a PC via USB. Theanalog input stage (see figure 2.2) is a good starting point for a new design and I have takensome inspiration from it.
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7
Figure 2.3: LDSO by T. Grocutt
2.1.6 “LSDO”
Author: T. Grocutt [6]Performance: 2 channels – 50 MS/sThe ADC is an Intersil HI5667, which is controlled by an Altera FPGA.
2.1.7 “eOscope”
Author: “eosystems.ro” [4]Performance: 1 channel – 40 MS/sThe ADC is a Texas Instruments ADS830, the sample buffer is an IDT 7201. An Atmel AVRmicrocontroller and a Xilinx CPLD are used for control. The device has an LCD screen and doesnot interface to a computer.
8
Figure 2.4: eOscope
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Chapter 3
Specifications
3.1 Hardware specifications
After studying the performances of the designs shown in the last chapter, the following specifi-cations have been established:
Sampling frequency ≥ 10MHzResolution ≥ 8 bitAnalog bandwidth (3dB) ≥ 100MHzInput voltage range ≥ ±30VInput resistance = 1MΩInput capacitance = 10 . . . 50pFCoupling selectable AC / DCAttenuation / amplification selectableSupply voltage = 3.3V or 5VPower consumption ≤ 2W
Table 3.1: Hardware requirements
From these basic requirements, some others can be derived: for example, any operational am-plifier acting on the signal must have a high enough slew rate so that it can follow the signal.
3.2 Software specifications
The software has two major functions: a) control the settings of the acquisition card such asfrequency and attenuation and b) visualization of the samples in a diagram of time/voltage andpossibly other information.
The detailed requirements will be defined later in section 5.1, as they depend on the hardwaredesign.
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Chapter 4
Hardware design
4.1 Analog section
ADC
DAC generating offset voltage
low−pass filter
x5 gain
add offset
:10 attenuationAC coupling
unity gain
x20 gain
Figure 4.1: Overview of the analog section
An oscilloscope probe is connected to a BNC connector. From there, the signal to be measuredgoes through several different stages as shown on figure 4.1.
4.1.1 AC/DC coupling
The first stage of the oscilloscope is the AC or DC coupling. AC coupling is done by a capacitorC101 of 47nF. This capacitor can be by-passed by closing a relay (see figure 4.2). Although sucha mechanical device can be bulky and consume a lot of current, it seems a better choice than aFET switch which would have to be driven at ±30V.
For the relay, the model G6K by Omron was chosen for its small size, 3V operation and low coilcurrent. This current of 30mA makes it possible to drive the relay directly from 74 logic ICs,provided the logic family has sufficient drive current.
When the relay is closed, the capacitor is discharged through the relay. In order to respect therelay’s current limit, a resistor is placed in series with the coupling capacitor.
The coil of the relay (R = 91Ω) is in series with a 20Ω resistor. This leads to a coil current of30mA in the closed state. The Schottky diode is a protection against voltage spikes that canoccur when removing the coil supply voltage.
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32
41
8
NC
2
1
C101 47n R101 30
CONN101
D105
R109
20
AC/DC
OMRON G6K
K101
Figure 4.2: Coupling circuit
4.1.2 Attenuation and over-voltage protection
Now the signal is attenuated by a factor of 10, selected by a relay of the same type as above. Theattenuation itself is achieved using a combined resistive and capacitive voltage divider for lowand high frequencies, respectively. Figure 4.3 shows the attenuation circuit.
+3.3V
−3.3V
67
51
8
C102
220p
C103
27pR102
1M8
R103
1M8
R104
100k D101
3V
D102
3V
R105
62
R106
62
D106
adjust to 24p4
OMRON G6K
K102
:10
R119
20
D103
clamped to +−3.5V
Figure 4.3: Attenuation and clamping circuit
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Type Bandwidth [MHz] Amps/package Iib[pA]
AD8065 145 1 1ADA4899 600 1 100000LT1222 500 1 100000LT1722 200 1, 2, 4 10000
Table 4.1: Input buffer op-amps
The values of C102,103 and R102...104 are chosen so that they result in a total input impedance of1MΩ and about 25pF, values that are common in commercially available oscilloscopes.
The following stages must be protected against voltages exceeding ±3V. Sometimes, this isdone by clamping the signal over two diodes to ±Vsupply. This means that the power supplymust be able to compensate any over-voltage. In the present case, this would not be a goodidea, as the power is supplied by a PC over the USB bus. A voltage surge might damage thecomponents of the computer.
The solution adopted here is the use of Zener diodes. They are reverse biased with a constantsmall biasing current from the power supplies. The signal is then clamped by conventionaldiodes to the Zeners.
4.1.3 Input buffer
Now the signal is put through an op-amp of unity gain. The requirements for this amplifier areas follows:
• Compatibility with the ±3.3V power supply.
• Input and output voltage range of ±3V.
• 3dB bandwidth of at least 100MHz at unity gain, in order to satisfy the requirements givenin section 3.1.
• Slew rate > 60V/µs. (see below)
• Low input biasing current Iib.
Besides the bandwidth, the slew rate is an important AC parameter for an amplifier. The signalmust be allowed to swing along the whole voltage range (from −3 to +3V) during one sampleperiod (100ns at 10Msps).
Input biasing current is important as this is the first amplifier, which is directly connected to theinput. Any biasing current influences the circuit we want to measure. Operational amplifiersoften have Iib in the range of several microamperes. Table 4.1 lists some candidates.
For the first design of the analog stage, the AD8065 by Analog Devices was chosen. This chipturned out to be difficult to obtain. Also, it tends to amplify high frequencies to much, as willbe shown in section 6.1.
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R107
3k9
R108
1k
−3.3V
+3.3V
R110
3k3
DCOFFSET
R114 1k
R115
1k
+3.3V
−3.3V
3
41
5V+
2V−
U101
AD8065
R121
20
3
21
8V+
4V−
U102
AD8062
−3.3V
R123
330LM4040
Z101
Figure 4.4: Buffering and offset circuit
4.1.4 DC offset
The second op-amp stage will add a selectable offset voltage to the signal, as well as limiting itsswing for the ADC or the following gain stages. ADCs with a supply voltage in the order of 3Voften have an input voltage swing of 2V centered around a reference voltage. This is also truefor the ADC chosen here, which is presented in section 4.2.1. The offset voltage is generated by aDAC with an output range of 0 to 2.5V. This would make it impossible to have a negative offset,or “shift down” the signal. The solution is to use the amplifier in a summing configuration: theweighted addition of the signal, the DAC voltage and a negative reference voltage gives a greatflexibility. The voltages are summed as follows:
Vout = 0.33Vin + 1.28Vo f f set + 0.39(−2.5V)
The important requirements for the amplifier are: a gain bandwidth > 200MHz and a slew rate> 20V/µs. These parameters are obtained by the same reasoning shown for the first amplifier.Some candidates are listed in table 4.2
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Type Bandwidth [MHz] Amps/package Comments
AD8061 1 not rail-to-rail inputAD8062 2 not rail-to-rail inputLMH6609 900 not rail-to-railLMH6639 190 rail-to-railLMH6654 250 low noise, not rail-to-rail
Table 4.2: Op-amps for offset
COM13
NC10
NO16
IN9
MAX4547
COM5
NC8
NO2
IN1
MAX45473
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R122
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AD8062
ADCIN
Figure 4.5: Gain circuit
4.1.5 Gain
The signal can be amplified using a multiplier of 5 or 20 or a combined multiplier of 100. Thegain of 5 is achieved with a single operational amplifier with a gain bandwidth > 500MHz. Again of 20 would be difficult for a single amplifier, so two operational amplifiers are used.
As can be seen on figure 4.5, the first amplifier has a gain of 1 + 24001200 = 3 and the second 1 +
68001200 = 6.67. For the lower gain, the type of the amplifier is the same as for the offset circuit.
For the two gain stages of 6.67 and 5, the LT6200-5 was used. It has a minimum stable gain of 5(see table 4.3). Small resistors are placed in series with the op-amp outputs to isolate the outputsfrom the parasitic input capacitances of the next stage.
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Type Bandwidth [MHz] Amps/package Comments
LMH6733 1000 3 single supply, not rail-to-railLT1806 325 1, 2 unity-gain stableLT1818 400 1, 2 unity-gain stableLT6200-5 800 1 G ≥ 5OPA699 1000 1 limited voltage
Table 4.3: Op-amps for gain stage
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4.2 Sampling
SA1SA2SA3SA4SA5SA6SA7SA8SA9
SA5SA1SA2SA3SA4SA6SA7SA8SA9
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CLK12
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GND14
OE15
D9 16
D8 17
D7 18
D6 19
D5 20
OVDD21
TP 22
OGND23
D4 24
D3 25
D2 26
D1 27
D0 28
REFOUT29
GND30
REFIN31
REFP32
U201
NC
NC
R202
51
C204
100n
C205
22p
C206 100n
C207 100n
C208
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Q2 13
Q3 14
Q8 15
GND16
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Q4 19
Q5 20
Q6 21
Q7 22
XO/HF 23
EF 24
RS25
FL/RT26
D728D629D530D431
VCC32
U202
NC
Vcc
Vcc
Vcc
Figure 4.6: ADC and FIFO memory
4.2.1 ADC
Several companies offer analog to digital converters with the desired sampling rate. Importantcharacteristics are the resolution and the maximum and minimum sampling rate (some con-verters have a minimum sampling rate of about 1MHz, which would be wasteful for acquiringsignals of low frequency). Supply voltage is also an important concern as some circuits requiredifferent voltages for the analog and digital parts.
The converter chosen for this project is the Maxim MAX1444. It has a resolution of 10 bit and asampling rate of up to 40MHz. Pin-compatible variants offer up to 80MHz.
4.2.2 Sample storage
The sample data is stored in a FIFO memory of type IDT72V06. This chip has a supply voltageof 3V, a capacity of 16k × 9 bit and an access time of 15ns. The high capacity allows for someleeway in the communication over USB. That is, a total of 16384 samples can be memorizedbefore the FIFO memory is full and has to be read out.
The ADC will output a 10-bit value at each rising clock pulse plus tDO = 8ns max, as shown infigure 4.7. Figure 4.8 show the timing diagram of the FIFO memory (tDH = 0). If the same clocksignal is applied to the ADC and to the W input of the FIFO, the output of the ADC changesbetween the periods DATA IN VALID of the FIFO.
On the FIFO, the write cycle starts on the falling edge of W if the full flag is not set. Data is notoverwritten if the FIFO is full.
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Figure 4.7: Sampling operation on the ADC. Excerpt from datasheet
Figure 4.8: Write operation on the FIFO. Excerpt from datasheet
Figure 4.9: Acquisition circuit board
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4.3 Clock
Both the ADC and the FIFO operate on the same clock. The clock source must be programmableby software in a range of up to 10MHz.
Important parameters the frequency accuracy and jitter. The importance of the jitter of the ADCcan be illustrated with the following example:
The relationship between signal-to-noise ratio and jitter delay tj is given by the following equa-tion (see [8]):
SNRj = 20 log10
[1
2π f tj
]The effective number of bits (ENOB) of an ADC is typically defined as:
ENOB =SNR− 1.76
6.02
My design uses 9 bits of the ADC (ENOBADC = 9). Jitter noise should not make things worse.Thus ENOBj (the equivalent limitation on the number of bits due to jitter) must be bigger than9. Re-arranging the equation gives the following condition for the product of input frequencyand jitter time:
f tj < 2.5 · 10−4
Suppose we are measuring a sine wave signal of 100kHz at full swing. The jitter must be smallerthan 2.5ns, which corresponds to 2.5% at a sampling frequency of 10MHz.
The chip chosen was an LTC6903 by Linear Technologies. It provides a clock signal between1kHz and 68MHz and can be programmed via SPI (serial peripheral interface). This IC has ajitter of less that 0.4% for frequencies below 10MHz, as can be seen on figure 4.10.
Figure 4.10: Jitter vs frequency for LTC6903. Excerpt from datasheet [9]
The clock signal is buffered by a 7404 inverter (in a single-gate variant). Such a buffer is sug-gested in the datasheet if more than two inputs are driven, or if the line is longer than 5cm. Both
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SCLK
SDIN
CSCLK
LTC6903
GND1
SDI2
SCK3
SEN4
CLK 5
CLK 6OE7V+
8
U501
Vcc
NC
C501 10n
CLKC502 1u
2 4
74LVC1G04
U502
Figure 4.11: Clock generation circuit
are the case here. Also, the clock signal needs to stay high during a reset of the FIFO. Thanks tothe inverting buffer, we can simply turn off the clock chip with the correct SPI command, andthe clock line will stay high.
4.4 Bus interface
4.4.1 Bus timing requirements
Figure 4.12 shows the state of the bus when sending data from the PC to the oscilloscope module.The address on the bus must be compared to the module’s address. If they match, the data issimply read at every rising edge of the EnableOut signal.
Address ZZZVVVVVVVVVVVVVVVVVVVVVVVV-VVVVVVVVVVVVVVVVVVVVVVZZ
EnableOut LLLLLHHLLHHLLHHLL-HHLLHHLLHHLLLL
Read LLLLLLLLLLLLLLLLLLLLLLLLLLLLL-LLLLLLLLLLLLLLLLLLLLLLLLLL
Data ZZZVVVVVVVVVVVVVVVVVV-VVVVVVVVVVVVVVVVVVZZ
Address
Data0 Data1 DataN
Figure 4.12: Timing diagram PC→ oscilloscope
The bus timing for retrieving the data from the module is shown in figure 4.13. The Cypresschip will read the data at the middle of every pulse of EnableOut.
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Address ZZZVVVVVVVVVVVVVVVVVVVVVVVV-VVVVVVVVVVVVVVVVVVVVVVZZ
EnableOut LLLLLHHLLHHLLHHLL-HHLLHHLLHHLLLL
ReadOut LHHHHHHHHHHHHHHHHHHHHHHHHHH-HHHHHHHHHHHHHHHHHHHHHHHL
Data ZZZVVVVVVVVVVVVVVVVVV-VVVVVVVVVVVVVVVVVVZZ
Address
Data0 Data1 DataN
Figure 4.13: Timing diagram oscilloscope→ PC
After a first design of the analog stage had been established, it became clear that multiple chan-nels could be easily offered. This is done by making an interface card where multiple ADC cardscould be plugged in. The overhead for this turned out to be minimal: only a multiplexer wasneeded to send the WRITE or READ signal to the correct ADC card.
4.4.2 Communication protocol
The communication protocol for this project has been designed to be simple. It can be imple-mented using standard logic circuits. For reading the samples, the 9-bit values are read directlyfrom the FIFO. The data format is as follows:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0.. .. .. .. .. /FF /EF D8 D7 D6 D5 D4 D3 D2 D1 D0
| |set if FIFO not full --+ |set if FIFO not empty -----+
The 9 lowest bits are the data bits. The flags indicating whether the FIFO is empty (EF) or full(FF) are also sent. The computer simply reads an amount of data and discards the words thathave EF set to 0.
The data lines of the FIFO are connected directly to the bus. For the two flags, a buffer of type74125 is used.
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Changing the acquisition parameters is just as simple: one word is sent over the bus that con-tains all the control bits. The 8 lowest bits are kept separately for each channel in a flip-flop oftype 74574. The following figure lists each control bit:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0.. .. .. .. .. .. .. /CS AC :10 x20 x5 SDI SCK /DS /RS
| | | | | | | | |SPI: clock chip select --------+ | | | | | | | |AC or DC coupling --------------------+ | | | | | | |:10 divider ------------------------------+ | | | | | |x20 multiplier -------------------------------+ | | | | |x5 multiplier ------------------------------------+ | | | |SPI: data in -------------------------------------------+ | | |SPI: clock -------------------------------------------------+ | |SPI: DAC chip select -------------------------------------------+ |reset FIFO ---------------------------------------------------------+
4.4.3 Logic circuitry
The digital logic is constructed using logic ICs from the 7400 series. The choice of the fam-ily is crucial: only a few both support low supply voltages and have low propagation delays.Additionally, for driving the relays, high output drive current is necessary.
Name Supply [V] Delay [ns] Drive [mA] Comments
HC 2–6 9 8 standardAHC 2–6 5 8LVT 2.7–3.6 2 64LVC 1.2–3.6 4 24
Table 4.4: Logic family parameters
For driving the relays, the LVT family will be used. The other chips will be selected by theiravailability and price.
4.4.4 Logic functions
The module must be able to detect its address on the bus. A 8-bit wide comparator (74521) isused. The address bus being 16 bit wide, in fact I use up 256 addresses of the 65536 possibleones.
Next we need to know whether we are supposed to read from or write to the bus. This is done bylooking at the R/W line of the bus. These signals are now combined using NAND and invertergates.
After the first prototype was built, it became apparent that some samples were lost. The problemwas that after all valid values had been read from the FIFO, a pulse of the sampling clock couldoccur. This meant that one value was read from the ADC into the FIFO. As the FIFO was nolonger empty now, another read operation would take place on the next bus clock pulse. Because
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1 EN
2 A0
4 A1
6 A2
8 A3
11 A4
13 A5
15 A6
17 A7
3B0
5B1
7B2
9B3
12B4
14B5
16B6
18B7
19A=B
74521
Vdd
A15
A14
A13
A12
A11
A10
A09
A08
ADDR
U401
Figure 4.14: Address decoder circuit
1 2
7404
5 6
7404
9 8
7404
12
13
1
2
7410
6
5
3
4
7410
1A13 Q
2B
14 Ce 3CLR
15 Re/Ce
4 Q
74123
Vcc
NCVdd
U402
ADDR
R/W
R/W
U402
U402
ENOUT BUSREAD
ENOUT
C401
270p
U403
U403
falling: write to bus
rising: readfrom the bus
BUSREAD
U411
C40247p
R4013k3
R402 470
D401
BUSWRITE
D09
Figure 4.15: Bus read/write detection circuit
the ADC clock and the bus clock are not synchronized at all, this could lead to an incompletewrite operation.
The solution was to inhibit further read attempts after the FIFO was empty. A 74123 monostablecircuit is triggered by the empty flag. It is re-triggered at each pulse of the bus clock and resetsitself after some time.
4.5 Power supply requirements
The analog part of the circuit needs +3.3V and−3.3V supplies. For the digital part, only a +3.3Vsupply is needed but it should be separated from the analog supply to avoid voltage spikesinfluencing the analog signals. Table 4.5 gives an estimation of power consumption when usingone channel.
An attempt was made to design a power supply. However, the ripple voltage from the DC–
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# Component Type Vs [V] Is/device [mA] Total power [mW]
2 Relay Omron G6K 3.3 30 1981 Op-amp AD8065 6.6 7 461 Op-amp AD8062 6.6 14 922 Op-amp LT6200 6.6 20 1321 Analog switch MAX4547 6.6 ≈ 0 ≈ 01 ADC MAX1444 3.3 19 631 FIFO IDT72V06 3.3 60 1981 DAC LTC2630 3.3 ≈ 0 ≈ 01 Flip-flop 74574 3.3 5 171 Bus buffer 74125 3.3 5 171 Comparator 74688 3.3 5 171 Flip-flop 74574 3.3 5 171 Clock LTC6903 3.3 3 101 AND 7408 3.3 5 172 Inverter 7404 3.3 5 171 Monostable 74123 3.3 5 17
total 858
Table 4.5: Estimation of power consumption
DC converter turned out to be problematic. A commercially available dual power supply iscurrently used.
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4.6 Board construction
Two acquisition boards and one bus interface board have been made and tested. Figure 4.16shows the three circuit boards connected to the existing USB interface by Fabrizio Lo Conte (ingray).
Figure 4.16: Oscilloscope with two channels.
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Chapter 5
Software
5.1 Requirements
The program must first establish a connection to the Cypress card via USB. Then the acquisitionparameters such as the gain must be sent to the card. The clock is halted so as not to haveany difference in the sample memory of the different channels. After the FIFO memory of eachchannel has been reset, the clock can be programmed and started.
Now the program must periodically read the values from the FIFO chips. Apart from readingand storing the 9 data bits, the flags FEMPTY and FFULL must be checked for each word.
If the full flag is set, sample data has been lost. In that case we have no choice but to reset theFIFO and start the sampling anew. If the empty flag is set, the corresponding words are notvalid samples. We simply ignore them and wait for data where the empty flag is not set.
The sample date is displayed as a diagram of voltage vs time. A trigger condition will definethe first sample to show on the left edge of the screen. The display can be triggered by a risingor a falling edge of a channel and at a voltage both specified by the user.
5.2 Language and libraries
The Python programming language [13] has been chosen because of the following advantagesover C++ (the traditional choice):
• it is an interpreted language, programs can be run on different platforms (Windows, Linux)without compiling
• memory is managed automatically, which reduces the work necessary as well as the po-tential for errors
For the communication over USB, the libusb library is used. This makes the code dealing withUSB platform-independent.
Graphical user interfaces (GUI) for Python programs are traditionally implemented with theTk toolkit. This toolkit is however rather old (the first version dates back to 1991) and was
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graphical user interface
sample acquisition
controlsframe.py
wx
drawwindow.py
bufferedwindow.py
usb
main.py
thread dso.py
iousb.py
sampleops.c
sampleops.py
spi.py
trigger.py
Figure 5.1: Simplified view of code dependencies. White boxes: existing libraries
developed for the X Window System used in Unix operating systems. WxWidgets [14] is a moremodern toolkit running on all modern operating systems. It is used for this project via theWxPython interface [12].
5.3 Structure of implementation
5.3.1 main.py
This module creates the frames for displaying the data and the control elements. It then startsthe data acquisition in dso.py as a seperate thread. A timer is set to re-draw the data 50 timesper second.
5.3.2 drawwindow.py and bufferedwindow.py
The oscilloscope traces are drawn in this module. Also, a grid is drawn and the parame-ters such as voltage and time per grid unit are shown. The DrawWindow class is based on theBufferedWindow class, which implements double-buffering to avoid flickering.
27
Figure 5.2: Screen-shot of the program showing a 10kHz sine wave
5.3.3 controlsframe.py
The control elements (buttons, sliders) are defined here. A screen-shot of the program is shownin figure 5.2. Note that the control elements are only shown for two channels. This is simplydone to prevent the window from taking up a lot of screen space. All four channels can beactivated by changing a single line in a configuration file.
5.3.4 dso.py
Most of the actual work is done by this module. The method start() first establishes a connec-tion with the USB interface. Then, the parameters such as gain, offset and sampling frequencyare set. The FIFO memory chips are reset and the data acquisition begins.
In an infinite loop, we first check if an operation by the user requires a reset of the FIFOs, forexample if a channel has just been activated. Then the request for the sample data are sent tothe USB interface. The samples received are then sent to the triggering module for storage andanalysis (see next section). In the rest of the loop, we check if other parameters such as offsetand gain have been modified. These do not require a reset, the new value is simply sent overthe USB.
28
5.3.5 trigger.py
Sample data is received by this module in chunks of several hundred samples. First, it is putinto a buffer according to the channel number.
The channel that the user selected for triggering is then analyzed, sample for sample, to find thepositions of the trigger event (indicated in the following figure as red dots).
For a periodic signal, there are usually several trigger points. We have to chose one that isfollowed by enough data to fill the screen.
The “old” data, that is samples which were received before the trigger point, can now be deleted.This has to be done for all channels in the same way in order to guarantee the synchronicity.
The sample values which are inside the display window are then sent to the drawwindow.pymodule, where all the channels are drawn in one frame.
29
5.3.6 sampleops.py
Some functions that deal with sample data in a time-consuming way have been separated intothis file. This Python module can then be replaced by a module written in C, as shown later inthe section on optimization.
5.3.7 iousb.py and spi.py
These modules contain the communication function for the USB bus and the SPI interface thatis used for the DAC and the clock.
5.4 Optimization
The choice of the Python programming language made a rapid development possible. It ishowever not without disadvantages: Operations on byte strings are not as fast as they would bein C or C++.
Code execution time has been measured for an acquisition time of one minute. Table 5.1 showsthe times for the function that use the most time in total. The cumulative time is the time of thefunction itself and all other functions that are called from it.
file function time/call [µs] cumulative time/call [µs]
sampleops.py usb bulk read1 614.4 –trigger.py callback 72.7 97.9iousb.py write 62.8 –sampleops.py checksamples 31.3 –iousb.py sortInData 43.5 312.5sampleops.py find trig events 23.3 –iousb.py sendData 22.2 1011.0iousb.py addDataToReadBuffer 5.6 –dso.py cb 4.5 134.5
Table 5.1: Time spent in functions (not optimized)
The functions highlighted with bold text have been chosen for optimization. These functionswere re-written in C. The result is shown in Table 5.2. Measuring the time of the C functionis not possible with the method used. But by comparing the cumulative time of some Pythonfunction, one can see that there it is indeed faster: The function sendData for example, whichcalls write and sortInData, uses 35% less time.
30
file function time/call [µs] cumulative time/call [µs]
iousb.py sendData 278.9 652.7trigger.py callback 72.8 85.3iousb.py write 142.5 –iousb.py sortInData 49.3 231.0iousb.py addDataToReadBuffer 5.7 –dso.py cb 5.7 91.0
Table 5.2: Time spent in functions (optimized)
31
Chapter 6
Results
6.1 Performance of analog stage
The transfer function of the input stage from the BNC connector to the input of the ADC hasbeen measured. This measurement was done with DC coupling and has been repeated for allgain settings. A network analyzer of type Agilent 4395A with an active FET probe (750MHz)was used.
It should be noted that the values of the gain refer to the range of the ADC input. A gain of onemeans that the maximum input signal of ±3V is amplified to the maximum input of the ADC,which is +0.5V . . . + 2.5V. On the Bode diagrams, the marker denoted “0” indicates the 3dBcut-off frequency. Input power, scale and reference position have been adapted to best showeach curve.
Figure 6.1: Bode plot for G = 1/10 Figure 6.2: Bode plot for G = 1/2
32
Figure 6.3: Bode plot for G = 1
Figure 6.4: Bode plot for G = 2
Figure 6.5: Bode plot for G = 5
Figure 6.6: Bode plot for G = 10
Figure 6.7: Bode plot for G = 20
Figure 6.8: Bode plot for G = 100
33
Figure 6.9: Bode plots for G = 1 at different nodes
The bandwidth obtained here is around 8MHz for some gain configurations and around 20MHzfor others. This does not satisfy the specifications. An obvious problem is the spike at around30MHz.
If we measure the frequency response at different nodes in the circuit (figure 6.9), it is clearthat this spike is caused by the unity-gain buffer op-amp. In the bode diagram, the differencebetween the signals labeled “before buffer” and “after buffer” is caused by the AD8065.
The datasheet of this chip shows that it is indeed a shortcoming. In figure 6.11 it can be seenthat the magnitude of this error depends on CL, the load capacitance from output to ground.
34
Figure 6.10: AD8065 small signal frequency response. Excerpt from datasheet [1]
Figure 6.11: AD8065 frequency response for various CL. Excerpt from datasheet [1]
35
Figure 6.12: Bus communication
6.2 Software performance
The software runs on Linux, and with slightly worse performance on Windows. It can acquirethe samples and display the traces graphically. All parameters (AC/DC coupling, attenuation,gain, offset) can be modified. The channels are shown in the same frame using different colors.
The sampling frequency is theoretically limited to about 3Msps. This is due to the USB interfacewhich has a throughput of about 43Mbit/s (reading speed, see [10]), and the fact that eachsample uses 16 bits. Improvements should be possible here, as the gross throughput for USB is480Mbit/s.
Currently, the sampling frequency is limited by the latency of the operating system on the PC.At 2MHz for example, the FIFO memory would fill up completely in 8ms. Desktop operatingsystems such as Windows and Linux have a granularity of the task scheduler that is in the rangeof 1 to 10ms. The problem is apparent on figure 6.12, which shows the communication on theparallel bus when connected to a Linux PC. Each spike represents one packet of 1022 words.Interruptions of up to 10ms duration are occurring. On a reasonably fast PC running Linux, thehighest sampling rate achieved using one channel was 1.5Msps.
One possible solution is to use a real-time operating system, such as RTLinux or RTAI. Thedrawback of such a system would be the loss of compatibility with any desktop PC.
36
Chapter 7
Summary and outlook
7.1 Conclusion
The project, in its current state, has the basic functionalities of a digital oscilloscope. It is capableof measuring voltage signals smaller than ±30V. The signal can be attenuated or amplified atvarious factors. The digital logic that processes the sample data has been designed to be simple.On the hardware side, no programming was involved.
PCB layouts for the circuits have been made and the oscilloscope was assembled with two chan-nels. I characterized the frequency response of the analog stage.
The software allows the user to view the data in the same way as with any oscilloscope, andto modify the configuration of the hardware (gain, sampling rate, etc.). Written in Python withsome functions optimized in C, the software runs on both the MS Windows and GNU/Linuxoperating systems.
The specifications are however not completely satisfied: real-time sampling faster than 1.5Mspsis not possible. This is due to the latency of the operating system and is unlikely to be improvedunless significant changes are made to the hardware or the software. Also, the desired analogbandwidth could not be reached.
7.2 Future prospects
The following improvements to this project are possible:
• resolve problems in the high frequency range by choosing a different operational amplifier(see section 6.1) and modifying the PCB layout to reduce parasitic capacitances.
• investigate the use of programmable logic (CPLD or FPGA) instead of standard 74 logicchips. This would likely result in higher flexibility and lower component count but alsohigher price.
• design, test and integrate a power supply that satisfies the requirements laid out in section4.5. The 5V supply of the USB interface could be used for this, as power consumption isquite low (< 1W for one channel).
37
• do trigger detection in hardware. This would allow for higher sampling rates if the datais not transmitted in real-time, but only after a trigger condition has occurred.
• extend the software to do various data visualization methods such as frequency analysis,X–Y curves or arithmetic operations on multiple channels.
* * *
Stephan Walter
LausanneJanuary 14, 2008
38
Bibliography
[1] Analog Devices Inc.: AD8065/AD8066 datasheet.
[2] area26: PC-based DSO. http://beta.area26.no-ip.org/projects/dso.
[3] BitScope Designs: The Bitscope hardware design. http://www.bitscope.com/design/hardware/.
[4] eosystems.ro: eOscope. http://eosystems.ro/eoscope/eoscope_en.htm.
[5] Glaser, J.: Digital sampling oscilloscope. http://johann-glaser.at/projects/DSO/.
[6] Grocutt, T.: Large storage depth oscilloscope, 2000. http://dsoworld.co.uk/.
[7] Jones, D.L.: Digital storage oscilloscope adapter Mk3, 1998. http://alternatezone.com/electronics/dsoamk3.htm.
[8] Kester, W.: Data Conversion Handbook. Elsevier/Newnes, 2005, ISBN 0750678410. http://www.analog.com/library/analogDialogue/archives/39-06/data_conversion_handbook.html.
[9] Linear Technology Corporation: LTC6903/LTC6904 datasheet.
[10] Lo Conte, F.: Interface I/O Universelle pour port USB, 2006.
[11] Lutti, L.: Autocostruzione di un oscilloscopio digitale, 2003. http://www.enetsystems.com/
~lorenzo/scope/.
[12] Rappin, N. and R. Dunn: wxPython in Action. Manning Publications Co., Greenwich, CT,USA, 2006, ISBN 1932394621.
[13] Rossum, G. van: Python reference manual, 2006. http://docs.python.org/ref/ref.html.
[14] Smart, J., R. Roebling, V. Zeitlin, R. Dunn, et al.: wxWidgets 2.8.6: A portable C++ and PythonGUI toolkit, 2007. http://www.wxwidgets.org/manuals/stable/wx_contents.html.
39
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for
iin
rang
e(N
UM
CH
AN
NEL
S)],
self
.set
ting
s.tr
igch
anne
l,se
lf.tr
igch
anne
l)
#cr
eate
trig
cond
ition
radi
obox
mak
era
dio
box(
”Con
diti
on”,
trig
cond
itio
nna
mes
,
42
40se
lf.s
etti
ngs.
trig
cond
itio
n,se
lf.tr
igco
ndit
ion)
size
r.A
dd(t
rigs
izer
,0,w
x.EX
PAN
D)
freq
labe
l=w
x.St
atic
Text
(sel
f.pan
el,
45la
bel=
u”/\
/Sa
mpl
ing
freq
uenc
y/ˆ\
/”,
styl
e=w
x.A
LIG
NC
ENTR
E)fr
eqsl
ider
=w
x.Sl
ider
(sel
f.pan
el,
valu
e=se
lf.s
etti
ngs.
freq
sett
ing/
FREQ
DIV
,m
inV
alue
=0,m
axV
alue
=MA
XFR
EQU
ENC
Y/F
REQ
DIV
)50
self
.Bin
d(w
x.EV
TSL
IDER
,sel
f.fre
quen
cy,f
req
slid
er)
size
r.A
dd(f
req
labe
l,0,
wx.
EXPA
ND
)si
zer.
Add
(fre
qsl
ider
,0,w
x.EX
PAN
D)
chan
size
r=
wx.
BoxS
izer
(wx.
HO
RIZ
ON
TAL)
55
#tr
igle
vel
tsiz
er=
wx.
BoxS
izer
(wx.
VER
TIC
AL)
tlev
ella
bel=
wx.
Stat
icTe
xt(s
elf.p
anel
,la
bel=
”Tri
g\nl
evel
”,st
yle=
wx.
ALI
GN
CEN
TRE)
60ts
izer
.Add
(tle
vel
labe
l,0,
wx.
ALL|w
x.A
LIG
NC
ENTE
R,2
)tl
evel
=w
x.Sl
ider
(sel
f.pan
el,
valu
e=M
AX
SAM
PLE
VALU
E−
self
.set
ting
s.tr
igle
vel,
min
Val
ue=0
,max
Val
ue=M
AX
SAM
PLE
VALU
E,si
ze=(
5,40
0),
styl
e=w
x.SL
VER
TIC
AL)
65se
lf.B
ind(
wx.
EVT
SLID
ER,s
elf.t
rig
leve
l,tl
evel
)ts
izer
.Add
(tle
vel,
1,w
x.A
LL|w
x.EX
PAN
D|w
x.A
LIG
NC
ENTE
R,2
)ch
ansi
zer.
Add
(tsi
zer,
1,w
x.A
LL,b
orde
r=5)
for
cin
rang
e(N
UM
CH
AN
NEL
S):
70#
chan
nelt
oggl
ebu
tton
csiz
er=
wx.
BoxS
izer
(wx.
VER
TIC
AL)
cbut
ton
=w
x.To
ggle
Butt
on(s
elf.p
anel
,id=
c,la
bel=
chan
nel
nam
es[c
],si
ze=(
50,2
6))
ifc
inse
lf.s
etti
ngs.
acti
vech
ans:
75cb
utto
n.Se
tVal
ue(T
rue)
self
.Bin
d(w
x.EV
TTO
GG
LEBU
TTO
N,s
elf.t
oggl
ech
anne
l,cb
utto
n)cs
izer
.Add
(cbu
tton
,0,w
x.A
LL|w
x.A
LIG
NC
ENTE
R,b
orde
r=0)
#A
C/D
Cco
uplin
gch
eckb
ox80
box
=w
x.C
heck
Box(
self
.pan
el,i
d=c,
labe
l=co
uplin
gna
mes
[1])
self
.Bin
d(w
x.EV
TC
HEC
KBO
X,s
elf.c
oupl
ing,
box)
csiz
er.A
dd(b
ox,0
,wx.
ALL|w
x.A
LIG
NC
ENT
ER,b
orde
r=5)
#of
fset
slid
er85
self
.off
set
labe
l[c]
=w
x.St
atic
Text
(sel
f.pan
el,l
abel
=””,
styl
e=w
x.A
LIG
NC
ENT
RE)
self
.set
offs
ette
xt(c
)cs
izer
.Add
(sel
f.off
set
labe
l[c]
,0,w
x.A
LL|w
x.A
LIG
NC
ENT
ER,
bord
er=2
)90
coff
set=
wx.
Slid
er(s
elf.p
anel
,id=
c,va
lue=
MA
XO
FFSE
T−
self
.set
ting
s.ch
anne
ls[c
].off
set,
min
Val
ue=0
,max
Val
ue=M
AX
OFF
SET
,siz
e=(5
,300
),st
yle=
wx.
SLV
ERTI
CA
L)se
lf.B
ind(
wx.
EVT
SLID
ER,s
elf.o
ffse
t,co
ffse
t)95
csiz
er.A
dd(c
offs
et,1
,wx.
ALL|w
x.EX
PAN
D|w
x.A
LIG
NC
ENT
ER,
bord
er=2
)
#ga
inin
crea
se/d
ecre
ase
butt
ons
self
.gai
nla
bel[
c]=
wx.
Stat
icTe
xt(s
elf.p
anel
,lab
el=”
Gai
n:x1
”)10
0cs
izer
.Add
(sel
f.gai
nla
bel[
c],0
,wx.
ALL|w
x.A
LIG
NC
ENT
ER,
bord
er=2
)
gain
size
r=
wx.
BoxS
izer
(wx.
HO
RIZ
ON
TAL)
min
usbu
tton
=w
x.Bu
tton
(sel
f.pan
el,i
d=c,
labe
l=”−
”,si
ze=(
26,2
6))
105
self
.Bin
d(w
x.EV
TBU
TTO
N,s
elf.d
ecre
ase
gain
,min
usbu
tton
)pl
usbu
tton
=w
x.Bu
tton
(sel
f.pan
el,i
d=c+
10,l
abel
=”+”
,siz
e=(2
6,26
))se
lf.B
ind(
wx.
EVT
BUTT
ON
,sel
f.inc
reas
ega
in,p
lusb
utto
n)ga
insi
zer.
Add
(min
usbu
tton
,0,w
x.A
LL,b
orde
r=0)
gain
size
r.A
dd(p
lusb
utto
n,0,
wx.
ALL
,bor
der=
0)11
0cs
izer
.Add
(gai
nsiz
er,0
,wx.
ALL|w
x.A
LIG
NC
ENT
ER,b
orde
r=2)
chan
size
r.A
dd(c
size
r,1,
wx.
ALL
,bor
der=
5)
size
r.A
dd(c
hans
izer
,1,w
x.EX
PAN
D)
115
self
.pan
el.S
etSi
zer(
size
r)si
zer.
Fit(
self
)
def
trig
mod
e(se
lf,e
vent
):se
lf.s
etti
ngs.
trig
mod
e=
even
t.Sel
ecti
on12
0
def
trig
chan
nel(
self
,eve
nt):
43
self
.set
ting
s.tr
igch
anne
l=ev
ent.S
elec
tion
def
trig
cond
itio
n(se
lf,e
vent
):12
5se
lf.s
etti
ngs.
trig
cond
itio
n=
even
t.Sel
ecti
on
def
trig
leve
l(se
lf,e
vent
):se
lf.s
etti
ngs.
trig
leve
l=M
AX
SAM
PLE
VALU
E−
even
t.Int
130
def
togg
lech
anne
l(se
lf,e
vent
):#
first
rem
ove
chan
nelf
rom
listo
fact
ive
chan
nels
self
.set
ting
s.ac
tive
chan
s=
[cfo
rc
inse
lf.s
etti
ngs.
acti
vech
ans
ifc
!=ev
ent.I
d]
#th
enad
dit
agai
nif
itis
activ
e13
5if
even
t.Sel
ecti
on:
self
.set
ting
s.ac
tive
chan
s.ap
pend
(eve
nt.Id
)
def
coup
ling(
self
,eve
nt):
self
.set
ting
s.ch
anne
ls[e
vent
.Id].c
oupl
ing
=ev
ent.S
elec
tion
140
def
set
offs
ette
xt(s
elf,
c):
self
.off
set
labe
l[c]
.Set
Labe
l(”O
ffse
t:\n%
.3fV
”%
(se
lf.s
etti
ngs.
chan
nels
[c].o
ffse
t∗\
MA
XO
FFSE
TV
OLT
AG
E/
(MA
XO
FFSE
T+1)
))14
5
def
offs
et(s
elf,
even
t):
o=
MA
XO
FFSE
T−
even
t.Int
self
.set
ting
s.ch
anne
ls[e
vent
.Id].o
ffse
t=o
self
.set
offs
ette
xt(e
vent
.Id)
150
def
freq
uenc
y(se
lf,e
vent
):se
lf.s
etti
ngs.
set
freq
(eve
nt.In
t∗FR
EQD
IV)
def
decr
ease
gain
(sel
f,ev
ent)
:15
5g
=se
lf.s
etti
ngs.
chan
nels
[eve
nt.Id
].gai
n−
1if
g<0:
g=
0se
lf.s
etti
ngs.
chan
nels
[eve
nt.Id
].gai
n=
gse
lf.g
ain
labe
l[ev
ent.I
d].S
etLa
bel(
”Gai
n:”+
gain
nam
es[g
])
160
def
incr
ease
gain
(sel
f,ev
ent)
:g
=se
lf.s
etti
ngs.
chan
nels
[eve
nt.Id−
10].g
ain
+1
ifg>
MA
XG
AIN
:g=
MA
XG
AIN
self
.set
ting
s.ch
anne
ls[e
vent
.Id−
10].g
ain
=g
self
.gai
nla
bel[
even
t.Id−
10].S
etLa
bel(
”Gai
n:”+
gain
nam
es[g
])
dso.
py
impo
rtsy
s,lo
ggin
g,ti
me
from
optp
arse
impo
rtO
ptio
nPar
ser
impo
rtio
usb,
sett
ings
,spi
5fr
omco
mm
onde
fsim
port∗
from
confi
gim
port∗
from
sam
pleo
psim
port
chec
ksam
ples
clas
sD
SO(o
bjec
t):
10de
fin
it(s
elf)
:lo
ggin
g.in
fo(”
open
ing
USB
devi
ce...
”)tr
y:se
lf.c
ard
=io
usb.
IOD
evic
e()
exce
ptio
usb.
NoI
nter
face
Erro
r:15
logg
ing.
erro
r(”N
oC
ypre
ssU
SBin
terf
ace
foun
d”)
sys.
exit
(1)
exce
ptio
usb.
Inte
rfac
ePer
mis
sion
sErr
or:
logg
ing.
erro
r(”C
laim
ing
USB
inte
rfac
eno
tper
mit
ted.
”+
”Cha
nge
perm
issi
ons
orru
npr
ogra
mas
root
user
.”)
20sy
s.ex
it(1
)
spi.i
nit(
self
.car
d)
def
rese
tfif
os(s
elf)
:25
”””S
top
osci
llato
r,re
setF
IFO
ofea
chch
anne
l,re
star
tosc
illat
or.”
””sp
i.sen
dOsc
illat
or(0
,0,3
)
for
chan
neli
nse
lf.s
etti
ngs.
acti
vech
ans:
self
.car
d.cl
earB
it(B
ASE
AD
DR
ESS
+ch
anne
l,FI
FOR
S)30
self
.car
d.se
tBit
(BA
SEA
DD
RES
S+
chan
nel,
FIFO
RS)
#TO
DO
halt
and
chec
kfif
ost
ate
spi.s
endO
scill
ator
((se
lf.s
etti
ngs.
freq
sett
ing
>>
10),
(sel
f.set
ting
s.fr
eqse
ttin
g&
0x3f
f))
35se
lf.c
ard.
send
Dat
a()
44
def
set
coup
ling(
self
,cha
nnel
,cou
plin
g):
ifco
uplin
g:se
lf.c
ard.
setB
it(B
ASE
AD
DR
ESS
+ch
anne
l,A
CD
C)
40el
se: se
lf.c
ard.
clea
rBit
(BA
SEA
DD
RES
S+
chan
nel,
AC
DC
)
def
set
offs
et(s
elf,
chan
nel,
offs
et):
spi.s
endD
AC
(cha
nnel
,off
set)
45
def
set
gain
(sel
f,ch
,gai
n):
”””C
ombi
nedi
vide
ran
dm
ulti
plie
rci
rcui
tsto
obta
inco
rrec
tgai
n.””
”
ifga
inin
[G0
1,G
05,
G2,
G10
]:50
#en
able
/10
divi
der
self
.car
d.cl
earB
it(B
ASE
AD
DR
ESS
+ch
,ATT
EN10
)el
se: se
lf.c
ard.
setB
it(B
ASE
AD
DR
ESS
+ch
,ATT
EN10
)
55if
gain
in[G
05,
G5,
G10
,G10
0]:
#en
able
x5m
ultip
lier
self
.car
d.se
tBit
(BA
SEA
DD
RES
S+
ch,G
AIN
5)el
se: se
lf.c
ard.
clea
rBit
(BA
SEA
DD
RES
S+
ch,G
AIN
5)60
ifga
inin
[G2,
G10
,G20
,G10
0]:
#en
able
x20
mul
tiplie
rse
lf.c
ard.
setB
it(B
ASE
AD
DR
ESS
+ch
,GA
IN20
)el
se:
65se
lf.c
ard.
clea
rBit
(BA
SEA
DD
RES
S+
ch,G
AIN
20)
def
star
t(se
lf,c
allb
ack,
sett
ings
,for
mat
=”de
c”,c
hann
els=
”0”)
:””
”Sen
dco
nfigu
rati
onto
mod
ule
and
star
trec
eivi
ngsa
mpl
es.”
””
70lo
ggin
g.in
fo(”
para
met
ers:
form
at=%
sch
anne
ls=%
sfr
eque
ncy=
%d”
,fo
rmat
,cha
nnel
s,se
ttin
gs.fr
eque
ncy)
self
.set
ting
s=
sett
ings
rese
nd=
True
75
def
cb(a
ddr,
data
):ch
anne
l=ad
dr−
BASE
AD
DR
ESS
try:
resu
lt=
chec
ksam
ples
(dat
a)80
callb
ack(
chan
nel,
resu
lt)
exce
ptR
unti
meE
rror
:lo
ggin
g.w
arni
ng(”
FIFO
FULL
chan
nel:%
d”,c
hann
el)
callb
ack(−
1,N
one)
self
.res
etfif
os()
85
logg
ing.
info
(”se
tcou
plin
g,at
tenu
atio
nan
dga
in...
”)fo
rch
inra
nge(
NU
MC
HA
NN
ELS)
:se
lf.c
ard.
addD
ataT
oWri
teBu
ffer
(BA
SEA
DD
RES
S+
ch,[
0xff
ff])
self
.car
d.cl
earB
it(B
ASE
AD
DR
ESS
+ch
,GA
IN5)
90se
lf.c
ard.
clea
rBit
(BA
SEA
DD
RES
S+
ch,G
AIN
20)
self
.set
coup
ling(
ch,0
)se
lf.s
etof
fset
(ch,
sett
ings
.cha
nnel
s[ch
].off
set)
self
.car
d.se
ndD
ata(
)
95w
hile
nots
etti
ngs.
halt
.lock
ed()
:if
sett
ings
.act
ive
chan
sm
odifi
edor
sett
ings
.freq
uenc
ym
odifi
ed:
callb
ack(−
1,N
one)
self
.res
etfif
os()
sett
ings
.act
ive
chan
sm
odifi
ed=
Fals
e10
0se
ttin
gs.fr
eque
ncy
mod
ified
=Fa
lse
REA
DSA
MPL
ES=
1020
/le
n(se
ttin
gs.a
ctiv
ech
ans)
for
chin
sett
ings
.act
ive
chan
s:se
lf.c
ard.
addD
ataT
oRea
dBuf
fer(
REA
DSA
MPL
ES,
105
BASE
AD
DR
ESS+
ch,c
b)se
lf.c
ard.
send
Dat
a()
for
chin
sett
ings
.act
ive
chan
s:ch
anda
ta=
sett
ings
.cha
nnel
s[ch
]11
0if
chan
data
.cou
plin
gm
odifi
ed:
self
.set
coup
ling(
ch,c
han
data
.cou
plin
g)ch
anda
ta.c
oupl
ing
mod
ified
=Fa
lse
rese
nd=
True
115
ifch
anda
ta.o
ffse
tm
odifi
ed:
self
.set
offs
et(c
h,ch
anda
ta.o
ffse
t)ch
anda
ta.o
ffse
tm
odifi
ed=
Fals
ere
send
=Tr
ue
45
120
ifch
anda
ta.g
ain
mod
ified
:se
lf.s
etga
in(c
h,ch
anda
ta.g
ain)
chan
data
.gai
nm
odifi
ed=
Fals
ere
send
=Tr
ue
125
ifre
send
:se
lf.c
ard.
send
Dat
a()
rese
nd=
Fals
e
ifse
lf.s
etti
ngs.
freq
uenc
y<
5000
:13
0ti
me.
slee
p(1/
self
.set
ting
s.fr
eque
ncy)
logg
ing.
info
(”St
oppi
ngos
cilla
tor.
..”)
spi.s
endO
scill
ator
(0,0
)
trig
ger.p
y
impo
rtth
read
from
com
mon
defs
impo
rt∗
from
sam
pleo
psim
port
find
trig
even
ts
5cl
ass
Trig
ger(
obje
ct):
”””R
ecei
vesa
mpl
esan
dap
ply
trig
ger
chec
king
.”””
sam
ples
=0
:[],
1:[]
10tr
igev
ents
=[]
lock
=th
read
.allo
cate
lock
()
def
init
(sel
f,se
ttin
gs):
self
.set
ting
s=
sett
ings
15
def
callb
ack(
self
,cha
nnel
,dat
a):
ifch
anne
l==−
1:#
rese
tsam
ple
buffe
rfo
rii
nse
lf.s
ampl
es.k
eys(
):20
self
.sam
ples
[i]=
[]se
lf.tr
igev
ents
=[]
retu
rn
ifse
lf.s
etti
ngs.
trig
mod
e==
TST
OP:
retu
rn25
trig
ch=
self
.set
ting
s.tr
igch
anne
lol
dtr
igle
n=
len(
self
.sam
ples
[tri
gch
])
self
.sam
ples
[cha
nnel
].ext
end(
data
)30
ifch
anne
l==
trig
chan
dse
lf.s
etti
ngs.
trig
mod
ein
(TR
UN
,TSI
NG
LE):
#if
we
have
new
data
for
the
trig
gere
dch
anne
l,an
alyz
eit
self
.trig
even
ts.e
xten
d(35
find
trig
even
ts(
data
,ol
dtr
igle
n,se
lf.s
etti
ngs.
trig
leve
l,se
lf.s
etti
ngs.
trig
cond
itio
n))
40
trig
sam
ple
=0
min
len
=m
in([
len(
self
.sam
ples
[c])
for
cin
self
.set
ting
s.ac
tive
chan
s])
45
for
i,e
inen
umer
ate(
self
.trig
even
ts):
if(m
inle
n−
e)<
self
.set
ting
s.ti
me
wid
th:
for
eein
rang
e(i,
len(
self
.trig
even
ts))
:se
lf.tr
igev
ents
[ee]−
=tr
igsa
mpl
e50
dels
elf.t
rig
even
ts[0
:i]br
eak
trig
sam
ple
=e
ifle
n(se
lf.s
ampl
es[t
rig
ch])
>10∗s
elf.s
etti
ngs.
tim
ew
idth
:55
#no
trig
even
tfou
nd,d
elet
eol
dsa
mpl
espr
int”
delo
ldsa
mpl
es”
trig
sam
ple=
len(
self
.sam
ples
[tri
gch
])−
self
.set
ting
s.ti
me
wid
thse
lf.tr
igev
ents
=[]
60fo
rc
inse
lf.s
etti
ngs.
acti
vech
ans:
dels
elf.s
ampl
es[c
][:tr
igsa
mpl
e]
elif
self
.set
ting
s.tr
igm
ode
==T
NO
NE:
for
chin
data
.key
s():
46
65de
lsel
f.sam
ples
[ch]
[:−se
lf.s
etti
ngs.
tim
ew
idth
]
def
get
sam
ples
(sel
f):
for
cin
self
.set
ting
s.ac
tive
chan
s:se
lf.g
etch
anne
lsa
mpl
es(c
)70
def
get
chan
nel
sam
ples
(sel
f,ch
):#
trig
ger
type
ttyp
e=
self
.set
ting
s.tr
igm
ode
swid
th=
self
.set
ting
s.ti
me
wid
th75
iftt
ype
==T
NO
NE:
self
.set
ting
s.ch
anne
ls[c
h].s
ampl
es=
self
.sam
ples
[ch]
else
: iftt
ype
==T
RU
N:
80se
lf.s
etti
ngs.
chan
nels
[ch]
.sam
ples
=se
lf.s
ampl
es[c
h][:s
wid
th]
elif
ttyp
e==
TST
OP:
self
.set
ting
s.ch
anne
ls[c
h].s
ampl
es=
self
.sam
ples
[ch]
[−sw
idth
:]de
lsel
f.sam
ples
[ch]
[:]
spi.p
y
impo
rtlo
ggin
g,ti
me
from
confi
gim
port∗
card
=N
one
5
def
init
(han
dle)
:gl
obal
card
card
=ha
ndle
10de
fse
ndO
scill
ator
(oct
,dac
,cnf
=2)
:””
”Sen
dda
tato
osci
llato
rch
ip.
f=2ˆ
oct∗
2078
[Hz]
/(2−
dac/
1024
)
15Se
eLT
C69
03da
tash
eetf
orde
taile
dm
eani
ngof
para
met
ers.
Doe
sno
tcal
lsen
dDat
a().”
””
card
.cle
arBi
t(BA
SEA
DD
RES
S,SP
IC
LK)
card
.cle
arBi
t(BA
SEA
DD
RES
S,SP
IO
SCI
CS)
20
shif
tBit
s(0,
oct,
4)sh
iftB
its(
0,da
c,10
)sh
iftB
its(
0,cn
f,2)
25ca
rd.s
etBi
t(BA
SEA
DD
RES
S,SP
IO
SCI
CS)
def
send
DA
C(c
hann
el,d
ata,
com
man
d=
3):
”””S
end
data
toD
AC
.
30D
efau
ltco
mm
and
=3
isto
wri
tevo
ltag
eda
taan
dpo
wer
upD
AC
.Se
eLT
C26
30da
tash
eet.
Doe
sno
tcal
lsen
dDat
a().”
””
card
.cle
arBi
t(BA
SEA
DD
RES
S+ch
anne
l,SP
IC
LK)
card
.cle
arBi
t(BA
SEA
DD
RES
S+ch
anne
l,SP
ID
AC
CS)
35
shif
tBit
s(ch
anne
l,co
mm
and,
4)sh
iftB
its(
chan
nel,
0,4)
shif
tBit
s(ch
anne
l,da
ta,1
2)sh
iftB
its(
chan
nel,
0,4)
40
card
.set
Bit(
BASE
AD
DR
ESS+
chan
nel,
SPI
DA
CC
S)
def
shif
tBit
s(ch
anne
l,va
lue,
bits
):fo
rii
nra
nge(
bits
):45
ifva
lue&
(2∗∗
(bit
s−1)
):ca
rd.s
etBi
t(BA
SEA
DD
RES
S+ch
anne
l,SP
ID
IN)
else
: card
.cle
arBi
t(BA
SEA
DD
RES
S+ch
anne
l,SP
ID
IN)
clkT
oggl
e(ch
anne
l)50
valu
e<
<=
1
def
clkT
oggl
e(ch
anne
l):
card
.cle
arBi
t(BA
SEA
DD
RES
S+
chan
nel,
SPI
CLK
)ca
rd.s
etBi
t(BA
SEA
DD
RES
S+
chan
nel,
SPI
CLK
)
ious
b.py
impo
rtar
ray,
tim
e,us
b,lo
ggin
gfr
omco
nfig
impo
rt∗
from
sam
pleo
psim
port
usb
bulk
read
1
47
5cl
ass
IOD
evic
e(ob
ject
):
”””C
omm
unic
ate
wit
hth
eU
SBca
rdde
velo
ped
byFa
briz
ioLo
Con
te.
The
nam
esof
the
met
hods
corr
espo
ndm
ostl
yto
thos
ein
Fabr
izio
’s10
CU
SBC
ontr
ol.c
pp.B
uffe
rle
ngth
sar
eno
tgiv
enin
argu
men
tsas
the
leng
thof
the
listi
sde
fined
impl
icit
lyin
Pyth
on.
”””
def
init
(sel
f):
15se
lf.d
ev=
self
.find
Dev
ice(
)
ifno
tsel
f.dev
:ra
ise
NoI
nter
face
Erro
r()
20se
lf.h
andl
e=
self
.dev
.ope
n()
try:
self
.han
dle.
clai
mIn
terf
ace(
self
.intf
)ex
cept
usb.
USB
Erro
r:ra
ise
Inte
rfac
ePer
mis
sion
sErr
or()
25
self
.bul
kIn
=BU
LKIN
EPse
lf.b
ulkO
ut=
BULK
OU
TEP
logg
ing.
info
(”D
evic
eop
ened
OK
”)
30se
lf.w
rite
Buff
er=
[]se
lf.r
eadB
uffe
r=
[]se
lf.r
eadR
eque
sts
=[]
self
.cur
rent
GPI
FCou
nt=
0se
lf.la
stw
ritt
en=
35
def
del
(sel
f):
try:
logg
ing.
info
(”cl
osin
gU
SBin
terf
ace.
..”)
self
.han
dle.
rele
aseI
nter
face
(sel
f.int
f)40
dels
elf.h
andl
eex
cept
:pa
ss
def
findD
evic
e(se
lf):
45””
”Ret
urn
inte
rfac
eha
ndle
ofU
SBca
rd””
”fo
rbu
sin
usb.
buss
es()
:fo
rde
vin
bus.
devi
ces:
ifde
v.id
Vend
or==
VEN
DID
and
dev.
idPr
oduc
t==P
RO
DID
:lo
ggin
g.in
fo(”
IOca
rdfo
und,
tryi
ngto
confi
gure
...”)
50se
lf.in
tf=
dev.
confi
gura
tion
s[0]
.inte
rfac
es[0
][0]
logg
ing.
debu
g(”I
nter
face
nr:%
scl
ass:
%s
subc
lass
:%s
prot
ocol
:%s”
,se
lf.in
tf.in
terf
aceN
umbe
r,se
lf.in
tf.in
terf
aceC
lass
,55
self
.intf
.inte
rfac
eSub
Cla
ss,
self
.intf
.inte
rfac
ePro
toco
l)re
turn
dev
def
addD
ataT
oWri
teBu
ffer
(sel
f,ad
dres
s,da
ta):
60””
”Que
ueda
tafo
rw
riti
ng””
”se
lf.w
rite
Buff
er.a
ppen
d(le
n(da
ta))
self
.wri
teBu
ffer
.app
end(
addr
ess)
self
.wri
teBu
ffer
.ext
end(
data
)se
lf.la
stw
ritt
en[a
ddre
ss]=
data
[−1]
65
def
addD
ataT
oRea
dBuf
fer(
self
,cou
nt,a
ddre
ss,c
allb
ack)
:””
”Que
uere
adre
ques
ts””
”
req
=R
eque
st()
70re
q.co
unt=
coun
tre
q.ad
dres
s=
addr
ess
req.
callb
ack
=ca
llbac
kse
lf.r
eadR
eque
sts.
appe
nd(r
eq)
75se
lf.r
eadB
uffe
r.ap
pend
(cou
nt)
self
.rea
dBuf
fer.
appe
nd(a
ddre
ss)
self
.cur
rent
GPI
FCou
nt+=
coun
t+2
def
send
Dat
a(se
lf):
80””
”Sen
dda
tain
queu
e”””
tose
nd=
[]
read
len
=le
n(se
lf.r
eadB
uffe
r)if
read
len
>0:
85to
send
.app
end(
read
len)
48
tose
nd.a
ppen
d(0x
FFFF
)to
send
.ext
end(
self
.rea
dBuf
fer)
tose
nd.e
xten
d(se
lf.w
rite
Buff
er)
90
self
.wri
te(t
osen
d)
ifre
adle
n>
0:se
lf.in
Dat
a=
usb
bulk
read
1(se
lf.h
andl
e,95
2∗se
lf.c
urre
ntG
PIFC
ount
)se
lf.s
ortI
nDat
a()
self
.wri
teBu
ffer
=[]
self
.rea
dBuf
fer
=[]
100
self
.cur
rent
GPI
FCou
nt=
0
def
sort
InD
ata(
self
):””
”Cal
lcal
lbac
kfu
ncti
onfo
rev
ery
rece
ived
data
bloc
k”””
for
req
inse
lf.r
eadR
eque
sts:
105
#fir
sttw
ow
ords
are
notu
sed,
igno
reth
emre
q.ca
llbac
k(re
q.ad
dres
s,se
lf.in
Dat
a[2:
req.
coun
t+2]
)de
lsel
f.inD
ata[
:req
.cou
nt+2
]se
lf.r
eadR
eque
sts
=[]
110
def
wri
te(s
elf,
buff
er,t
imeo
ut=
200)
:#
buffe
ris
a16
bita
rray
butw
ene
edto
wri
te8b
it#
ther
efor
ew
eco
nver
titt
oa
stri
ngb
=ar
ray.
arra
y(’H
’,bu
ffer
).tos
trin
g()
self
.han
dle.
bulk
Wri
te(s
elf.b
ulkO
ut,b
,tim
eout
)11
5
def
setB
it(s
elf,
addr
ess,
bit)
:””
”Set
asp
ecifi
cbi
t.”””
wor
d=
self
.last
wri
tten
[add
ress
]|(1
<<
bit)
self
.add
Dat
aToW
rite
Buff
er(a
ddre
ss,[
wor
d])
120
def
clea
rBit
(sel
f,ad
dres
s,bi
t):
”””C
lear
asp
ecifi
cbi
t.”””
wor
d=
self
.last
wri
tten
[add
ress
]&˜(
1<<
bit)
self
.add
Dat
aToW
rite
Buff
er(a
ddre
ss,[
wor
d])
125
def
repe
at(s
elf,
addr
ess)
:
”””R
e−se
ndth
ela
stva
lue.
”””
self
.add
Dat
aToW
rite
Buff
er(a
ddre
ss,[
self
.last
wri
tten
[add
ress
]])
130
clas
sR
eque
st(o
bjec
t):p
ass
clas
sN
oInt
erfa
ceEr
ror(
Exce
ptio
n):p
ass
clas
sIn
terf
aceP
erm
issi
onsE
rror
(Exc
epti
on):
pass
mai
n.py
#!/u
sr/b
in/e
nvpy
thon
impo
rtlo
ggin
g,th
read
,tim
e,sy
s,w
x
5im
port
cont
rols
fram
e,dr
aww
indo
w,d
so,s
etti
ngs,
trig
ger
from
com
mon
defs
impo
rt∗
from
confi
gim
port∗
clas
sTr
aces
Fram
e(w
x.Fr
ame)
:10
def
init
(sel
f):
wx.
Fram
e.in
it(s
elf,
pare
nt=N
one,
titl
e=”D
SO”,
size
=(10
00,5
12))
self
.win
dow
=dr
aww
indo
w.D
raw
Win
dow
(sel
f,se
ttin
gs)
self
.tim
er=
wx.
Tim
er(s
elf,
id=1
)15
wx.
EVT
TIM
ER(s
elf,
1,se
lf.n
ewD
raw
ing)
self
.tim
er.S
tart
(50)
#20
imag
es/s
econ
d
def
new
Dra
win
g(se
lf,e
vent
):tr
igge
r.ge
tsa
mpl
es()
20se
lf.w
indo
w.u
pdat
eDra
win
g()
clas
sA
pp(w
x.A
pp):
def
OnI
nit(
self
):fr
ameT
race
s=
Trac
esFr
ame(
)25
fram
eTra
ces.
Show
()
fram
eCon
trol
s=
cont
rols
fram
e.Fr
ame(
sett
ings
)fr
ameC
ontr
ols.
Show
()
30fr
ameT
race
s.Bi
nd(w
x.EV
TC
LOSE
,sel
f.OnE
xit)
fram
eCon
trol
s.Bi
nd(w
x.EV
TC
LOSE
,sel
f.OnE
xit)
49
retu
rnTr
ue
35de
fO
nExi
t(se
lf,e
vent
=Non
e):
sett
ings
.hal
t.acq
uire
()lo
ggin
g.in
fo(”
Wai
ting
for
acqu
isit
ion
thre
adto
rese
tdev
ice.
..”)
tim
e.sl
eep(
0.5)
logg
ing.
info
(”G
ood−
bye!
”)40
sys.
exit
()
sett
ings
=se
ttin
gs.S
etti
ngs(
)se
ttin
gs.c
hann
els[
0].a
ctiv
e=
True
sett
ings
.cha
nnel
s[1]
.act
ive
=Fa
lse
45se
ttin
gs.tr
igch
anne
l=0
trig
ger
=tr
igge
r.Tr
igge
r(se
ttin
gs)
logg
ing.
basi
cCon
fig(l
evel
=get
attr
(log
ging
,LO
GLE
VEL
))50
def
mai
n():
thre
ad.s
tart
new
thre
ad(d
so.D
SO()
.sta
rt,(
trig
ger.
callb
ack,
sett
ings
))A
pp()
.Mai
nLoo
p()
55m
ain(
)
sam
pleo
ps.c
#inc
lude
<st
dio.
h>#i
nclu
de<
stdl
ib.h
>#i
nclu
de<
usb.
h>#i
nclu
de”P
ytho
n.h”
5
type
def
stru
ctPy
usb
Dev
iceH
andl
e
PyO
bjec
tH
EAD
usb
dev
hand
le∗d
evic
eHan
dle;
inti
nter
face
Cla
imed
;10
Pyus
bD
evic
eHan
dle;
#defi
neFI
FOEM
PTY
MA
SK(1
<<
9)#d
efine
FIFO
FULL
MA
SK(1
<<
10)
#defi
neU
SBR
EAD
TIM
EOU
T10
0
15#d
efine
BULK
INEP
0x86
#defi
neM
AX
WR
ITE
BUFF
ER10
24
stat
icPy
Obj
ect∗
usb
bulk
read
1(Py
Obj
ect∗
self
,PyO
bjec
t∗ar
gs)
20
ints
ize
=0;
Pyus
bD
evic
eHan
dle∗h
andl
e;
if(!P
yArg
Pars
eTup
le(a
rgs,
”Oi”
,&ha
ndle
,&si
ze))
25re
turn
NU
LL;
char∗b
uffe
r=
mal
loc(
size
);if
(!buf
fer)
retu
rnN
ULL
;
30Py
BEG
INA
LLO
WTH
REA
DS
size
=us
bbu
lkre
ad(h
andl
e−>
devi
ceH
andl
e,BU
LKIN
EP,b
uffe
r,si
ze,U
SBR
EAD
TIM
EOU
T);
PyEN
DA
LLO
WTH
REA
DS
35Py
Obj
ect∗
ret=
NU
LL;
if(s
ize
<0)
PyEr
rSe
tStr
ing(
PyEx
cR
unti
meE
rror
,”U
SBre
ader
ror”
);
else
inti
;40
uin
t16
t∗bu
fptr
=(u
int1
6t∗
)buf
fer;
ret=
PyLi
stN
ew(s
ize/
2);
for
(i=0
;i<
size
/2;i
++)
PyLi
stSE
TIT
EM(r
et,i
,PyI
ntFr
omLo
ng((
int)
bufp
tr[i
]));
45
free
(buf
fer)
;re
turn
ret;
PyO
bjec
t∗re
sult
;50
stat
icPy
Obj
ect∗
chec
ksam
ples
(PyO
bjec
t∗se
lf,P
yObj
ect∗
args
)
PyO
bjec
t∗da
ta;
if(!P
yArg
Pars
eTup
le(a
rgs,
”O”,
&da
ta))
55re
turn
NU
LL;
50
unsi
gned
inti
,s;
intl
en=
PyLi
stSi
ze(d
ata)
;
60fo
r(i=
0;i<
len;
i++)
s=
PyIn
tA
SLO
NG
(PyL
ist
GET
ITEM
(dat
a,i)
);if
(!(s
&FI
FOFU
LLM
ASK
))
PyEr
rSe
tStr
ing(
PyEx
cR
unti
meE
rror
,”FI
FOfu
ll”);
retu
rnN
ULL
;65
PyLi
stSe
tIte
m(r
esul
t,i,
PyIn
tFr
omLo
ng(s
&0x
1ff)
);if
(!(s
&FI
FOEM
PTY
MA
SK))
i++;
brea
k;70
Py
DEC
REF
(dat
a);
retu
rnPy
List
Get
Slic
e(re
sult
,0,i
);
75
stat
icPy
Obj
ect∗
find
trig
even
ts(P
yObj
ect∗
self
,PyO
bjec
t∗ar
gs)
st
atic
intp
rev
=10
000;
80Py
Obj
ect∗
data
;in
told
trig
len,
leve
l,tc
ond;
PyA
rgPa
rseT
uple
(arg
s,”O
iii”,
&da
ta,&
old
trig
len,
&le
vel,
&tc
ond)
;
PyO
bjec
t∗re
sult
=Py
List
New
(0);
85
intl
en=
PyLi
stSi
ze(d
ata)
,i,s
;
for
(i=0
;i<
len;
i++)
s=
PyIn
tA
SLO
NG
(PyL
ist
GET
ITEM
(dat
a,i)
);90
if(t
cond
?((
prev
>le
vel)
&&
(s<
=lev
el))
://fa
lling
edge
?((
prev
<le
vel)
&&
(s>
=lev
el))
)//r
isin
ged
ge?
PyLi
stA
ppen
d(re
sult
,PyI
ntFr
omLo
ng(i
+old
trig
len)
);95
prev
=s;
retu
rnre
sult
;
100
stat
icPy
Met
hodD
efsa
mpl
eops
met
hods
[]=
”ch
ecks
ampl
es”,
chec
ksam
ples
,MET
HVA
RA
RG
S,N
ULL,
”fin
dtr
igev
ents
”,fin
dtr
igev
ents
,MET
HVA
RA
RG
S,N
ULL,
”us
bbu
lkre
ad1”
,usb
bulk
read
1,M
ETH
VAR
AR
GS,
NU
LL,
105
NU
LL,N
ULL
/∗se
ntin
el∗/
; PyM
OD
INIT
FUN
Cin
itsa
mpl
eops
(voi
d)
110
fput
s(”U
sing
Csa
mpl
ean
alys
isfu
ncti
ons\
n”,s
tder
r);
resu
lt=
PyLi
stN
ew(1
020)
;
PyIn
itM
odul
e3(”
sam
pleo
ps”,
sam
pleo
psm
etho
ds,N
ULL
);11
5 co
nfig.
py
#U
SBde
vice
vend
orID
VEN
DID
=0x
04b4
#U
SBde
vice
prod
uctI
D5
PRO
DID
=0x
1004
#U
SBde
vice
bulk
inen
dpoi
ntBU
LKIN
EP=
0x86
10#
USB
devi
cebu
lkou
tend
poin
tBU
LKO
UT
EP=
0x02
USB
REA
DT
IMEO
UT
=10
0
15BA
SEA
DD
RES
S=
0xA
100
REA
DBU
FFER
SIZ
E=
4096
WR
ITE
BUFF
ERSI
ZE
=40
96M
AX
GPI
FC
OU
NT
ER=
6553
5
51
20#
I/O
pins
FIFO
RS
=0
GA
IN5
=4
GA
IN20
=5
AT
TEN
10=
625
ATT
EN10
MA
SK=
2∗∗A
TTEN
10A
CD
C=
7FI
FOEM
PTY
=9
FIFO
EMPT
YM
ASK
=2∗∗F
IFO
EMPT
YFI
FOFU
LL=
1030
FIFO
FULL
MA
SK=
2∗∗F
IFO
FULL
#SP
Ipin
sSP
IC
LK=2
SPI
DIN
=335
SPI
OSC
IC
S=8
SPI
DA
CC
S=1
TIM
EW
IDT
H=
500
40M
AX
OFF
SET
=40
95M
AX
OFF
SET
VO
LTA
GE
=2.
5M
AX
SAM
PLE
VALU
E=
511
MA
XFR
EQU
ENC
Y=
1100
0FR
EQD
IV=
1645
#lo
gle
vel
LOG
LEV
EL=
”DEB
UG
”
52
Appendix B
Software user’s guide
B.1 GNU/Linux
The following programs and libraries are required to run the program:
• Python 2.4 or higher (http://python.org)
• wxPython 2.6.* or 2.8.* (http://wxpython.org)
• wxWidgets (http://wxwidgets.org)
• pyusb (http://pyusb.berlios.de)
• libusb (http://libusb.sf.net)
On a Debian or Ubuntu system, these can be installed by issuing the following command:
sudo apt-get install python-pyusb python-wxgtk2.8
By default, a Linux system does not permit the direct usage of a USB device for any user. Theprogram will abort with an error message. There are two solutions: log in as the “root” user, orallow USB access for normal users. The latter can be done by copying the file software/linux/90-cypressio.rules from the CD to the directory /etc/udev/rules.d.
B.2 Microsoft Windows
The use of the software requires a driver which is incompatible with the driver normally usedwith Cypress USB devices. The Cypress driver must be completely removed before installingthe new driver, which is located on the CD in the software/windows/ directory.
53
Appendix C
Schemata
54
C10
1
47n
C10
2
220p
C10
3
27p
R10
1
30
R10
2
1M8
R10
3
1M8
R10
4
100k
2
1
CO
NN
101
D10
1
3VD10
2
3V
R10
5
62 R10
6 62
R10
7
3k9
R10
8
1k
−3.
3V
+3.
3V
+3.
3V
−3.
3V
D10
5
R10
9
20R
110
3k3
DC
OF
FS
ET
D10
6
adju
st to
24p
4
R11
112
k
R11
2
3k
R11
3
1k2
R11
41k
R11
5 1k
gain
=5
gain
=20
R11
76k
8R
118
2k4
+3.
3V
−3.
3V
3 4
15
V+ 2
V−
U10
1
AD
8065
CO
M13
NC
10
NO
16
IN9
MA
X45
47
U10
4
CO
M5
NC
8
NO
2
IN1
MA
X45
47
U10
4
675
18
OM
RO
N G
6K
K10
2
GA
IN5
GA
IN20
AC
/DC
:10
R11
9
20
3 2
6
7 V+
4V−
LT62
00
U10
5
+3.
3V
−3.
3V
3 2
6
7 V+
4V−
LT62
00
U10
3
+3.
3V
−3.
3V
+3.
3V
−3.
3V
R12
0
1k2
324
18
OM
RO
N G
6K
K10
1
C10
4
100n
−3.
3V
+3.
3VC
105
100n
for
AD
8065
C10
6
100n
−3.
3V
+3.
3VC
107
100n
for
AD
8062
R12
1
20
R12
2
20
C10
8
100n
−3.
3V
+3.
3VC
109
100n
for
LT62
00
NC
3 2
18
V+ 4
V−
U10
2
AD
8062
5 6
78
V+ 4
V−
U10
2
AD
8062
AD
CIN
C11
0
100n
−3.
3V
+3.
3VC
111
100n
for
MA
X45
47
−3.
3V
R12
3
330
D10
3
LM40
40
Z10
1
Figu
reC
.1:A
nalo
gst
age
55
SA
1S
A2
SA
3S
A4
SA
5S
A6
SA
7S
A8
SA
9
SA
5S
A1
SA
2S
A3
SA
4S
A6
SA
7S
A8
SA
9
+3.
3V
R20
1
51
C20
1
100n
C20
2
2u2
C20
3
22p
CLK
D08
D07
D06
D05
D03
D02
D01
D00
D04
AD
CIN
CLK
FIF
OR
S
WR
ITE
FE
MP
TY
FF
ULL
MA
X14
44
RE
FN
1
CO
M2
VD
D3
GN
D 4
GN
D 5
IN+
6
IN−
7
GN
D 8VD
D9
VD
D10
GN
D 11
CLK
12
PD
13
GN
D 14
OE
15
D9
16
D8
17
D7
18
D6
19
D5
20
OV
DD21
TP
22
OG
ND
23
D4
24
D3
25
D2
26
D1
27
D0
28
RE
FO
UT
29
GN
D 30
RE
FIN
31
RE
FP
32
U20
1
NC
NC
R20
2
51
C20
4
100n
C20
5
22p
C20
610
0n
C20
710
0n
C20
8
100n
R20
3
10k
C20
9
100n
C21
0
2u2
IDT
72V
05
W2
D8
3
D3
4D
25
D1
6D
07
XI
8
FF
9
Q0
10
Q1
11
Q2
13
Q3
14
Q8
15
GN
D 16
R18
Q4
19
Q5
20
Q6
21
Q7
22
XO
/HF
23
EF
24
RS
25
FL/
RT
26
D7
28D
629
D5
30D
431
VC
C32
U20
2
NC
Vcc
Vcc
Vcc
Figu
reC
.2:A
DC
and
FIFO
56
CS
DA
CLT
C26
30
VC
C4
GN
D 5
SD
I3
SC
LK2
CS
1
VO
UT
6
U30
1
+3.
3V
DC
OF
FS
ET
SC
LK
SD
IN
12
34
56
78
910
1112
1314
1516
1718
1920
U30
2D
00D
01
D02
D03
D04
D05
D06
D07
D08
D09
D10
RE
AD
WR
ITE
CLK
+3.
3V
−3.
3V
D00
D01
D02
D03
D04
D05
AC
/DC
:10
SC
LK
SD
IN
CS
DA
C
GA
IN5
FIF
OR
S
GA
IN20
D06
D07
RE
AD
2A
3Y
1E
N
7412
5U
304
5A
6Y
4E
N
7412
5U
304
FE
MP
TY
FF
ULL
WR
ITE
D09
D10
Vcc
C30
110
0n
1O
UT
21D
32D
43D
54D
65D
76D
87D
98D
191Q
182Q
173Q
164Q
155Q
146Q
137Q
128Q
11C
LK
7457
4U
305
Figu
reC
.3:P
er-c
hann
elbu
slo
gic
and
DA
C
57
SC
LK
SD
IN
CS
CLK
LTC
6903
GN
D 1
SD
I2
SC
K3
SE
N4
CLK
5
CLK
6O
E7
V+8
U50
1
Vcc
NC
C50
110
n
CLK
C50
21u
24
74LV
C1G
04
U50
2
Figu
reC
.4:C
lock
gene
rati
on
58
2
34
1 5
109
87
6 18 20
17 19
1615
1413
1211
22
2324
21 25
3029
2827
26 38 40
37 39
3635
3433
3231
J401
A00
A02
A04
A06
A08
A10
A12
A14
A15
A13
A11
A09
A07
A05
A03
A01
A15
A14
A13
A12
A11
A10
A09
A08
D07
D05
D03
D01
D15
D13
D11
D09
D06
D04
D02
D00
D14
D12
D10
D08
D02
D03
D08
NC
NC
NC
NC
NC
SC
LK
SD
IN
CS
CLK
EN
OU
TR
/W
AD
DR
NC
NC
12
7404U40
2
AD
DR
R/W
R/W
56
7404U40
2
98
7404
U40
2
EN
OU
TB
US
RE
AD
EN
OU
T
12
34
56
78
910
1112
1314
1516
1718
1920
U40
71
2
34
56
78
910
1112
1314
1516
1718
1920
U40
8D
00D
01
D02
D03
D04
D05
D06
D07
D08
D09
D10
RE
AD
1W
RIT
E1
CLK
Vdd
+3.
3V
−3.
3V
WR
ITE
1
WR
ITE
2
BU
SR
EA
D
BU
SW
RIT
E
D01
D03
D05
D07
D09
WR
ITE
2V
dd
+3.
3V
D00
D02
D04
D06
D08
D10
RE
AD
2
CLK −3.
3V
NC
NC
NC
addr
ess
mas
k
= 0
xA1_
_
C40
1
270p
12
131 2
7410
U40
3
6
53 4
7410
U40
3
falli
ng: w
rite
to b
us
risin
g: r
ead
from
the
bus
NC
NC
1G
1
2A
1
3B
1
41Y
0
51Y
1
61Y
2
71Y
3
15G
2
14A
2
13B
2
122Y
0
112Y
1
102Y
2
92Y
3
7413
9U
404
dem
ultip
lexe
r w
/ ina
ctiv
e−hi
gh o
ut
A00
A01
BU
SR
EA
D
RE
AD
4
WR
ITE
3
WR
ITE
4
98
7404
U40
5
56
7404
34
7404
12
7404
RE
AD
1
RE
AD
2
RE
AD
3
NC
1E
N
2A
0
4A
1
6A
2
8A
3
11A
4
13A
5
15A
6
17A
7
3B
0
5B
1
7B
2
9B
3
12B
4
14B
5
16B
6
18B
7
19A
=B
7452
1U
401
1O
UT
21D
32D
43D
54D
65D
76D
87D
98D
191Q
182Q
173Q
164Q
155Q
146Q
137Q
128Q
11C
LK
7457
4U
406
BU
SR
EA
D
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
12
34
56
78
910
1112
1314
1516
1718
1920
U40
91
2
34
56
78
910
1112
1314
1516
1718
1920
U41
0D
00D
01
D02
D03
D04
D05
D06
D07
D08
D09
D10
RE
AD
3W
RIT
E3
CLK
Vdd
+3.
3V
−3.
3V
D01
D03
D05
D07
D09
WR
ITE
4V
dd
+3.
3V
D00
D02
D04
D06
D08
D10
RE
AD
4
CLK −3.
3V
Vdd
1A
13Q
2B
14C
e3
CLR
15R
e/C
e
4Q
7412
3U
411
C40
247
p
R40
13k
3
Vcc
NC
R40
247
0
D40
1
BU
SW
RIT
E
D09
Vdd
Figu
reC
.5:B
usin
terf
ace
59
