Wafer Level System Integration · WLP LC-TB-BGA ULC-CSP stacked CSP 1997 S-CSP VSI Flex-Sys chip in...
Transcript of Wafer Level System Integration · WLP LC-TB-BGA ULC-CSP stacked CSP 1997 S-CSP VSI Flex-Sys chip in...
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Wafer Level System Integration
Oswin Ehrmann
Fraunhofer Institut forReliability and Microintegration
IZMD-13355 Berlin GermanyGustav-Meyer-Allee 25
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Outline• Introduction• Wafer Bumping and Flip Chip Bonding for ATLAS• Future Options and Requirements:
– Bump size and Pitch– Lead Free Bumping– Thin Silicon– Integration of Passives– 3D Integration
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Fraunhofer in profile
59institutes
12500employees(full-timeequivalence
1000 million Eurobugdet
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
• 250 Scientists and Engineers (+100 Students)/ Cleanroom 800 m2
• Applied Research and Development of Advanced Packaging Solutions for Microelectronics• Branch Labs and Centers in Chemnitz, Teltow, Paderborn, Oberpfaffenhofen and Munich• Worldwide Technology Transfer and Consulting Services
FraunhoferInstitutZuverlässigkeit undMikrointegration
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Fraunhofer Institut for Reliability and Microintegration IZM
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Front End
Back End
Electronic Packaging
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Front End Wafer
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Packaging Roadmap
COF/FCOB
QFP
SQFP
DIP
SO
VSO
SOJTFP
V-PAK
FC
CCC
stacked chips
stackedmodules
MCMCOB
PGA
VTFP
CSP
FC-MCM
BGA
TB-BGA MC-BGA
2000till2004
WLP
LC-TB-BGA
ULC-CSP
stacked CSP
1997
S-CSPVSI
Flex-Sys
chip in polymer
Polytronic
19981999
thin silicon
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Chip on BoardSi-Chip
Si-Chip
Substrat
Substrat
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Flip Chip
Si-Chip
Si-Chip
Si-Chip
Substrat
Bump
Si-Chip
Substrat
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
ECD Bumping at IZM
Gold
AuSn
PbSn
SnAg
Cu - CuSn
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Processflow PbSn-Bumping using Electroplating
Resist Stripping and wet Etchingof the Plating Base
Sputter Etching and Sputteringof the Plating Base / UBM
Spin Coating and Printingof Photoresist
Electroplating of Cu and PbSn
Reflow
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Sputter Etching
Sputtering of Plating Base / UMB
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Photolithographie
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
ElectroplatingConstruction Scheme of the Electrolytic Cell of a Rack Plater
A B
C
D E
F
G
A: Anode
B: Spray Tubes
C: Shielding
D: Wafer
E: Overflow
F: ImmersionHeater
G: Level Switch
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Electroplating EquipmentSemitool Equinox
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
ATLAS Detektor Large Hadron Collider (CERN)
Length: 50 m
Diameter: 25 m
Weight: 7000 t
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Thin-Film-Multichipmodul
Size 22 x 64 mm²
Silicon Sensor
16 Readout ICs (KGD)
46 080 IO-Bumps pitch 50 µm,
electroplated SnPb
ATLAS Pixel Detector Module
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Fundamental Construction of Bumps on ATLAS Detector Chips25 µm electroplated PbSn63
300 nm sputtered Cuas plating base
200 nm sputtered Ti:Was adhesion layer
and diffusion barrier
Al chip pad withoverlapped passivation
5 µm electroplated Cuas solderable base
12 µm20 µm26 µm 20 µm
as plated after reflow
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
High Density ECD Bumping & Flip ChipIBM 0.25 µm rad tolerant design
44““
2800 Bumps / chipsize / pitch :30 µm / 50 µm
88““
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
ATLAS FE-I3 CMOS IC
98 Readout Chipwafer
200 mm Si-Wafer, CMOS 0.25µ Technology
288 tested Chips per Wafer
Chip Size: 7,4 x 11 mm²
EIectroplated I/O Bumps:~ 841 000 Bumps per Wafer, Ø 25µm
Plating Base: Ti:W/Cu
UBM: Cu
Solder: Sn60Pb40
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Bumped FE-I Chip
IBM 0.25 µm rad tolerant design
Chip with 9 column pairs
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
ParticleBump
PositionMissing Bump
Small Bump Large Bump
Defect Classes
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
020
4060
80100
120140
160180
2000 2005 2010 2015 2020
Year
Chi
p In
terc
onne
ct P
itch
[µm
]
area array
peripheral
Source: ITRS
IC Technology Roadmap: Chip Interconnect Pitch
ATLAS
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
ATLAS Si-Sensor Substrate Wafer520 Processed Sensor Wafer:
100 mm Silicon Wafer
Double side processed
Thickness 250 µm
3 sensor tiles with46080 pixel cells50 x 400(600) µm²
Electroplated Sensor Pixel Contacts :Pixelmetallization Al
Plating Base Ti:W/Cu
Pad 5 µm Cu + 1µm Ni + Au
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Bare Module Flip Chip Assembly
reflow:at 250°C, reductive atmosphere
flux deposition
rework:single die exchange of misplaced die, to many bridged bumps, die that failedelectrical test
inspection and measurements:x-ray inspection, electric module test
pick and place:FC150 of SüssMicrotech, Pick & Place Accuracy ≤ 3µm
readout chips, sensor tiles:test, inspection, classification
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Assembly of ATLAS Pixel Detector Modules16 ROC Flip-Chip Bonded to the Sensor46 080 electroplated SnPb IO-Bumps, Ø 25 µm, pitch 50 µm
Assembly of 1139 ATLAS ModulesAssembled Chips: ~ 19000 chipsModule Yield incl. rework: 97 %Chip Rework Rate: 0.7 %
Chip Yield after Bumping:20.720 processed Readout Chips
Class 1: perfect chips
Class 2: accepted defects(< 4 defective bumps, small particle, ...)
Calss 3: rejected chips(> 4 defective bumps, scratches, residues, plating defects,...)
98% der Module mit <10 Bumpdefekten
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
ATLAS Pixel Detector at LHC at CERN
ATLAS Detector Ø 25m Inner Detector Ø 2m
PIXEL Detector Ø 0.9mBare Module 22 x 64 mm²
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
ATLAS Pixel Detectorat LHC at CERN
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
ATLAS Pixel Detector at LHC at CERN
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
2 x 3
Detector Placquettes for CMS
1 x 1
1 x 3
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Future Requirements: Bump size and Pitch
Solder Bumping PbSn37/63 Diameter: 10 µm
Pitch: 20 µm
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Solder for MeltingFC Interconnects Point
SnBi 42/58 138°C
PbSn 37/63 183°C
SnZn 91/9 199°C
SnAg 96.5/3.5 221°C
SnCu 99.3/0.7 227°C
AuSn 80/20 280°C
PbSn 95/5 314°C
Future Requirements: Lead Free
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Meeting the requirements of future environmentally friendly lead-free flip chip interconnects basing on the EU-directive ROHS 2000
Bump dimensionsSize: 30 -100 µmPitch: down to 50 µmAg composition: 3.0 ~ 4.0 at.%Melting point: 221 °C
Lead Free Bumping
SnAg
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Lead Free BumpingSnAg
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
GaAs X-ray Pixel Detector
project partners: MPD, Fine Tech, FhG-IZFP, FhG-IZMfunded by: EFRE and the Free State of Saxony
Frontend Readout Chip
MEDIPIX 256x256 IOs
Pixel cell size 55 x 55 µm²
Chip size 14 x 14 mm²
SnAg Bumps Ø25 µm, more than 6 000 000 bumps/wafer
GaAs Sensor Chip
GaAs Detector 256x256 pixels
Pixel size 55 x 55 µm²
Chip size 16 x 16 mm²
Electroplated Cu-Pad, height 5 µm
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
GaAs Hybrid Pixeldetector: X-Ray Test
Pixeldetector assembled on MEDIPIX board and tested at FhG-IZFP
x-ray images of a spring and a screw using the 202x202 pixel detector prototyp(photography by FhG-IZFP)
project partners: MPD, Fine Tech, FhG-IZFP, FhG-IZMfunded by: EFRE and the Free State of Saxony
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
AuSn Bumping for RF- Devices -
AuSn Bumps on GaAs typ size
diameter: 40 µmHight: 30-40 µm
sp. AuTi:W(N)
ζ-phase
ep. Au
Chip Pad Pass.
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
AuSn Electroplated Bumps
• 50 µm pitch full array• 30 µm AuSn20• x-ray pixel detector
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Cu Pillar Bumps (Height: 80 µm, Diameter: 60 µm)
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Process Flow - Stencil Printing
Source:
Al bond pad Ni UBM Solder paste
Reflowed solder bumpCleaned solder bump
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Solder Bumping by Stencil Printing
150 µm pitch 500 µm pitch
Electroless Ni + Solder Printing
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Waferbumping by C4NP
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Waferbumping by C4NP
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Waferbumping by C4NP
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Waferbumping by C4NP
• Bumping of thinned wafers• Bumping of wafers with vias (stacking)• Solder with 3 or more components • Fine Pitch Bumping
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
ELASTec®
Source: Infineon
J-shaped planar microspring
Source: Georgia Tech
Source: NanoNexus,
Xerox Co., PARC
ClawConnect™ made of StressedMetall™:
Elastic Contact Structures
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
„Nano“- structured
Bump surface
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Thin Film Build Up for the Realization of PassivesBuild up for the realization of all three passivetypes
Future Requirements: Integration of Passive Components
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Future Requirements: Integration of Passive Components
R = 1kΩ
R = 5kΩ
thinfilm resistors thinfilm inductors
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Thinning of bumped wafers:
180 µm
Future Requirements: Thin Silicon
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Future Requirements: Thin Silicon
Silicon becommes flexible when thickness is reduceddown to less than 30µm
• bending radius 1mm / 1µm thick-ness
• fully flexible and ultra thin systemsavailable
• best opportunities to proceed withFC and CSP technologies
• basis for 3D chip integration
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Dicing by Thinning
•Dry Etching of about 30µm deep groves•Backside Grinding - Etching - CMP
•nearly ideal chip edges (roundedcorners are possible)• shorter process times for singulationinto individual chips• narrow cuts save silicon area for smallchips•non rectangular dies are possible
Rounded chip corners
non-rectangular dies
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Wafer Level
3D Integration Technologies
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Stacking Technologies: Die-Stacking
Pyramid Stack Same Size Stack with Spacer
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Stacking Technologies: Die-Stacking
Through Silicon Via Die-Stack
Chip-in-Polymer Die-Stack
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Stacking Technologies: Wafer-Stacking
Yield !!!
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Pre Front End Process – Post Front End Process New Front End Process Restrictions in Process Parameters
Design Restrictions
Through Silicon Vias: Basic Questions
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Wafer Front Side Processing - Wafer Back Side Processing
Through Silicon Vias: Basic Questions
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Wafer-Level-Packaging for Optical Applications
• Tapered Vias & Streets
• controlled sidewall angle for sribe line
• controlled sidewall angle for via holes
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Ball Grid Array on the backsidewith Silicon Via Contacts
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Wafer-Level-Packaging for Optical Applications
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
TSV – Formation and Metallization
• Deep Via High Aspect Ratio Etching (h >20 µm – 80 µm)
• Side Wall Insulation
• Via Filling by Cu-CVD/
• Via Filling by Cu-Electroplating
• Via Filling by W - CVD
Through Silicon Vias
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Through Silicon Vias: Si Etching
Si Trench Etch 2.5 x 20 µm²
How Deep is the Via?
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
ICV-Dimensions: 3 µm x 10 µm x 50 µm
300 nm SACVD TEOS20 nm TiN CVD900 nm W CVD und W Backetch800 nm M1 (AlSiCu, structured) 850 nm PN/POX (Passiviation)
W- Fill of High Aspect Ratio TrenchThrough Silicon Vias: Via Filling
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
23,4 µm
Deep Inter-Chip ViasAR 20:1
W-Fill and Etch Back
SACVD Oxide
W (via-fill)
Through Silicon Vias: Via Filling
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Copper CVD
Through Silicon Vias: Via Filling
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Process flow– Fabrication of inter-chip vias with
standard wafer process sequence
– Simultaneous formation of electrical and mechanical connection
• Fabrication of Tungsten orCopper filled InterChip Vias on Top Substrate
• Via Opening and Metallization
• Thinning (20µm)
• Opening of Plugs
• Electroplating
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
MOCVD-TiN/WO3/TEOS Spacer
Therm. Oxide
TEOS
TEOSM2-AlSiCu
CMOS Top Wafer prior to Thinning
SACVD planarized ILD
10x2,5 µm ICVs
• ICVs 10 x 2,5 µm, 20 µm deep, AR 8:1
• Distance between W-filledICVs and Transistors: ~ 4 µm to Source/Drain Area~ 11 µm to Gate Area
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Alignment and Solderingto the Bottom Wafer
Process flowSimultaneous formation of electrical and
mechanical connection
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
- Thin SLID layers with large area contacts
- Modular concept - Suitable for chip-to-wafer stacking
• Integration densities up to 105
cm-2
Process flow
Alignment and Solderingof additional Top Chips
Technische Universität BerlinResearch Center of
Microperipheric Technologies
Department:High Density Interconnect & Waferlevel PackagingPhone: +49-(0)30-46403-124Fax: +49-(0)30-46403-123E-Mail: [email protected]
Fraunhofer Institut Zuverlässigkeit und Mikrointegration (IZM)
Dept. High Density Interconnect & Wafer Level Packaging
Gustav-Meyer-Allee 25, 13355 Berlin
Tel.: +49 (0) 30 464 03-124, Fax: -123
Technische Universität Berlin
Forschungsschwerpunkt Technologien der Mikroperipherik, TIB Sekr. 4/2-1
Gustav-Meyer-Allee 25, 13355 Berlin
Tel.: +49 (0) 30 314-72 882, Fax: -72835