Wafer Level Packaging - IEEEewh.ieee.org/soc/cpmt/presentations/cpmt0202a.pdf · Wafer Level...
Transcript of Wafer Level Packaging - IEEEewh.ieee.org/soc/cpmt/presentations/cpmt0202a.pdf · Wafer Level...
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Feb-02 1
Wafer Level PackagingL. Nguyen
National Semiconductor Corp.Santa Clara, CA
Acknowledgments: N. Kelkar, V. Patwardhan, C. Quentin, H. Nguyen, A. Negasi, E. Warner
IEEE CPMT Meeting, San Jose, CA
Feb-02 2
What is a WLP?• Significant confusion in the industry over the term
“wafer-level packaging”• Simple definition: “All packaging and interconnection
must be fabricated on the wafer prior to dicing” →Bumped chips are WLP?
• Differentiation: Are the devices packaged further prior to assembly?
• High I/O µPs and ASICs: chips are mounted on chip carriers before surface mount attachment → Not WLPs
• Small die and/or die with low I/O can be mounted directly on the final substrate → WLPs
2
Feb-02 3
Outline• CSP packaging trends• CSP migration toward wafer level processing• WL-CSP barriers and challenges• micro SMD package construction• Process / assembly flows• Package selection criteria• Future developments
– Lead-free– Wafer level underfill
• Conclusions• References
Feb-02 4
Outline• CSP packaging trends• CSP migration toward wafer level processing• WL-CSP barriers and challenges• micro SMD package construction• Process / assembly flows• Package selection criteria• Future developments
– Lead-free– Wafer level underfill
• Conclusions• References
3
Feb-02 5Source: Electronic Trend Publications 1999
Package Forecast
100 1000 10 4 10 5
4-18
20-32
36-68
72-100
104-144
148-208
212-304
308+
19982003
UNITS (M)
I/O R
AN
GE
Feb-02 6
Flip Chip Packages
0
200
400
600
800
1000
1997 1998 1999 2000 2001 2002
FCOBFCOOBGA FCCSP FCMCM FC
UN
ITS
(M)
YEAR
Definitions
Direct AttachFCOB - Flip Chip on BoardFCOO - Flip Chip on Other
In PackageBGA FC - FC in BGACSP FC - FC in CSP
(includes WL-CSP)MCM FC - FC in MCM
Source: Electronic Trend Publications 1999
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Feb-02 7
WLP Growth Projections
Source: TechSearch 2001
Total Packages
Source: Electronic Trend Publications 1999
0
5 105
1 106
1.5 106
2 106
2001 2002 2003 2004 2005
HighLow
YEAR
8-in
WA
FER
EQ
UIV
ALE
NT
Feb-02 8
STANDARD< 208 leadTO ⇒ SOP ⇒ MSOP ⇒ SOT ⇒ SC70PDIP ⇒ SOIC ⇒ TSSOP ⇒ CSP ⇒ CSP
(Leaded/Laminate) (Wafer)PLCC ⇒ QFP ⇒ TQFP ⇒ CSP> 208 leadPGA ⇒ BGA ⇒ BGA ⇒ FP-BGA
(1.27 mm) (1.0 mm) (0.8 mm)POWERTO220 ⇒ DPAK, D2PAK, TO263PACKAGE ENHANCEMENTS THERMAL Embedded heat slug ⇒ Drop-in HS ⇒ Exposed DAP
Shorted leads MQFPAluminum nitride EMC
ELECTRICAL Shorter leadsShorter wire bond ⇒ Exposed DAP ⇒ Solder bumpsMultiple wires
OPTICAL LCC ⇒ Pre-molded ⇒ CSPCustom Custom Custom
Form Factor Migration
5
Feb-02 9
Outline• CSP packaging trends• CSP migration toward wafer level processing• WL-CSP barriers and challenges• micro SMD package construction• Process / assembly flows• Package selection criteria• Future developments
– Lead-free– Wafer level underfill
• Conclusions• References
Feb-02 10
CSP Migration toward Wafer Level Packaging
• CSP applications are rapidly expanding with drivers in …– Flash memory– RAMBUS DRAM– Analog
• Evolution of CSP technology toward Wafer Level Packaging due to the following factors:– Batch fabrication of ICs in arrays– Test and burn-in in strip and array format; strip format has
continuously increased in manufacturing for higher throughput– Adaptability of some configurations to wafer level processing
more than others (e.g., possibility for die shrink)– Emergence of 0.5 mm pitch as the standard for CSPs in memory, µPs, DSPs, ASICs, and most consumer products
6
Feb-02 11
CSP for Portable Application… 1
Other applications:
Game Gear, Play Station, Portable Computers, etc..
Feb-02 12
CSP for Portable Application… 2
Handspring Visor Edge
(Integrated passive devices in Ultra CSP)
Casio Color Wristwatch/Camera(CPU in RealCSP by IEP Technologies)
7
Feb-02 13
Benefits of WL-CSPWafer Level-CSP can provide the following benefits:
– Batch processing to lower costs– Handling and shipping logistics can be streamlined
• Final test is done at the wafer level. Savings in test and logistics can be equally, or more important, than the manufacturing cost of the package
• ICs can be packaged in the fab and shipped directly to customers for surface mounting with conventional SMT; shortens TAT; lower assembly capital costs
• Ability to minimize inventory
– No need for Known Good Die - tested like other ICs– Functionality can be packed into a form factor as small
as the die– Wider pitch allows for wider UBM, taller bumps, and
better joint reliability
Feb-02 14
Outline• CSP packaging trends• CSP migration toward wafer level processing• WL-CSP barriers and challenges• micro SMD package construction• Process / assembly flows• Package selection criteria• Future developments
– Lead-free– Wafer level underfill
• Conclusions• References
8
Feb-02 15
Barriers and ChallengesLike any other new technologies, WL-CSP still faces a
number of hurdles ...• Infrastructure is not quite established• Wafer bumping is still too costly• High cost for poor yield wafers• High cost for low wafer bumping yields• Who should manufacture the WL-CSP (IC or bumping
house)• Die shrink strategy• Solder joint reliability is more critical (since underfill may
not be used in the application)
Feb-02 16
Users of WL-CSPs• USA
– FCD, Unitive, MCNC, Dallas Semi (1wire), Xicor (Shell BGA, Ultra CSP), National Semi (micro SMD), Atmel, CMD (Ultra CSP), Alpine Micro Systems (WALEP), TI (NanoStar)
• Europe– TU Berlin, IMEC, CS2
• Taiwan– Apack, Unitive Taiwan, ASE, SPIL, Chipbond, ShellCase (Xintec)
• Korea– Amkor, Hyundai
• Japan– IEP/Oki/Casio (Real CSP)– Fujitsu/Shinko (Super CSP)– Hitachi (WPP2)
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Feb-02 17
Outline• CSP packaging trends• CSP migration toward wafer level processing• WL-CSP barriers and challenges• micro SMD package construction• Process / assembly flows• Package selection criteria• Future developments
– Lead-free– Wafer level underfill
• Conclusions• References
Feb-02 18
Micro SMD• Micro SMD is a Wafer Level-Chip Scale Package• No interposer - the die is the package• Micro SMD has the following advantages:
– No need for underfill (although some OEMs use underfills for certain applications such as portable consumer products)
– Smallest footprint per I/O - savings in PCB estate– Leverage standard surface mount assembly technology– Cost-effective manufacturing and assembly– Matrix interconnect layout designed at 0.5 mm pitch– 0.9 mm maximum package height– Epoxy backcoating provides conventional black marking surfaces
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Feb-02 19
Package Construction
Micro SMD: 4, 5, 8, and 14 I/O
0.5 mm pitch; JEDEC Standard MO-211
0
1
2
3
4
5
6
7
8
TSSOP-14 MSOP-8 SOT23-5 SC70-5 microSMD-8
SMT PACKAGE TYPE
3 mm
1.5 mm
1.5 mm
5 mm
MSOP-8
5 mm
Comparison between various SMT
packages and the micro SMD
Feb-02 20
Package Construction
Cross-section of an 8 I/O micro SMD
bonded to an organic substrate
Cross-section of a solder ball
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Feb-02 21
Outline• CSP packaging trends• CSP migration toward wafer level processing• WL-CSP barriers and challenges• micro SMD package construction• Process / assembly flows• Package selection criteria• Future developments
– Lead-free– Wafer level underfill
• Conclusions• References
Feb-02 22
Process FlowIncoming wafer2nd passivation
Bumping
Back side coating
Laser mark
Test (Wafer sort)
Saw
Tape and reel
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Feb-02 23
Tape & Reel
Saw
Final Test
Marking
Backside Coating
Solder Bumping
Wafer Fab
micro SMD
Wafer Sort
Wafer Fab
Tray / Tape & Reel
Mark
Final Test
Trim & Form
Mold
Wire Bond
Die Attach
Saw
Conventional Package PQFP & TSSOP
Lead Plating
CSP
Wafer Sort
Wafer Fab
FinalSingulated
Test
Saw
Laser Mark
Mold
Wire Bond
Plasma Clean
Die Attach
Saw
Tape & Reel
5 process steps1 test step
7 process steps2 test steps
7 process steps2 test steps
Assembly Flows
Feb-02 24
Outline• CSP packaging trends• CSP migration toward wafer level processing• WL-CSP barriers and challenges• micro SMD package construction• Process / assembly flows• Package selection criteria• Future developments
– Lead-free– Wafer level underfill
• Conclusions• References
13
Feb-02 25
Package Selection• WL-CSPs will replace traditional perimeter leaded packages:
– Initially targets low pin count memory and analog devices; growth highest in wireless portable applications where small form factor and weight are crucial factors
– Growth relies on the existing assembly infrastructure
• Criteria for choosing from the many CSP versions?– From IC supplier: Reduced TAT, inventory size, cost reduction
from transportation and logistics simplification, manufacturability, and scaleability
– From user: Cost, electrical performance, thermal performance, manufacturability (assembly), and reliability
Feb-02 26
Package Selection
0
20
40
60
80
100
120
98 99 00 01Year
Pin
Cou
nt
LaminateCSP
L/F basedCSP (.5/.65 mm)
micro SMD
TSSOPs
MSOPsSOTs
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Feb-02 27
Package Selection(Thermal)
50
100
150
200
250
300
MSOP SOT LLP micro SMD
2-layer board @
0.5 W
2-layer board @
0.5 W
1-layer board @ 1.0 W
w
ith 50x50 mm
Cu
enhancement
2-layer board @
0.7 W
Thermal performance comparison of 8-lead MSOP,
SOT, LLP, and micro-SMD
Junc
tion
Tem
pera
ture
(o C
/W)
Feb-02 28
Package Selection (Manufacturability - PCB Layout)
• Both non-solder mask defined (NSMD) and solder mask defined (SMD) layouts possible
• Prefer NSMD for (1) tighter control on copper etch process, (2) minimal stress concentration, and (3) ease of trace routing
• Recommend 0.5 oz (12 to 15 µm) top layer copper thickness
• Internal reliability data collected with NSMD design, 0.5 oz copper and OSP lead finish
• For Au finish recommend to limit Au flash thickness < 0.5 µm
500
500
160 350
All dimensions are in micronsPCBSolder mask
Copper pad
Micro SMD 8 bump package footprint
Substrate
Solder Mask
Copper Pad
NSMD SMD
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Feb-02 29
Package Selection (Manufacturability - Solder Paste Printing)
• Recommend laser cut process followed by electro-polish to ensure tapering aperture walls to facilitate paste release.
• Recommend aperture 0.300 mm X 0.300 mm square on a 0.125 mm thick laser cut + electro-polished stencil
• Type 3 or finer solder paste is recommended
• With recommended stencil parameters a vertical standoff of ≥ 0.140 mm in the final assembly can be achieved
300
525
525
225
All dimensions are in microns Stencil
Stencil aperture
Micro SMD 8 bump stencil layout
225
300
R 50
Feb-02 30
Package Selection (Manufacturability - Pick & Place)
• Micro SMD can be placed using standard SMT placement m/c
• Part silhouette or bump recognition can be used to position micro SMD
• Micro SMD aligns with land pattern by self-aligning of flip chip solder joints
• Component placement height for the micro SMD should be compensated for its thickness such that minimal force (< 50 gm/bump) is exerted on it when comes in contact with the PCB
• Micro SMD can be assembled without solder paste (flux only) in case of rework procedure
Offset
0
50
100
150
200
250
0 50 100 150 200 250 300
X-Offset (um)
Y-O
ffset
(um
)
O - Self AlignedX - Not Aligned
SMT Process EnvelopeFlip-Chip Process Envelope
Platforms used:Fuji CP60, CP3; Amistar
PlacePro 5800; ESEC Micron 2; Siemens; Universal GSM
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Feb-02 31
Package Selection(Manufacturability - Solder Reflow)
• Micro SMD is assembled using standard reflow process
• Thermal profile at specific board locations is determined
• Recommend Nitrogen purge during solder reflow operation
• The micro SMD is qualified for up to three reflow operations (J-STD-020)
• Rated max peak temperature = 260°C for < 30 sec
• Depending on the type of flux used assembly may be cleaned
Reflow Furnace: Heller 1700N2 Capable
Feb-02 32
Package Selection (Manufacturability - Rework)
• Rework process similar to a standard BGA or CSP part
• Rework process duplicates the original reflow profile
• Automated re-work developed using OK International’s BGA-3000 Rework System (includes localized convection heating with profiling capability, bottom-side pre-heater, and part placer with image overlay alignment)
• Manual rework is possible using soft tip high temperature pick-up tool (e.g. tweezers, vacuum wand) and hot vacuum / air gun
“A Successful Rework Process for Chip-Scale Pack-ages”, Paul
Wood, OK International, Chip Scale Review, Vol. 2, No. 4, 1998.
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Feb-02 33
WL-CSP Failure Modes
• Eutectic bump w/o PI showed Al pad peeled off from die and cratering
• PI showed no significant effect on high lead• PIEU with 3 mil stand-off showed 50% cumulative
failure rate at 550X• High lead deformed much greater than eutectic solder
NPEU
PIHL
NPHL
PIEU
DiePassivation
PIUBM
High LeadEutetic
Solder MaskCu Pad
Al Pad
PCB
Failure Locations
Feb-02 34
Failure Locations
No PI + Eutectic (Al Pad Peel Off) PI + Eutectic (Joint Failed at PCB)
No PI + High Lead (Failed at Intermetallic) PI + High Lead (Failed at High Lead)
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Feb-02 35
Failure Mechanisms
Material Process
Loading Geometry
Solder JointFatigue Life
Substrate
SolderUnderfill
Device Solder maskCTE
Eutectic
High Pb
Adhesion
CTE/EPassivation
Bumping
Encapsulation
VoidsWetting
Voids
Solder Joint
SiliconSubstrate
Underfill
Height
Cap DiaDNP
Size
Thickness
Thermal ShockTemperature Cycle
Time IndependentPlastic Deformation
Time DependentCreep Deformation
Effect of Manufacturing Variables
Cause and Effect for Solder Joint Fatigue
Feb-02 36
Outline• CSP packaging trends• CSP migration toward wafer level processing• WL-CSP barriers and challenges• micro SMD package construction• Process / assembly flows• Package selection criteria• Future developments
– Lead-free– Wafer level underfill
• Conclusions• References
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Feb-02 37
Development of Pb-Free Solders(Ternary Systems)
SYSTEM KNOWN COMPOSITIONS Tm (oC)91.8Sn/3.4Ag/4.8Bi (E) 211
92Sn/3.3Ag/4.7Bi 213-21543Sn1Ag/56Bi (E) 136.583.5Sn/2.5Ag/14Bi 142-218
94Sn/2Ag/4Bi 223-23192.5Sn/1.5Ag/6Bi 188-229
88.0Sn/3.2Ag/8.8In 200-20783.9Sn/4.1Ag/12In 190-20077.2Sn/2.8Ag/20In 178-189
93.6Sn/4.7Ag/1.7Cu (E) 21696.75Sn/1.25Ag/2Cu 224-26096.5Sn/0.5Ag/3Cu 225-296
95.65Sn/0.35Ag/4Cu 227-33294.75Sn/1.25 Ag/4Cu 224-260
Sn-Ag-Bi
Sn-Ag-In
Sn-Ag-Cu
SYSTEM KNOWN COMPOSITIONS Tm (oC)Sn-Ag-Zn 95.5Sn/3.5Ag/1Zn 217
70Sn/20Bi/10In 143-19380Sn/10Bi/10In 163-209
Sn-Bi-Sb 75Sn/19Bi/6Sb 140-220
78Sn/16Bi/6Zn 134-19641.7Sn/57Bi/1.3In 127
Sn-Cu-In 75Sn/0.01-9.5Cu/0.01-6In/addition 209-214
Sn-Bi-Zn
Sn-Bi-In
Feb-02 38
Consortia Recommendations• NCMS: 96.5Sn/3.5Ag; 91.7Sn/3.5Ag/4.8Bi; 42Sn/58Bi• NEMI: Sn/Ag/Cu without Bi is best in reliability (217-221oC)• Brite Euram: 95.5Sn/3.8Ag/0.7Cu (for general purpose soldering);
99.3Sn/0.7Cu; 96.5Sn/3.5Ag; Sn/Ag/Bi• Germany: 96.5Sn/3.5Ag; 99Sn/1Cu• UK (Department of Trade & Industry): options depend on the
applications: – automotive/military Sn/Ag/Cu(Sb)– industrial/telecoms Sn/Ag/Cu, Sn/Ag– consumer Sn/Ag/Cu(Sb), Sn/Ag, Sn/Cu, Sn/Ag/Bi
• Japan Electronics Industry Development Association:– Sn/Ag/Cu (before Pb-free components available)– Sn/Ag/Bi (after Pb-free components available)
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Feb-02 39
Micro SMD Adoption PathSn/Ag/Cu
Sn/Pb
Bump Paste Sn/Pb Sn/Ag/Cu
B: Sn/Ag/CuP: Sn/Pb
B: Sn/Ag/CuP: Sn/Ag/Cu
B: Sn/PbP: Sn/Ag/Cu
B: Sn/Ag/CuP: Sn/Pb
B: Sn/PbP: Sn/Ag/Cu
B: Sn/PbP: Sn/Pb
220oC 260oC
260oC 220oC
260oC 220oC
• Best solder joint performance results with homogeneous combination of lead-free solder.• Standard Sn/Pb packages can be mounted with lead-free paste.• Worst solder joint performance results with lead-free packages with Sn/Pb paste and Sn/Pb reflow.
Feb-02 40
Outline• CSP packaging trends• CSP migration toward wafer level processing• WL-CSP barriers and challenges• micro SMD package construction• Process / assembly flows• Package selection criteria• Future developments
– Lead-free– Wafer level underfill
• Conclusions• References
21
Feb-02 41
Bottom View - Micro SMD 8 I/O with Wafer Level Underfill
Side View - Micro SMD 8 I/O with Wafer Level Underfill
Top View - Micro SMD 8 I/O with Wafer Level Underfill is assembled on PCB
Over View - Micro SMD 8 I/O with Wafer Level Underfill
Wafer Level Underfill
Feb-02 42
Wafer Level UnderfillState of the Art - Conventional Underfill
Process
Process Flow1. Align bumped device with substrate pads2. Reflow assembly to create solder joint3. Dispense underfill and flow under device4. Cure underfill
Solder BumpReflow
Align and Place Underfill CureSUBSTRATE
DEVICE
Underfill Dispense
22
Feb-02 43
State of the Art - Conventional Underfill Process
Process Disadvantages1. Slow - 4-5 minutes (for 6 mm die w/ 3mil gap)2. Performed at device level - can be bottleneck3. Lengthy cure (1-4 hours) - separate process 4. Sensitive to air entrapment (voids)
Material Disadvantages1. Thermoset materials - not reworkable2. Material properties - often at odds w/ process requirements
a. High filler loading - slows flow under dieb. Low filler loading - susceptible to popcorning
3. Cure sensitive properties - short floor life4. Solvent use can cause voiding or bubbling
Wafer Level Underfill
Feb-02 44
State of the Art - Fast Flow Underfill ProcessProcess Disadvantages
Sensitive to material/device wetting characteristics
Underfill of Test Chip Q with full array (13 mm die, 25 µm gap, 250 µm pitch)Material - Dexter FP4511
Underfill of Test Chip Q with mixed array(13 mm die, 25 µm gap, 200 µm & 400 µm
pitches)Material - Dexter FP4511
Wafer Level Underfill
23
Feb-02 45
State of the Art - Fast Flow Underfill Process
Process DisadvantagesSensitive to air entrapment
Large void formed during underfill of Test Chip Q (full array) with
Dexter FP4511
Small void formed during underfill of Test Chip Q (perimeter array) with
Namics U8433
Wafer Level Underfill
Feb-02 46
State of the Art - No Flow Underfill Process
Process1. Dispense underfill over entire bond area2. Align and place die3. Cure underfill
DEVICE
Align and PlaceSUBSTRATE
Underfill DispenseSUBSTRATE Underfill Cure
Wafer Level Underfill
24
Feb-02 47
State of the Art - No Flow Underfill ProcessProcess Disadvantages
1. Alignment difficult - bond pads covered2. Underfill can be retained between solder ball and pad
causing mechanical or electrical joint failure3. Process still performed at package level4. Susceptible to voiding5. Potential to “float” die w/o accurate dispensing
Material Disadvantages1. High reliability materials still in R&D 2. Extremely high CTE (up to 80 ppm/K)3. Potential for moisture absorption4. Non-reworkable
Wafer Level Underfill
Feb-02 48
a) Bumped and Coated wafer
b) Gel Underfill
e) Simultaneously Reflow Solder and Cure Underfill
d) Assemble Die and Substrate
c) Saw Wafer into Die
Substrate
Die
Underfill
Wafer
Wafer
Wafer
Apply heat
d) Apply Underfill
b) Assemble Die and Substrate
c) Reflow Solder
Substrate
Die
a) Saw Wafer into Die
Wafer
flow
Dispensing Needle
Die
Substrate
e) Cure Underfill
Die
Substrate
Apply heat
Die
Apply heat
Apply heat
Substrate
Die
Proposed Process FlowCurrent Process Flow
Underfill
Substrate
Screen Printing
• High viscosity - material does not flow through the screen ahead of the squeegee and ruin the print resolution
• Pseudoplastic - material flows through the screen under high pressures exerted by the squeegee
• High solids - more efficient material transfer; thicker films; reduced waste
Processing Issues
25
Feb-02 49
Stress-Induced Warpage
• Wafer curvature - planarity is critical to the dicing process.– Caused by CTE mismatch
between “soft cured” underfill and the silicon wafer.
– Primary factors: wafer thickness, film thickness, modulus of wafer, modulus of film, type of coating (e.g., blanket vs. patterned).
Substrate
Die
No contact betweensolder ball and pad
Wafer - Small CTE
Coating - Large CTE
Wafer
Coating Large Shrinkage
Small Shrinkage
Wafer
Coating
Stress on Wafer
a)No stress at gel temperature
b)Shrinkage at ambient temperature
c)Stress at ambient temperature
Processing Issues
Feb-02 50
Wafer Warpage
- Wafer: 200 mm (8”)- Nominal thickness: 0.77
mm- Underfill coating: 0.11
mm (4 mils)- Two underfills: 1 and 10
GPa
Curvature can reach 0.2x (E=1 GPa) to 2.6X (E=10 GPa) of a 200 mm wafer nominal thickness
0
1
2
3
0 1 2 3 4 5 6
COATING PATTERN
NO
RM
ALIZ
ED C
UR
VATU
RE
Processing Issues
26
Feb-02 51
Dicing-Induced Damage
• Potential problems encountered during dicing @ 30-40 kRPM– Chipping: minimal on coated
side; potentially high on back side.
– Blade loading: accelerated blade wear / life; irregular cut widths; heat generated caused melting of the material into the kerf.
– Film delamination: poor adhesion accentuated by the shearing of the wafer.
Blade
KerfUnderfill
Tape
Hub
Wafer Negligible impact
Chipping @ die edges
Irregular kerf width/bladeloading
Reflow of material into kerf
Film delamination
Processing Issues
Feb-02 52
Solder Wetting Under Constrained Conditions
• Wetting of solder pad -potentially poor / incomplete pad wetting due to the presence ofthe underfill surrounding the solder balls.
• Primary factors: surface tension of underfill / solder, weight of die, external force, coating thickness.
Silicon die
SubstrateUnderfill
Initial State
At Temperature T
Final State
Processing Issues
27
Feb-02 53
Outline• CSP packaging trends• CSP migration toward wafer level processing• WL-CSP barriers and challenges• micro SMD package construction• Process / assembly flows• Package selection criteria• Future developments
– Lead-free– Wafer level underfill
• Conclusions• References
Feb-02 54
Conclusions• WL-CSP is driven by imperatives such as:
– Packaging cost– Production, handling, and testing logistics– Functionality, performance, size, and weight– Integration and interconnect density
• WL-CSP such as the micro SMD is highly suitable for low pin count analog applications (cellular phones, cameras, flash minicards, portable products, etc.)
• Criteria for selection of a particular form factor and pin count will depend on both IC suppliers and end customers readiness
• Next advances in lead-free and wafer level underfill
28
Feb-02 55
Outline• CSP packaging trends• CSP migration toward wafer level processing• WL-CSP barriers and challenges• micro SMD package construction• Process / assembly flows• Package selection criteria• Future developments
– Lead-free– Wafer level underfill
• Conclusions• References
Feb-02 56
References• General WLP books/articles:
– TechSearch CSP/BGA Update Service– Prismark (market research, trends)– Electronic Trend Publications (market research, trends)– IEEE Transactions on Advanced Packaging, Vol. 23, No. 2, May 2000
issue.– “Wafer Level Packaging Has Arrived,” P. Garrou, Semiconductor
International, pp. 119-128, October 2000.– Chip Scale Packaging, J. Lau and S. W. R. Lee, Eds., McGraw Hill (1999).– “Wafer Pre-Applied Encapsulant Materials and Processes,” Q. Tong, S-H
Hong, L. Nguyen, H. Nguyen, and A. Negasi, 52nd Electron. Comp. & Tech. Conf., May 28-31, San Diego, CA (2002).
– “Lead-free WL-CSP: Assembly and Reliability,” V. Patwardhan, N. Kelkar, and L. Nguyen, 52nd Electron. Comp. & Tech. Conf., May 28-31, San Diego, CA (2002).
• TC-18: Wafer Level Packaging– http://cpmt.org/tc/tc18.html