VYSOKÉ ÚýENÍ TECHNICKÉ V BRN FAKULTA ELEKTROTECHNIKY … · the art of the IGBT transistor...
Transcript of VYSOKÉ ÚýENÍ TECHNICKÉ V BRN FAKULTA ELEKTROTECHNIKY … · the art of the IGBT transistor...
VYSOKÉ ÚČENÍ TECHNICKÉ V BRNĚ FAKULTA ELEKTROTECHNIKY A KOMUNIKAČNÍCH TECHNOLOGIÍ
ÚSTAV VÝKONOVÉ ELEKTROTECHNIKY A ELEKTRONIKY
Ing. ZIAD NOUMAN
FIELD PROGRAMMABLE GATE ARRAYS USAGE IN INDUSTRIAL AUTOMATION SYSTEMS
UŽITÍ PROGRAMOVATELNÝCH HRADLOVÝCH POLÍ V SYSTÉMECH
PRUMYSLOVÉ AUTOMATIZACE
TEZE DIZERTAČNÍ PRÁCE
Obor: Silnoproudá elektrotechnika a elektroenergetika Školitel: doc. Ing. BOHUMIL KLÍMA, Ph.D.
KeywordsFault detection and diagnosis (FDD), Fault Tolerant Control (FTC), Field ProgrammableGate Arrays (FPGA), Insulated-Gate Bipolar Transistor (IGBT), gate drive, ADC,monitoring, PC board, redundancy, Very High Speed Integrated Circuit Hardware De-scription Language(VHDL), Verilog, Fast Fourier Transform (FFT), DDR2SDRAM,Industrial automation.
Klıcova slovaDetekce poruch a diagnostika (FDD), Rızenı odolne vuci porucham (FTC), Pro-gramovatelne hradlove pole (FPGA), Tranzistor IGBT, Budic, Analogove-digitalnıprevodnık, monitoring, PC deska, redundance, Jazyk VHDL, Verilog, Rychla Fouriero-va transformace (FFT), DDR2-SDRAM, Prumyslova automatizace.
Mısto ulozenı pracePrace je k dispozici na Vedeckem oddelenı dekanatu FEKT VUT v Brne, Technicka3058/10, 616 00 Brno.
Copyright c© 2015 Author: Ing.Ziad Nouman
Contents
1 Introduction 11.1 Motivation and Objectives . . . . . . . . . . . . . . . . . . . . . . . 2
2 Background and State of the Art 32.1 Present State in Inverter Diagnosis . . . . . . . . . . . . . . . . . . . 4
3 Proposed IGBT Gate Driver Architecture 73.1 Gate Driver Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 83.2 Data Exchange SPI Protocol . . . . . . . . . . . . . . . . . . . . . . 83.3 The proposed IGBT Gate Driver . . . . . . . . . . . . . . . . . . . . 103.4 Design of the Proposed IGBT Gate Driver . . . . . . . . . . . . . . . 11
3.4.1 Design of the Driver Stages of Proposed IGBT Gate Driver . . 113.4.2 Design of the Power Supply System for the Proposed IGBT
Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.4.2.1 Design of the Insulated DC/DC Converters . . . . . 14
3.4.3 The Proposed Analog to Digital Converters Design . . . . . . 14
4 FPGA Board Design for IGBT Control and Diagnosis 164.1 Proposed FPGA Board Design . . . . . . . . . . . . . . . . . . . . . 16
4.1.1 PC Layout of the Proposed FPGA Board . . . . . . . . . . . 17
5 Stages Control Signals Generator Design 195.1 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6 Conclusion 266.1 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Bibliography 28
ii
Chapter 1
Introduction
Today’s, industrial automation systems are highly complex networks of embed-ded systems consisting of many sensors, drives, controllers, and intelligent I/O de-vices. Recently, Field Programmable Gate Arrays (FPGAs) are used throughout in-dustrial automation systems to add intelligence, flexibility, and high precision control.Their applications include motion control, machine to machine communications, mo-tor drives, diagnosis and fault-tolerant control, smart energy and smart grid, big dataanalytic, etc.
Generally, when the FPGAs are used in motor drives, they implement complex con-trol algorithms and modulation switching. Additionally, they can provide functionsfor fault protection of motor such open circuit and short circuit. In other words, theFPGAs usage is limited to motor control and modulation switching, but they are notused to detect the problems of inverter components during the switching process. Forexample, the monitoring of the IGBT switching process (turn-on, turn-off) in a powerinverter may lead to predict and diagnose the faults before the complete degradationoccurrence in the drive system.
Mostly, no methods exist for continuous monitoring of inverter switching transistorcondition or other parts of power inverter such as DC link capacitance, leakage resis-tance, or terminals contact resistances etc. Diagnostic methods based on continuouscondition monitoring, which were developed for mechanical vibration monitoring orfor many other fields - for example ball bearing condition monitoring or partial dis-charges in motor winding, do not exist for IGBT transistors proper operation. Thequality of switching process is possible to observe only on transients, when the tran-sistor switches on or off. Based on the study presented in chapter 2, it could be notedthat several factors affect the switching transient in the transistor: transistor switchingspeed, gate resistance, gate current, gate voltage, DC link capacitance, snubbers ca-pacitance, etc. Among these quantities, which can be measured, are collector-emittervoltage VCE , gate-emitter voltage VGE and gate current IG. These quantities are onlymeasurable in the IGBT gate driver in the inverter. Based on the quantities measure-ments and their quantitative evaluation, the degree of degradation in the power compo-
1
CHAPTER 1. INTRODUCTION 2
nents (IGBT transistors, diodes, capacitors, etc.) may be predicted, where the charac-teristic of these components change during the degradation. Therefore, the diagnosticmethods, which depend on measuring and monitoring the IGBT quantities during theswitching process in the gate drive circuits, should lead to predict the critical degree ofthe components degradation. Accordingly, the maintenance can be scheduled to avoidthe failure of the components during the operation.
As long as the IGBT gate driver is used to measure and monitor the required quan-tities for the diagnosis, a new hardware for the gate driver is required. In addition to itsbasic functions (turn-on, turn-off), the gate driver should be able to perform measure-ments, recording, and mathematical analysis during the IGBT switching process. Thedigital signal processing for the analysis and recording is required. Generally, FastFourier Transform (FFT) or Wavelet transform are used for this purpose. Therefore,the implementation of programmable devices, which are placed directly on the gatedriver, are required. The programmable devices may be Field Programmable GateArrays (FPGAs) or microprocessors.
1.1 Motivation and ObjectivesThe idea is to integrate the diagnostic functions into the IGBT gate driver circuits.These functions should allow analysis of the required quantities in the IGBT transistorand its gate driver. The purpose is to measure and monitor these signals during theIGBT switching process. The quantitative evaluation of the measured parameters,which are recorded and analyzed using programmable devices, can indicate the degreeof the degradation. As a result, the IGBT failure can be predicted and it would be ableto plan the targeted service (replacement of specific IGBT, driver, capacitor).
The aim is to design a hardware of the IGBT gate driver, which would allow achiev-ing the previous properties.The structure of the proposed IGBT gate driver can be summarized as follows:
1. Multiple gate stages outputs for realization of variable gate resistance by sequen-tial switching. It allows realization of liner charging of gate capacitance delayedsequential switching signals are generated in the FPGA and are programmed inHDL language.
2. Programmable devices (FPGAs) for recording and analysis of the digital signals.
3. Multiple power supplies for IGBT gate stages and for FPGA feeding.
4. Driver interface to inverter control system with data exchange capability exceptstandard PWM signal. The insulated SPI interface is used for this purpose.
Chapter 2
Background and State of theArt
The scope of this chapter is focused on the IGBT transistor basics (structure, switch-ing operation, control) [18] [8] [46] [21]. This chapter also reviews the current state ofthe art of the IGBT transistor faults, fault detection and diagnosis and the fault-tolerantcontrol.
The IGBT turn-on and turn-off are controlled by the gate voltage, and the speed ofswitching is determined by the gate current. The gate drive circuit feeds the IGBT gatesignals. Therefore, it is considered as an interface between the logic signals generatedfrom the controller and the signals of IGBT gate [5]. There are two types of gatedrive circuits, namely, voltage drive and current drive. The gate drive circuit generatesa positive voltage +VGE during the turn-on, and a negative voltage −VGE during theturn-off. Moreover, the gate drive circuit should control the time change rate di/dt ofthe IGBT collector current to avoid excessive Electro-Magnetic Interference (EMI),and it should control the time change rate dVCE/dt of the IGBT collector-emitter volt-age to avoid the IGBT latch up [24] [25].
Equation 2.1 is used to calculate the peak value of the current flowed to charge anddischarge the gate during the IGBT switching.
IGP =+VGE +
∣∣−VGE∣∣
RG +Rg(2.1)
where RG is the external gate resistor and Rg is the internal gate resistor.A small gate resistor reduces the switching times and switching losses, but this maycause a high surge voltage. The value of the gate resistor has a significant impact onthe turn-on speed of IGBTs, while it barely affects the turn off speed.
The average value of the drive current IG can be calculated by Equation 2.2.
+IG =−IG = fsw×(∣∣+Qg
∣∣+∣∣−Qg∣∣) (2.2)
3
CHAPTER 2. BACKGROUND AND STATE OF THE ART 4
where +Qg is the gate charge from 0V to +VGE and −Qg is the gate charge from−VGE to 0V. The gate drive power Pd(on) required to turn on the IGBT is given by
Pd(on) = fsw×[1
2×(∣∣+Qg
∣∣+∣∣−Qg∣∣)× (∣∣+VGE
∣∣+∣∣−VGE∣∣)] (2.3)
supposing that the gate drive power Pd(o f f ) required to turn off the IGBT is equal tothe power Pd(on), then the gate drive power Pd required to drive the IGBT switching iswritten as the following
Pd = Pd(on)+Pd(o f f ) = fsw×[(∣∣+Qg
∣∣+∣∣−Qg∣∣)×(∣∣+VGE
∣∣+∣∣−VGE∣∣)]. (2.4)
2.1 Present State in Inverter DiagnosisThe components of a drive system depend on their function and the place of use.Therefore, the faults and their causes may differ from system to another. The twocomponents most prone to failure in the drive system are electrolytic filtering capac-itors [22] and power devices, but 38% of faults in the drive systems occur due to thefailure of power devices during the switching operation [26].
The causes of failure in the drive system were briefly discussed in [1].The IGBT open circuit faults, which are defined as electrical causes, may be caused
by the lifting of bonding wires [3] [27], or by the gate driver failure [38] [36]. The opencircuit fault is not considered a fatal fault, but it can lead to another fault in healthyparts. Therefore, it is necessary to get rid of these faults to protect the system fromthe complete failure. Several detection methods for open circuit faults were developedin [17] [30] [41].
The short-circuit (SC) is considered the usual fault mode of semiconductors, be-cause the short-circuit faults are very destructive. Therefore, the protection and diag-nosis system requires special measures to turn off the drive system immediately. TheIGBTs SC withstand time, which can be in the range of 6 µs to 10 µs, is dependent ontheir type and structure. If the protection circuit failed to turn off the IGBT during thewithstand time, the IGBT will be destroyed.
Generally, all the output stages of the proposed gate drive circuits have a gateresistor that is split into two resistors RG(on) for switching turn-on, and RG(o f f ) forswitching turn off. This allows controlling and optimizing the switching turn on andswitching turn off separately [11] [10].
The desaturation technique is a common method for detection the fault occurrencein the IGBT device [9] [16]. The detection of SC fault is achieved, if the collectoremitter voltage VCE rises above 5-8 volts during the on-state operation. The SC condi-tion indicates that the collector current IC has exceeded the normal value. This methodis simple because it uses only a diode for sensing the fault.
A new IGBT protection circuits are proposed in [14] [42] to accelerate the faultdetection time.
CHAPTER 2. BACKGROUND AND STATE OF THE ART 5
All proposed SC protection circuits include a soft turn off technique to reduce volt-age spike caused by the high current falling rate, where the soft shutdown methodincreases the system reliability under the SC conditions [7].
Recently, SC protection circuits based on the gate voltage monitoring were pro-posed [23] [34].
The IGBT turn-on and turn-off are treated as transient phenomena. During theswitching transient of the IGBT devices, the power dissipation and switching stressincrease. Therefore, the switching speed is required to reduce the effect of these phe-nomena on the IGBT performance. In other words, the IGBT protection against thetransient surge is required [37] [15] [33].
Recently, the fault detection and diagnosis in drive systems depend on the onlinemonitoring and measurement [29] [45], where the extracted online information can beused for the design of fault tolerant control system (FTCS). Few works have describedthe ability of online fault detection and diagnosis [2].
The IGBT devices and any power devices used in the drive system are prone to hightemperatures during the operation. Therefore, the protection of IGBT against degra-dation is important. There are variety of methods used for measuring the temperatureof the IGBT device [6] [19].
The fault detection and isolation (FDI), fault detection and diagnosis (FDD), andfault-tolerant control (FTC) and the interaction between them are considered a suitableway for improving reliability and flexibility of drive systems. In addition, the cost ofrepair and maintenance decreases highly.
The FTCS used in IGBT inverters depends on the redundant components. TheFTCS improves both the reliability and the safety of technical systems. Additionally,the FTCS reduces the maintenance costs, which are very expensive, and it improvesthe life time of the drive system. In the literature, several approaches have dealt withthe fault tolerant control (FTC) in drive systems that are fed by IGBT inverters [43][12].
Based on the previous review, it is noted that the control units used in the drivesystems play the key role in FDD and FTC. Generally, the control unit is composedof hardware and software. The hardware includes the gate driver, protection and di-agnosis circuits, controller, whereas the software includes all algorithms for FDD andFTC. In order to minimize the time between the fault detection and diagnosis, us-ing the field programmable gate arrays (FPGAs) is the new solution for the FTCSs,power electronics, and drive applications [28]. FPGAs can perform networking andcontrol support simultaneously. A single FPGA can do the work of dozens of mi-crocontrollers. Therefore, the microcontroller is going to disappear with the FPGAappearance. The industrial control systems based on the FPGAs design proved theirflexibility, reliability, capacity, and fast response in difficult conditions.
Nowadays, complex functions for power electronic systems are implemented usingthe FPGA controller design. The FPGA controller was used in the application ofswitching power converters [13]. The use of FPGAs in voltage source inverters fed
CHAPTER 2. BACKGROUND AND STATE OF THE ART 6
induction machines has been discussed in the literature. The proposed digital controlcircuit for multilevel multipulse source voltage converter, which is presented in [31][35], is based on the FPGA design. Additionally, a lot of researches discussed thedesign and implementation of PID controllers using FPGA [47] [47].
Generally, standard drivers are built according to the architecture shown in Fig-ure 2.1.They include usually an output stage, secondary logic, protection circuits and sec-ondary part of insulated power source on the secondary side (side of power transis-tor). Whereas on the primary side, there are primary parts of power source and primarylogic. The control PWM signals and power supply are transferred through the insula-tion barrier to the secondary side and transistor/driver error signals are transferred tothe primary side.
PW
M S
ign
al
Insu
lati
on
OutputStage
SecondarySide Logic
Fau
lt S
ign
al
Insu
lati
on
Power SupplySecondary Side
Power SupplyPrimary Side
PrimarySide Logic
PWMSignal
FaultSignal Protection
Circuity
Single IGBT Module
Figure 2.1: Standard driver architecture [20].
The Insulation barrier must have high du/dt immunity, low parasitic capacity andstatic insulating capability according to the application field of the driver. The insula-tion barriers are usually realized using opto-couplers or signal transformers. There arenow high speed logic isolators. Since the problem of isolation is still the main issuefor designers and researchers, other techniques for isolation barriers were presented inthe literature, for example the proposed method in [4] discussed the implementation ofan IGBT control signal by wireless transmission, while the proposed method in [39]used a printed transformer which can insulate a voltage of 10kV.
Chapter 3
Proposed IGBT Gate DriverArchitecture
From Figure 2.1 in section 2.1, the development of the gate driver architecture isnecessary for purposes of the proposed diagnosis in the developed gate driver. Theproposed gate drive circuit architecture is shown in Figure 3.1, where the analog mea-surements of required quantities are implemented on the secondary side of the pro-posed gate driver. The measured quantities are VCE , VGE , and IG. Additionally, the
RShunt IL
Sn
ub
ber
3 Parallel Stages
R G(EXT)
Desaturation Protection
BUFFIN
BUFFIN
BUFFIN
DSPMEM
MEM
MEM
Memory
BUFFOUT
µPSPI
ADCs
High Power
IGBT-ModuleProposed FPGA Board Design
IG
VCE
VGE
IL
DSP
DSP
Stages Control Signals
Fault Signal
PWM Signal
Figure 3.1: The Architecture of Proposed Gate Driver with ADCs Devices for Moni-toring and diagnosis [32].
load current IL can also be measured. The transients of these quantities can be evalu-ated. Then, the quality of switching process can be monitored.
7
CHAPTER 3. PROPOSED IGBT GATE DRIVER ARCHITECTURE 8
3.1 Gate Driver InterfaceThe data transfer of PWM control signal and back transfer of fault signal are assumedusing separate insulated channels, as shown in Figure 3.2. Separate fault signal is not
PW
M S
ign
al
Insu
lati
on
OutputStage
SecondarySide Logic
Fau
lt S
ign
al
Insu
lati
on
Power SupplySecondary Side
Power SupplyPrimary Side
PrimarySide Logic
FaultSignal Protection
Circuity
Single IGBT Module
ADCs
VGE VCEIG
RAM/FLASHMemory
FPGA Based
Controller
SP
I In
terf
ace
SP
I In
terf
ace
Insu
lati
onCLOCK
SELECT/SYNC
DATA IN
DATA OUT
IL
Cu
rren
t S
enso
r
PWMSignal
Figure 3.2: Interface Between One IGBT Gate Driver and Main FPGA Controller.
necessary, because the error information is also transferred through the data interface.However, in the case of requirement for switching-off other transistors of invertersimultaneously, it is necessary to separate the fault signals.
The bi-direction data synchronized with the inverter control unit (main controller)require a high communication speed, reliability, and simplicity of implementation.There are many types of serial communication interface, which can be used for thispurpose. A Synchronous Peripheral Interface (SPI) is used in the drive system, asshown in Figure 3.2.
3.2 Data Exchange SPI ProtocolData exchange is realized between the main controller of the inverter and the gatedriver FPGA by a simple communication protocol for SPI as shown in Figure 3.3.
CHAPTER 3. PROPOSED IGBT GATE DRIVER ARCHITECTURE 9
DATA ADDR
EMPTY
MESSAGEID
DATA WRITE CHECKSUM
STATUS WORD CHECKSUMEMPTY
CLK
DATA IN
DATA OUT
SELECT/SYNC
(a) Data frame for writing parameter into one gate driver memory.
DATA ADDR EMPTYMESSAGEID
DATA READ
CHECKSUM
STATUS WORD CHECKSUMEMPTY
CLK
DATA IN
DATA OUT
SELECT/SYNC
(b) Data frame back reading of parameter or an individual variable.
EMPTYMESSAGEID
CHECKSUM
STATUS WORD CHECKSUM
EMPTY
CLK
DATA IN
DATA OUT
SELECT/SYNC
DATA ADDRCYCLIC
DATA 1PERIODIC
DATA nPERIODIC
DATACYCLIC
(c) Data frame for periodic data exchange between driver and inverter controller.
Figure 3.3: Proposed SPI data transfer protocol.
CHAPTER 3. PROPOSED IGBT GATE DRIVER ARCHITECTURE 10
3.3 The proposed IGBT Gate DriverFigure 3.4 shows the detail of the proposed IGBT gate driver for one channel. The
DC/DC Converter
5V
/2
.5 A
Parallel Gate
FPGA
15V/0.4A -8V/0.4A
3.3VSix Stages control
Signals
Voltages Monitoring 3.3V
10 BitOR
100 MHz
100 MHz
100 MHz
10 BitOR
OR10 Bit
15V /0.4 A
-8V /0.4 A
Of Upper Channel
Clock SourcesFrom FPGA
Dedicated
Circuits
Voltage Reference
VCE
3
2
1
1
2
3
4
VGE
IG
IL
Upper
Bottom
IGBT Dual Module
C
E
C
E L
C: CollectorE: EmitterG: GateL: Load
G
G
To Analog Digital Converters
(ADCs)
Switching Control
15 V External
DC Power Supply
Reg1
Reg2
Reg316V/1.6A
To Gate
Stages
Output of Range (1 bit)
Drive Stages
ADC105 MSPS
ADC105 MSPS
ADC105 MSPS
AGND
AGND
AGND
Insu
lato
r
PWM1
SELECT/ SYNC
CLK
DATA IN
DATA OUT
Main Controller
XADC
4
Figure 3.4: IGBT gate driver detail for one channel in IGBT module.
IGBT gate driver for one channel, whether the upper or the bottom, includes the fol-lowing components:
• FPGA based controller: It receives the measured digital signals, such as IC, V GE,IG and VCE , from high speed parallel ADCs across buffer functions using a Verilogprogram.
• High speed parallel analog digital converters: High speed (105MSPS), high res-olution (10bit) ADCs are used in the design. Their analog inputs are the outputsof the dedicated circuits for the quantities which are going to be measured. TheADCs are operated with the internal reference of 1V or 0.5V, this depends theconfiguration. The ADCs clocks are generated by the gate driver FPGA usingVerilog code and another tools. The clock frequency range must be from 50MHzto 105MHz, this is based on the required sampling rate.
• Voltage references.
CHAPTER 3. PROPOSED IGBT GATE DRIVER ARCHITECTURE 11
• Parallel gate drive stages: They are used to control the external gate resistorsduring the turn on/off.
• Stages control signals: They are used for controlling the parallel stages inputs. Averilog code can be written for generating these control signals which assert delaytimes between the gate stages during the IGBT switching.
• Insulator: A high speed logic isolator could be used.
• High speed communication: An SPI interface can be used to achieve the exchangedata between the main controller and the used FPGAs based controller which areused to analysis the measured digital signals in the gate driver.
• Dedicated circuits: They can be voltage dividers,operational amplifiers, anti-aliasing filters, etc.
• Insulated DC/DC converter: The zero voltage zero current (ZVSZCS) push-pullresonant topology and regulators will be designed for this purpose.
3.4 Design of the Proposed IGBT Gate Driver
3.4.1 Design of the Driver Stages of Proposed IGBT Gate DriverFigure 3.5 depicts the block diagram of the driver stages for the upper and bottomtransistor of dual IGBT module. These stages are divided into two channels: Upperchannel for the upper transistor, and bottom channel for the bottom transistor. Each
RShunt IL
Sn
ub
ber
First Driver stage
Second Driver stage
Third Driver stage
First Driver stage
Second Driver stage
Third Driver stage
FP
GA
ba
sed
co
ntr
oll
er
Bottom Channel
Upper Channel
UPA1
UPA2
UPA3
UPB1
UPB2
UPB3
BOTA1
BOTA2
BOTA3
BOTB1
BOTB2
BOTB3
IGBT Dual Module-U DC
+UDC
FP
GA
ba
sed
co
ntr
oll
er
First Stage
Control Signals
Second Stage
Control Signals
Third Stage
Control Signals
First Stage
Control Signals
Second Stage
Control Signals
Third Stage
Control Signals
Figure 3.5: Block diagram of the parallel driver stages used in the proposed gate drivecircuit.
CHAPTER 3. PROPOSED IGBT GATE DRIVER ARCHITECTURE 12
channel is composed of three parallel driver stages. The stages output of each channelfeeds its own transistor in the dual IGBT module. These stages are responsible for theIGBT switching (turn-on, turn-off) during the operation. Figure 3.6 shows the driver
15V
15V
-8V
330Ω
3.3V
Channel
GND
Channel
GND
AX
BX
POWER Stage X Output
Stage Control Signal
1KΩ
NPN
NPN
PNP
PNP
N-MOSFET
N-MOSFET
P-MOSFET
P-MOSFET
RG(on)
RG(off)
Q1X
Q2X
Q3X
Q4X
Q5X
Q6X
Q7X
Q8X
RAX
RBX
Stage Control Signal
Figure 3.6: Schematic diagram of single driver stage in one channel.
stage structure in each channel where X indicates the stage number. The transistorP-channel MOSFET Q1X is used for the IGBT turning on, while the transistor N-channel MOSFET Q2X is used for the IGBT turning off. The turn-on voltage of theIGBT is approximately +15V, and the turn-off voltage is about −8V. Accordingly,the voltage drop along the charging/discharging path can be calculated as follows
4VGE =+15V− (−8V) = 23V
The source pin of the transistor Q1X is connected to the positive supply of 15 V, andthe source pin of the transistor Q2X is connected to the negative supply −8V. There-fore the Q2X is turned off, if its source becomes more negative than the gate voltage.
The maximum IGBT gate current IG is determined according to the external resis-tors, where the external gate resistors RG(on) limit the gate current IG(on) during theturning on, and the resistors RG(o f f ) limit the gate current IG(o f f ) during the turningoff. Moreover, the gate driver with this structure can control the du/dt and di/dt.
The Q1X switching (turn-on/off) is controlled by the emitter follower (Q3X, Q4X)with single power supply, whereas the Q2X switching is controlled by the emitterfollower (Q5X, Q6X). This follower is fed by positive voltage +15V for the collectorof the NPN transistor Q5X and from the negative voltage −8V for the collector of thePNP transistor Q6X.
CHAPTER 3. PROPOSED IGBT GATE DRIVER ARCHITECTURE 13
The small signal transistors N-MOSFET Q7X, and P-MOSFET Q8X are consid-ered as an input stage. They are controlled digitally by the FPGA controller. Eachstage consists of two transistors controlled by different signals in the FPGA controller,as shown in Figure 3.7. The structure of this gate driver allows controlling the gate re-sistors RG(on) and RG(o f f ). The digital signals used for switching the small transistorshave a delay time td which allows controlling the gate resistors sequentially during theIGBT operation (turn-on, turn-off). According to the datasheet of the IGBT module
Time
3.3
V M
AX
Turn onTurn off
Six
Sta
ges
Con
trol
Sig
nals
td1
td2
Q71
Q72
Q73
Q83
Q82
Q81
td3
td4
PWM
Signal
Q81
Q81
Q81
Figure 3.7: The digital signals used for controlling the input stages.
FF1000R17IE4 [40], and based on the Equation 2.1 in chapter 2, the peak value ofcurrent, which has to be provided by the first gate stage in each channel, for chargingand discharging the gate during the IGBT switching, is
IGP(stage) =15+ |−8|
5+1.5≈ 3.54A
3.4.2 Design of the Power Supply System for the Proposed IGBTGate Driver
Figure 3.8 illustrates the block diagram of the power supply system used for the pro-posed IGBT gate driver, where two insulated DC/DC converters are used. Each one
CHAPTER 3. PROPOSED IGBT GATE DRIVER ARCHITECTURE 14
DC
DC
DC
DC
16V/1.6A 15V/0.4A Regulator
-8V/0.4A Regulator
5V/2.5A Regulator
15V/0.4A Regulator
-8V/0.4A Regulator
5V/2.5A Regulator
Upper Channel
16V/1.6A
Bottom Channel
15V
For turning off The IGBT
For turning off The IGBT
For turning on The IGBT
For turning on The IGBT
FPGA Controller
3.3V
FPGA Controller
3.3V
IGBT Gate Drive
Figure 3.8: Block diagram of power supply in the proposed gate drive.
provides isolated output 16 V/ 1.6 A. The output of each converter feeds the followingregulators:
• Positive regulator with output 15V/0.4A.
• Negative regulator with output −8V/0.4A.
• Positive regulator with output 5V/2.5A for the FPGA controller.
In addition, the proposed gate driver requires a power supply with output voltage3.3V, which can be fed from the FPGA controller.
3.4.2.1 Design of the Insulated DC/DC Converters
Two ZVSZCS push pull resonant converters are provided in the design, where eachconverter feeds its own channel in the IGBT gate drive circuit with an output power25.6W and a current 1.6A. Figure 3.9 depicts the schematic circuit of the push pullresonant converters with bridge rectifiers used for the proposed design.
3.4.3 The Proposed Analog to Digital Converters DesignAs previously mentioned, the important quantities, which are measured during theIGBT switching process (turn-on, turn-off), are IG, VGE and VCE . The ADC devicesconvert the analog signals of the measured quantities to digital signals for analysis
CHAPTER 3. PROPOSED IGBT GATE DRIVER ARCHITECTURE 15
22Ω
22Ω
Q1
Q2
22KΩ 22KΩ
T1
T2
D1
D3
D2
D4
D5
D7
D6
D8
Resonant Cap
Toroidal Transformer
Upper Channel
Bottom Channel
16V/1.6A
PWM1
PWM2
SG3525ADW
15 V/ 2 A
I2
I1
+ -Cr1
+Cr2 -
+
-
+
-
+
-
+
-
LLHP
LUHP
VOUT
VOUT
VS2
VS1+
-
-
+
RT CT
56
RD
7
16V/1.6A
Cout
Cout
Figure 3.9: The schematic circuit of the push pull DC/DC converters used in powersupply system.
and processing. The quantitative evaluation determines the IGBT degree of degrada-tion. Generally, the IGBT switching process is between 2-4 µs. Therefore, the ADCconverters must be fast for digitizing the input signals during the switching processwithin this period. Figure 3.10 represents the block diagram of the ADC converters(AD9215) interface to the FPGA controller. A simple HDL code can be used to sam-
DATA [9:0]
DATA [9:0]
DATA [9:0]
OR
OR
OR
3.3V
10 Pins
10 Pins
10 Pins
External Clock
Generator
FFT
Core
FFT
Core
FFT
CoreGND
GND
Pin out
Pin out
Pin out
GND
150 MHz
FPGA Controller
AVDD
AVDD
AVDD
105 MSPS
105 MSPS
105 MSPS
100 MHz
100 MHz
100 MHz
ADC_CLK
ADC_CLK
ADC_CLK
VGE
VCE
IG
Clo
ckin
g
Wiz
ard
Figure 3.10: ADC Devices interface to the FPGA controller.
ple ADCs data at FPGA inputs. In addition to HDL code, the User Constraints File(UCF) is required to specify the pins location in the FPGA controller.
Chapter 4
FPGA Board Design for IGBTControl and Diagnosis
4.1 Proposed FPGA Board DesignFigure 4.1 shows the block diagram of the FPGA board used for the control and thediagnosis during the switching of the IGBT transistor.As can be seen from Figure 4.1 the hardware features are:
Kintex-7
XC7K70T-FBG484
Power supplies
1V, 1.8V,3.3V,0.9V
SPI FLASH
MEMORY
DDR2 SDRAM 128
MB
USB to UART Bridge
Clock Oscillator 150
MHz
Clock Oscillator 150
MHz
Two Leds
FPGA
Reconfiguration Push
Button Switch
JTAG Connector
2X15 pin Header
Strip 2mm pitch
connector(J4)
2X9 pin Header
Strip 2mm pitch
connector(J12)
2X50 pin 0.8mm Pitch Board to
Board connector (J11)
2X50 pin 0.8mm Pitch Board to
Board connector (J10)
Power connector with
switch and led
Figure 4.1: Block diagram of proposed FPGA design.
• Kintex-7 XC7K70T-FBG484.
16
CHAPTER 4. FPGA BOARD DESIGN FOR IGBT CONTROL AND DIAGNOSIS17
• DDR2 SDRAM (Micron MT47H128M8CF-25).
• SPI PROM (N25Q128 1.8/3.3V).
• USB to UART Bridge (CP2103).
• Two clock crystal oscillators 150MHz, 3.3V (TXC 7W-150.000MBB-T OSC).
• Power Supplies 1V/2.5A, 1.8V/1A, 0.9V/2.5A, 3.3V/1.5A.
• JTAG.
• Two 2X50 pin 0.8mm pitch board to board connectors (FX18-100S-0.8SH).
• Two leds.
• 2X9 pin header strip 2mm pitch connector.
• 2X15 pin header strip 2mm pitch connector.
• FPGA Reconfiguration push button switch.
• Power connector with switch and status led.
4.1.1 PC Layout of the Proposed FPGA BoardFigure 4.2 shows the printed circuit of the FPGA board (PCB). The number of layersused in the design is six as shown in Figure 4.3. The components are placed on thetop and bottom sides. Plated Through Hole (PTH) are used to connect between thelayers. The inner layers L3 and L4 are signal layers. They include the DDR2 signals(ADDR(0:13), DQ, DQS, control signals). Single-ended signals and differential pairswere also routed onto these inner layers.
In addition, polygon GND was used for shielding. The outer layer L2 is used asa reference plane (GND system), and it plays a significant role for EMI shielding.The outer layer L5 is used for the power distribution system (PDS). The polygonplanes were used to achieve the required power nets which allow carrying heavy powersupply currents for the FPGA device.
The power supplies of the FPGA device must not vary more than ±5% [44]. Thevoltage regulators VRs keep the power supplies constant. These VRs were placed ontothe top side. They are placed near the FPGA device to reduce the losses. The polygonplanes are provided. This design allows drawing a heavy current between layers intothe FPGA device.
In addition, the bypass filters were used to reduce the noise in the current which canbe supplied into the FPGA device.
CHAPTER 4. FPGA BOARD DESIGN FOR IGBT CONTROL AND DIAGNOSIS18
112.192mm
80.1
37m
m
128MB
FLASH
MEMORY
USB to UART
BRIDGE
TWO LEDS
CLK OSCILLATOR
150MHz
KINTEX-7
XC7K70T-FBG484
CONNECTOR
J12
CONNECTOR
J4
CONNECTOR
J11CONNECTOR
J10
DDR2 SDRAM
128MB
JTAG
CONNECTOR
VCCINT
VCCAUX
VTT
VCCO
FPGA
Reconfiguration
Push Button Switch
VREFP_0
Figure 4.2: Top and bottom view of the proposed FPGA board.
Top Layer
Prepreg (0.126mm)
L2(GND)
Core (0.2mm)
L3
Prepreg (0.54mm)
L4
Core (0.2mm)
L5(POWER)
Prepreg (0.126mm)
Bottom Layer
Total Height (1.416mm)Total Height (1.416mm)
Prepreg (0.126mm)
Core (0.2mm)
Prepreg (0.54mm)
Core (0.2mm)
Prepreg (0.126mm)
Top Layer
L2(GND)
L3 (Signals)
L4 (Signals)
L5 (Power)
Bottom Layer
Figure 4.3: The layer stack-up for 6 layers used in the FPGA board.
Chapter 5
Stages Control SignalsGenerator Design
Figure 5.1 represents the schematic block of the SCS generator for one channel in theproposed IGBT gate driver. A Verilog code is created for this purpose. Six stagescontrol signals are generated for one channel1. Two up counters and two comparators
PWM Signals
Generator
Verilog Module
CLKCLKOUT100 MHz
SCS_Q71
RST RSTSCS_Q72
SCS_Q73
SCS_Q81
SCS_Q82
SCS_Q83
EnDe-bouncing
Signal
PWM SignalFrom Main Controller
PWM1
Figure 5.1: Schematic block of the SCS generator in gate driver FPGA.
are used to generate the required signals, as shown in Figure 5.2. The maximum countvalue of the counters is determined by the duty cycle of the PWM wave which isgenerated by the main controller. As can be seen in the Figure 5.2, when the PWMsignal of the main controller has a rising edge, the stage control signal SCS Q71 isasserted by the SCS generator and the first counter begins to count. The count value ofthe counter1 is compared with the delay time td1. When the count value is greater thanthe value of td1, the stage control signal SCS Q72 is asserted, and the stage controlsignal SCS Q73 is confirmed when the value of the counter1 is greater than the delaytime td2. Accordingly, the external gate resistors are controlled by switching the stagestransistors Q71, Q72 and Q73 in sequence with delay times td1 and td2.On the other hand, the stage control signal SCS Q81 is asserted and the counter2
1This channel can be upper or bottom channel for the proposed IGBT gate driver.
19
CHAPTER 5. STAGES CONTROL SIGNALS GENERATOR DESIGN 20
Q71
t
Q72
Q73
Q81
Q82
Q83
First
Up C
ounte
r
Secon
d Up C
ounte
r
PWM
From Main Controller
Data Control
Stag
es c
on
tro
l Sig
nal
s
Delay time 4
Delay time 3Delay time 1
Delay time 2
Figure 5.2: Up counters operation with SCS generator outputs and PWM edges.
begins to increase, when the PWM signal of the main controller has falling edge. As aconsequence, the stage control signal SCS Q82 is asserted when the count value of thecounter2 is greater than the td3 and the stage control signal SCS Q83 is high when thecount value of the counter2 is greater than the td4. This allows controlling the externalgate resistors during the IGBT turn-off.
As long as the clock frequency of the SCS generator fclk is 100MHz, the timeperiod tclk is
tclk =1
f clk(5.1)
=1
100= 10ns.
Accordingly, the number of clock cycles, which is required to implement a delay time,could be calculated as follows
NCC =delaytime
tclk. (5.2)
Assuming that the IGBT switching frequency fsw is 5kHz, td1 = td3 = 0.85 µs, andtd2 = td4 = 1.5 µs2. The number of clock cycles can be calculated as follows
NCCtd1 =0.85·10−6
10·10−9 = 85cycles.
2This is only an example,
CHAPTER 5. STAGES CONTROL SIGNALS GENERATOR DESIGN 21
NCCtd2 =1.5·10−6
10·10−9 = 150cycles.
Figure 5.3 illustrates the stages of assertion of the stages control signals during the op-eration. The stages control signals of the transistors Q71, Q72 and Q73 are confirmedwhen the PWM signal is high, where the SCS Q72 is asserted after 85cycles, and theSCS Q73 is confirmed after 150cycles, as shown in Figure 5.3a. On the other hand,the stages control signals of the transistors Q81, Q82 and Q83 are asserted when thePWM signal is low, as shown in Figure 5.3b.
Divider1
Divider2
200,400 ns 200,600 ns 200,800 ns 201,000 ns 201,200 ns 201,400 ns 201,600 ns 201,800 n
(a) Digital signals of the transistors Q71..3 during their switching process.Divider1
Divider2
300,400 ns 300,600 ns 300,800 ns 301,000 ns 301,200 ns 301,400 ns 301,600 ns 301,800 ns
(b) Digital signals of the transistors Q81..3 during their switching process.
Figure 5.3: Digital signals of the stages transistors with the delay times.
The En signal is asserted using an external switch which is de-bounced using digitalcircuits.
Figure 5.4 shows all digital signals of the SCS generator and other parts during theoperation.
SCS Generator
End Divider
0 us 100 us 200 us 300 us 400 us 500 us
Figure 5.4: Digital signals of SCS generator during the operation.
CHAPTER 5. STAGES CONTROL SIGNALS GENERATOR DESIGN 22
5.1 Experimental ResultsThe schematic block shown in Figure 5.5 is an assembly of several designs whichwere tested on the proposed FPGA board. Verilog top level is used to interface tothe blocks. This design is used to test the SCS generator. All the components ofthe design are built using the Verilog language. The structure of SCS generator wasmentioned before. The other components are used to generate the PWM signal fortesting. The main frequency is 150MHz, it is the input frequency of the clock wizard.The clock wizard generates two frequencies 100MHz and 5MHz. The first one is usedby all components whereas the second one is used to control data by two externalpush buttons. As can be seen from Figure 5.5, the design is composed of inputsand outputs signals. The User Constraint File (UCF) is used to select the locationof these signals3. Generally, ChipScope core is added to the design for monitoringthe signals. Figure 5.6 illustrates the digital signals of the SCS generator which aremonitored using ChipScope core. As can be seen from Figure 5.6, when the PWMsignal has rising edge, the signals SCS Q71, SCS Q72, and SCS Q73 are confirmedsequentially, for controlling the IGBT gate resistors during the turn-on. On the otherhand, when the PWM signal has falling edge, the signals SCS Q81, SCS Q82 andSCS Q83 are also asserted sequentially, for controlling the IGBT gate resistors duringthe turn-off.
Additionally, the power supplies of the IGBT gate driver FPGA and the internaltemperature of the FPGA device can be monitored during the SCS generator opera-tion. As can be seen from Figure 5.7, the current Die temperature of the FPGA deviceis always 37.5 ◦C, the current value of VCCIN and VCCBRAM are 0.996V, and thepresent value of VCCAUX is 1.796V. This means that all the values are in the accept-able range.
3Xilinx PlanAhead software is used for this purpose.
CHAPTER 5. STAGES CONTROL SIGNALS GENERATOR DESIGN 23
CLK
_div
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clkd
ive
refc
lk
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t
clk
cont
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data
cont
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data
bt(1
:0)
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CLK
Enab
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RS
T
cont
rolle
d_da
ta(1
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nt
clk
enab
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rese
t
coun
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ard
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CLK
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Com
para
tor
com
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Dat
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clk
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Con
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SCS_
Gen
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CLK En
PW
M1
RST
SCS_
Q71
SCS_
Q72
SCS_
Q73
SCS_
Q81
SCS_
Q82
SCS_
Q83
Top_
Leve
l:1
Top1
CLK
PWM
SW1
SW2
SCS
_Q71
SCS
_Q72
SCS
_Q73
SCS
_Q81
SCS
_Q82
SCS
_Q83
Top_
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l_S
CS
_sig
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MC
ontro
ller:1
Top_
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l_S
CS
_sig
nals
_with
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MC
ontro
ller
SWC
OTR
OL(
1:0)
CLK
_IN
PBR
RES
T
SW_E
N
SC
S_Q
71
SC
S_Q
72
SC
S_Q
73
SC
S_Q
81
SC
S_Q
82
SC
S_Q
83
Figu
re5.
5:Sc
hem
atic
bloc
kof
the
Ver
ilog
top
leve
lfor
test
ing
CHAPTER 5. STAGES CONTROL SIGNALS GENERATOR DESIGN 24
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Chapter 6
Conclusion
The usage of Field Programmable Gate arrays (FPGAs) in industrial automation sys-tems of factories are very wide. However, their usage are limited in the control appli-cations and drive systems, and few research are concerned withe the FPGAs usage inthe diagnosis and fault detection. Therefore, the thesis is focused on the FPGAs usagein the fault diagnosis of inverter IGBT transistors during the switching process. A newIGBT gate driver architecture is developed to integrate the diagnostic functions. Thesefunctions allow analyzing the IGBT quantities IG, VGE and VCE during the switchingprocess. For this purpose, high speed parallel ADC converters are proposed. Multi-ple gate stages are designed for realization of variable gate resistance by sequentialswitching. Three parallel gate driver stages are used for one transistor in the powerinverter. The usage of these parallel driver stages allows controlling the external IGBTgate resistors during the IGBT switching process. Driver interface to inverter controlsystem with data exchange is designed, where the insulated SPI interface is used forthis purpose.
FPGA board was designed and integrated to the IGBT gate driver. The FPGA de-vice used in the design has two types of I/O Banks, high-performance (HP) and high-range (HR) I/O Banks. One of HP I/O Banks is used to interface a DDR2SDRAMmemory to the FPGA device with a voltage 1.8V. The HR I/O Banks are designed tosupport a range of I/O standards with voltages from 1.2V to 3.3V. These Banks areused to interface the high speed parallel ADCs of the IGBT gate driver to the FPGAdevice. The FPGA board includes differential signals and single signals which canbe provided from board to board connectors. The proposed FPGA board supportstwo configuration modes: JTAG/boundary-scan configuration mode and Master SerialPeripheral Interface (SPI) flash configuration mode (x4). These modes are used todownload the designed software on the FPGA device. Two clock sources are used toclocking the FPGA device. The clocks frequency is 150MHz. The FPGA device hasalso an integrated XADC which is composed of a dual 12 bit,1MSPS, ADCs. TheseADCs can be configured to sample in continuous or event driven modes. Additionally,the XADC is used to monitor the power sources of FPGA banks and it can also be usedto monitor the power system of the IGBT gate driver stages. An USB to UART bridge
26
CHAPTER 6. CONCLUSION 27
device is used to interface the PC to the FPGA device. The FPGA board was testedand the signals outputs were proper.In addition to control the IGBT transistor switching, the FPGA board acquires thedata from the ADCs converters during the switching event, where the FPGA devicecontains all the DSP tools for analyzing and quantitative evaluation.
Multiple power supplies for IGBT gate stages and for FPGA feeding were designed.Two insulated DC/DC converters are used to feed the drive system, where regulatorsare used to adjust the DC/DC converters outputs.
The Stages Control Signals (SCS) were generated using Verilog code. The de-signed generator generates six signals which are synchronized with the PWM signalwhich is generated by the main controller of the drive system. The input frequencyof the generator is 100MHz. The clocking wizard which is provided by the IP coresof FPGA devices is used to generate the generator frequency from the external clocksource. Global reset is used to reconfigure the entire software when an error occurs.Additionally, an enable signal is used to activate the generator. When the PWM signalhas rising edge, three signals are generated sequentially with predefined delays1, forcontrolling the gate driver stages during the IGBT transistor turn-on, and when thePWM signal has falling edge, three signals are also generated sequentially for con-trolling the gate driver stages during the IGBT transistor turn-off.The SCS generator is designed to generate six signals for three gate driver stages.This gate driver can control one IGBT transistor switching during turn-on/off, but thecapability of HDL language (Verilog, VHDL) allows building at least 12 SCS gener-ators which can be used in the fault-tolerant applications or in another applications ofindustrial automation.
6.1 Future WorkThe author of the doctoral thesis suggests to explore the following:
• It would be interesting to develop the IGBT gate driver with integrated diagnosticfunctions to include three phase inverter with diagnosis and fault-tolerant control.
• It would be important to develop the FPGA board to include differential clocksource which accelerates the speed of analyzing during the process.
• The implementation of mentioned steps above, requires the development of soft-ware to interface the inverter with drivers FPGAs to the main controller.
1These delays can be set in accordance to the requirements of used IGBT.
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Curriculum Vitae Ing. Ziad Nouman 00420773260963 @ [email protected] Nationality: Syrian Place of birth: Eskebleh
ACADEMIC EDUCATION Since 2010 Brno University of Technology – Czech Republic
Ph.D. student
2004 – 2005
Tishreen University - Lattakia Higher Study Diploma in Electrical Engineering The field of (electrical power systems)
2000 – 2004
Tishreen University - Lattakia Degree of Electrical Engineer. Section of Power Engineering.
1998 - 2000 Industrial Institute of Electricity and Mechanics – Damascus.
PLACES OF INTEREST Reading, Sport, learning languages, Tourism
LANGUAGES Arabic Maternal language English Good Czech Good
SPECIAL KNOWLEDGE Operating Systems Windows 98, Windows me, Windows 2000,
Windows XP Professional, Windows 7.
Office Microsoft Office System
Languages of Programming C, HDL (Verilog, VHDL), Matlab.
Software of Design Altium Designer, Cadence, Microcontroller Design, FPGA Design.
BIBLIOGRAPHY 34
AbstractThis doctoral thesis deals with the usage of Field Programmable Gate Arrays (FPGAs)in a diagnosis of power inverters which use the IGBTs transistors as switching devices.It is focused on the IGBT gate drives and their structures. As long as the transientphenomena and other quantities such as IG, VGE , VCE shows the IGBT degradationduring the switching process (turn-on, turn-off), a new IGBT gate driver architectureis proposed for measuring and monitoring these quantities. Quick measurements andmonitoring during the IGBT switching process require high sampling frequencies.Therefore, high speed parallel ADC converters (> 50MSPS) are proposed.
The thesis is focused on the FPGA design (hardware, software). A new FPGAboard is designed for desired functions implementation such as IGBT driving usingmultiple stages, IGBT monitoring and diagnosis, and interfacing to inverter controller.
AbstraktTato disertacnı prace se zabyva vyuzitım programovatelnych hradlovych polı (FPGA)v diagnostice menicu, vyuzıvajıcıch spınanych IGBT tranzistoru. Je zamerena nabudice techto vykonovych tranzistoru a jejich struktury. Prechodne jevy velicin, jakojsou IG, VGE , VCE behem procesu prepınanı (zapnutı, vypnutı), mohou poukazovatna degradaci IGBT. Pro merenı a monitorovanı techto velicin byla navrzena novaarchitektura budice IGBT. Rychle merenı a monitorovanı behem prepınacıho dejevyzaduje vysokou vzorkovacı frekvenci. Proto jsou navrhovany paralelnı vysoko-rychlostnı AD prevodnıky (> 50MSPS).
Prace je zamerena prevazne na navrh zarızenı s FPGA vcetne hardware a software.Byla navrzena nova deska plosnych spoju s FPGA, ktera plnı pozadovane funkce, jakoje rızenı IGBT pomocı vıcenasobnych paralelnıch koncovych stupnu, monitorovanı adiagnostiku, a propojenı s rıdicı jednotkou menice.