Vmc Report

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SUBMITTED BY: SULOCHNANA GAUTAM

MNNIT,ALLAHABAD


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To Whom It May Concern

This is to certify thatSULOCHANA GAUTAM havesuccessfully completed their project on:

VHDL code for VMC in VHDL

With all its functionalities during the summer training coursefromSemiconductor Technologies, Vedant theirworkwas authenticand conduct was diligent & sincere. The projectsatisfies the norms of the company and was developed under

the guidance ofMs. Anupam Maurya ,Mr. Amit ChandraMr. Satish Chandra & Mr. Anil Kumar.

Certificate is awaited

CERTIFIED BY:

MR. AMIT CHANDRA Mr.Sachin Kr. Kanodia

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Semiconductor TechnologiesVEDANT

VLSI DESIGN EDUCATION AND TRAINING LUCKNOW CENTRE


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(Project Guide) (Head)

ACKNOWLEDGEMENT

No academic endeavor can be single handedlyaccomplished. This work is no exception.

At the outset, we would like to record our gratitude to Mr.

Sachin Kr.Kanodia for initiating us into this training.

We sincerely acknowledge our thanks to our project

guide Ms. Anupam Maurya, Mr. Amit Chandra, Mr.Satish

Chandra & Mr. Anil Kumar for their valuable suggestions

and time to time consultation.

Last, but not the least, we would like to thank all the staff

of VLSI Design Department, Semiconductor Laboratory

(SCL), Vedant, Lucknow especially Ms. Charu Agarwal for

their kind cooperation and assistance during our trainingperiod.

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PREFACE

The evolution of Very large scale integration (VLSI) technology has

developed to the point where millions of transistors can be integrated

on a single die or chip where integrated circuits once filled the role

of subsystem component partitioned at analog-digital boundaries.

They now integrate complete systems on a chip by combining both

analog-digital functions. Complementary metal oxide semiconductors

technology has been the mainstay in mixed signal implementations

because it provides density and power savings on the digital side,

and a good mix of components for analog design.

Due in part to the regularity and granularity of digital circuit computer

aided design (CAD) methodologies have been very successful in

automating the design of digital systems given a behavioraldescription of the function desired. Such is not the case for analog

circuit design. Analog design still requires a hands on design

approach in general. Moreover many of the design techniques used

for discrete circuits are not applicable to the design of analog /mixed

signal VLSI circuits. It is necessary to examine closely the design

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process of analog circuit and to identify those principles that will

increase design productivity and the designers chances for success.

CONTENT Page no.

SEMICONDUCTOR TECHNOLOGIES 06

VEDANT 08

INTRODUCTION TO VLSI 09

INTRODUCTION TO VHDL 12

IEEE LIBRARIES 14 INTRODUCTION TO VMC 15

VHDL CODE AND RTL SCHEMATIC 18

WAVEFORM 41

BIBLIOGRAPHY 42

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SEMICONDUCTOR TECHNOLOGIES-

VEDANTAN ISO 9001:2000 CERTIFIED INSTITUTION

Semiconductor Technologies has always been in sync withthe future. It has understood and appreciated the needs ofIndia, its people and its ever-growing industry. Over the lastsix 20 years tell the saga of VEDANT contribution in leadingthe national effort in the vital areas of microelectronics.

M/s Semiconductor Technologies-VEDANT is Indiaspremier VLSI Design & Embedded System Designorganization since 2002. While VEDANT is Indias pioneer inthe field of VLSI Design & Embedded System Design andTesting. VEDANT is providing Education & Training on VLSIDesign & Embedded System Design through state-of-the-artlab facilities, equipped with the Industry Standard tools. VLSI

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Design / Embedded Systems Design Engineer design suchSilicon chipsmaking a career in VLSI Design / ESD is highlyrespected & rewarding one. Furthermore we would like tobring in your notice that VEDANT is a member of IndianSemiconductor Association as well. SemiconductoR

Technologies-VEDANT (Now an ISO 9001: 2000 CertifiedInstitution) is center for the training crafted in VLSI/ESDeducation module followed with VLSI Design software alongwith the FPGA programming & 8051 Microcontroller kit.

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VEDANTVEDANT (VLSI design and training) is one of the prestigious

projects of SCL, a pioneer with vertically integrated facility in the

country.

SCL VEDANT program covers the complete spectrum of VLSI

design inclusive of front end, back end and provides of

exposure to the IC fabrication process. Industry standard CAD tools

are used for the purpose of training backed up by project work under

the guidance of experts.

VEDANT (LUCKNOW CENTER) is the institute, which provides

training in VLSI design to students. The working environment is

concentrated on front-end design process. It runs two programsPG diploma in VLSI designing of four months and certificate

course of two months. It also provides Summer & Winter Training

in VLSI Design orEmbedded System.

It has an advanced lab which is equipped with latest industry

standard Electronic Design Automation (EDA) and FPGA tools

and 8051 Development Kits inclusive of

Model Sim 6.0a

Xilinx tools

FPGA Kit

8051 Development Kit8


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Keil Software

Flash Magic (Rom burning)

INTRODUCTION TO VLSI

For any given design, if the architecture of the fixed LSIand VLSI blocks suit the application then the design time isconsiderably shortened. When a one-chip microprocessor isnot quite suitable, micro programmable architectures canoften provide sufficient customization.

Micro programmable architectures, such as bit-slice,allow a closer control over the architecture but not totalcontrol. The basic building blocks are still designed by the

chip manufacturer for generic applications. Bit-slicearchitectures include interruptible sequencers and 32-bit

ALUs.The customization of the bit-slice modules to an

application is done through customer-designed moduleinterconnection, the implemented commands and theirsequences. The commands or instruction set is called themicro-program for the design.

ASIC (VLSI, VHLSI)The 1980s saw the acceptance of ASICs ( ApplicationSpecific Integrated Circuits), VLSI devices large enough toallow designers to implement architectures that were suited tosolving the design problem rather than forcing onearchitecture to solve everything. It was the natural extensionto the bit-slice architectures, where some control ofarchitecture was possible through microprogramming butwhere the basic building blocks were fixed designs.

Not far behind the ASIC and ASIC developments,multimedia and design integration saw a need to incorporateanalog functions into digital systems. For years the trend hadbeen away from analog design as a chosen career and nowthere was a shortage of design engineers. First came massivere-training of internal staff as companies struggled to cope.

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Then came the creation of Electrically Programmable AnalogCircuit (EPAC) and related devices.

Application- specific solutions also includes thestandard product mix where the market for a device is solarge that product are developed specific to a mass

application. PCI controllers is an example where oneinterface controller is targeted to handle the interface for manydevices and device types, the control problem tailored to thedevice via programming.

The application-specific customization of the designsolution allows the designer to have the creative power of agate-level breadboard design while keeping the productionadvantages of VLSI.

Over the years, there has been an evolution of theuniversal building blocks used by logic circuit designers. In themid-1960s, there were SSI gates; NAND, NOR, EXOR, andNOT or INVERT. In the early 1970s, MSI blocks, registers,decoders, multiplexers, and other blocks made theirappearances. In the late 1970s, ALUs (arithmetic logic units)with on-board scratchpad registers, interrupt controllers, microprogram sequencers, ROMs/PROMs, and other LSI devicesup to and including a complete one-chip microprocessor

(control, ALU and registers) became readily available. (Andfrom this the PC was born.)

SSI (small scale integration) is defined here to includechips containing approximately 2-10 gates. MSI (mediumscale integration) is used for chips containing 20-100 gates.LSI (large scale integration) ships contain 200-1000 gates,with the upper limit continually extending as VLSI (very largescale integration) became a reality. In the mid-1980s, ASIC

(application-specific integrated circuits) ranged from 1000gates to 20,000 gates (bipolar technology) or 200,000 (CMOStechnology).

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INTRODUCTION TO VHDL

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Excel VHDL is a user friendly windows based packagewhich encapsulates the powerful Simily VHDL engine.

A typical VHDL source file contains zero or more designunits. Examples of design units are entity, architecture,package, etc. When a VHDL source file is compiled, theresults of successful compilation are stored in a library .So, ineffect; the design units contained within the VHDL source fileare placed in a library.

A design unit that has been compiled into one library canreference other designs units in any other library through theuse of clauses and library statements.

In VHDL, the current working library is always calledwork. When using a VHDL compiler or simulator, there isalways a concept of a current working library. If no particularlibrary is specified as a current working library, the currentworking library is assumed to be work. You can associatethe work library with any other library.

There are two kinds of design units: Primary andSecondary design units. The design units of type entity,package and configuration are primary design units. Designunits or type architecture and package body are secondarydesign units. Secondary design units are always associatedwith a primary design unit. Secondary units typically containthe implementation of their primary units.

SIMPLE RULES TO REMEMBER

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All primary units in a given library must have unique names. Note:VHDL language actually allows the entity to have the same name, asone of its configurations but VHDL Similar requires that all primaryunits have unique names in a given library. All secondary units for agiven primary unit must also be named uniquely. A primary designand its associated design unit must both reside in the same library.

IEEE LIBRARIES

There is a VHDL standard library with a special name std. Thislibrary and its contents (the packages standard and textio) are built

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into the tools and cant be controlled. This also means that you canthave user defined library called std.

The other IEEE libraries are stored I lib folder of the installationdirectory. The source code is present in IEEE folder and the compiledcode is present in the IEEE.SYM folder. You may view the source

code folder to see the definitions for use in your code.

Introduction to VMC

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A vending machine provides various snacks, beverages, and other

products to consumers. The idea is to vend products without a

cashier. Items sold via vending machines vary by country and region.

Patrons may also buy nonfood items like newspapers or DVDs. One

company selling the latter is Red box in the United States.

In some countries, merchants may sell alcoholic beverages such as

beer through vending machines, while other countries do not allow

this practice (usually because of dram shop laws).

Cigarettes were commonly sold in the United States through these

machines, but this practice is increasingly rare due to concerns about

underage buyers. Sometimes a pass has to be inserted in the

machine to prove one's age. In some countries like Germany and

Japan, by contrast, cigarette machines are still common. Vending

machines were used at airports from the 1950s well into the 1970s to

sell life insurance policies covering death in the event that the buyer's

flight crashed. Such policies were quite profitable, because the risk of

any given flight crashing was (and remains) very low, but this practice

gradually disappeared due to the tendency of American courts to

strictly construe such policies against their sellers, such as Mutual

Omaha.

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The VMC i.e. the Vending Machine Controller is a basic machines

which we used to see in our daily life at many places e.g. at malls,

shops, etc.

These machines are basically installed to dispense the commodity

i.e. used regularly. It is for anything like ATM machines (whose basic

work to dispense money after verification of the authorized person),

may be for cold drinks where the person does not have to wait for the

shopkeeper to open the shop and then only get the required things.

So, the basic idea behind this project to supply a particular kind of

things as per the request of the customer, here we are implementing

a simple basic idea to develop the vending machine.

But it doesnt mean that the idea stops here it just give us a brief

about the approach and we can further enhance the idea upto any

level.

The vending machine is totally based on different states, which we

engineers used to call the state machine or FSM.

This project is based on this and it is for a cold drink i.e. it dispense

the cold drink only after the customer puts money into this.

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Assumptions:

The circuit reads signals from a coin input unit and sends outputs to

a change dispensing unit and a drink dispensing unit.

Here are the design parameters:

This project assumes that only one kind of soft drink is dispensed. This is a clocked design with CLK and RESET input signals.

The price of the drink is 10 rupees.

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CODE for VMC

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library IEEE;use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;

--use UNISIM.VComponents.all;

entity vmc_mc_xtrnal isPort ( clk,rst : in STD_LOGIC;

cancel :in bit;

coin:in integer:=0;ocoin1,ocoin2,ocoin5,ocoin10 : out integer;

fdisp : out STD_LOGIC);

end vmc_mc_xtrnal;

architecture Behavioral of vmc_mc_xtrnal is

signal change :integer;signal disp:std_logic;

signal emp: bit;

component controller is

Port ( clk,rst : in STD_LOGIC ;emp,cancel:in bit:='0';

coin:in integer:=0;

disp : out STD_LOGIC:='0';

change :out integer:=0);end component;

component money_changer isPort ( clk,rst : in STD_LOGIC;

coin : in integer:=0;

change : in integer:=0;

ocoin1,ocoin2,ocoin5,ocoin10 : out integer:=0);end component;

component cold_storage is

Port ( clk,rst : in STD_LOGIC;disp: in STD_LOGIC;

fdisp : out STD_LOGIC;emp : out bit:='0');end component;

begin

A1: controller port map(clk,rst,emp,cancel,coin,disp,change);A2:money_changer port map(clk,rst,coin,change,ocoin1,ocoin2,ocoin5,ocoin10);

A3:cold_storage port map(clk,rst,disp,fdisp,emp);

end Behavioral;

CONTROLLER

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.

--library UNISIM;--use UNISIM.VComponents.all;

entity controller is

Port ( clk,rst : in STD_LOGIC ;

emp,cancel:in bit:='0';coin:in integer:=0;

disp : out STD_LOGIC:='0';

change :out integer:=0);end controller;

architecture Behavioral of controller istype state is (s0,s1,s2,s3,s4,s5,s6,s7,s8,s9);

signal st:state;

signal chan:integer:=0;

begin

process(st,clk,cancel,coin,rst,emp)

begin

if rst='1' then chan


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change


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disp


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disp


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chan


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disp


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coin2


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if coin2>0 and coin1>0 then

ocoin2


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ocoin10=2 and coin1>=1 thenocoin2


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ocoin10=6 thenocoin1


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ocoin10=4 thenocoin2


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ocoin5


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coin1


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begin

if rst='1' then

fdisp


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Internal Schematic diagram of VMC

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RTL for controller of VMC

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internal of controller36


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RTL for money changer of VMC37


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Internal of money changer

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RTL for cold storage of VMC

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Internal of cold storage

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WAVEFORM OF VMC

BIBLIOGRAPHY41


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Following is the list of books from which help has been taken

for the completion of this project.

1 VHDL-PRIMER J.Bhasker

2 MODERN DIGITAL ELECTRONICS R.P.Jain

3 DIGITAL DESIGN MorisMano

Vmc Report

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